Re: Preparing isar-cip-core for RZ/Five

[Jan Kiszka <jan.kiszka@siemens.com>]

On 05.10.22 00:30, Prabhakar Mahadev Lad wrote:
> Hi Jan,
> 
>> -----Original Message-----
>> From: Chris Paterson <Chris.Paterson2@renesas.com>
>> Sent: 03 October 2022 21:13
>> To: Jan Kiszka <jan.kiszka@siemens.com>; Prabhakar Mahadev Lad
>> <prabhakar.mahadev-lad.rj@bp.renesas.com>; Hung Tran
>> <hung.tran.jy@renesas.com>
>> Cc: cip-dev <cip-dev@lists.cip-project.org>
>> Subject: RE: Preparing isar-cip-core for RZ/Five
>>
>> Hello Jan,
>>
>>> From: Jan Kiszka <jan.kiszka@siemens.com>
>>> Sent: 03 October 2022 19:36
>>>
>>> Hi Chris,
>>>
>>> after getting qemu-riscv64 ready (patches will come tomorrow), I
>> also
>>
>> Huzzah
>>
>>> had a quick look at the RZ/Five eval board you shared with us. But
>>> that raised a couple of questions, maybe you can help:
>>
>> I can try :)
>>
>>>
>>>  - Why is the default U-Boot hard-wired to a very special boot mode?
>> I'm
>>>    missing standard distro boot - which would include UEFI as well.
>>
> Its just that we used the standard configs which we use for BSP releases. Looking at the u-boot code enabling distro boot should be straight forward as EFI is supported on RISC-V
> 

Exactly - that's why I don't understand that you are not doing it
already. The default setup should be generic, easily extensible. But now
your users need to compile an own firmware and flash it, just to have a
standard boot procedure. And you won't be SystemReady this way as well.

Jan

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