* [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
[not found] <20230721035225.4986-1-xujianghui@cdjrlc.com>
@ 2023-07-21 3:53 ` sunran001
0 siblings, 0 replies; 13+ messages in thread
From: sunran001 @ 2023-07-21 3:53 UTC (permalink / raw)
To: alexander.deucher; +Cc: amd-gfx, dri-devel, linux-kernel
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun <sunran001@208suo.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index ddc488251313..0cf564ea1ed8 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -429,10 +429,10 @@ int amdgpu_pm_load_smu_firmware(struct
amdgpu_device *adev, uint32_t *smu_versio
int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool
enable);
int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev,
uint32_t size);
int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev,
uint32_t size);
-int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,enum
pp_clock_type type,
- uint32_t *min,uint32_t *max);
-int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,enum
pp_clock_type type,
- uint32_t min,uint32_t max);
+int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, enum
pp_clock_type type,
+ uint32_t *min, uint32_t *max);
+int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, enum
pp_clock_type type,
+ uint32_t min, uint32_t max);
int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum
smu_event_type event,
uint64_t event_arg);
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
@ 2023-07-21 3:53 ` sunran001
0 siblings, 0 replies; 13+ messages in thread
From: sunran001 @ 2023-07-21 3:53 UTC (permalink / raw)
To: alexander.deucher; +Cc: dri-devel, amd-gfx, linux-kernel
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun <sunran001@208suo.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index ddc488251313..0cf564ea1ed8 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -429,10 +429,10 @@ int amdgpu_pm_load_smu_firmware(struct
amdgpu_device *adev, uint32_t *smu_versio
int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool
enable);
int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev,
uint32_t size);
int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev,
uint32_t size);
-int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,enum
pp_clock_type type,
- uint32_t *min,uint32_t *max);
-int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,enum
pp_clock_type type,
- uint32_t min,uint32_t max);
+int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, enum
pp_clock_type type,
+ uint32_t *min, uint32_t *max);
+int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, enum
pp_clock_type type,
+ uint32_t min, uint32_t max);
int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum
smu_event_type event,
uint64_t event_arg);
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
2023-07-21 3:53 ` sunran001
@ 2023-07-21 15:59 ` Alex Deucher
-1 siblings, 0 replies; 13+ messages in thread
From: Alex Deucher @ 2023-07-21 15:59 UTC (permalink / raw)
To: sunran001; +Cc: alexander.deucher, dri-devel, amd-gfx, linux-kernel
On Thu, Jul 20, 2023 at 11:53 PM <sunran001@208suo.com> wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
The description doesn't match what the patch is doing.
Alex
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> index ddc488251313..0cf564ea1ed8 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> @@ -429,10 +429,10 @@ int amdgpu_pm_load_smu_firmware(struct
> amdgpu_device *adev, uint32_t *smu_versio
> int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool
> enable);
> int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev,
> uint32_t size);
> int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev,
> uint32_t size);
> -int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,enum
> pp_clock_type type,
> - uint32_t *min,uint32_t *max);
> -int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,enum
> pp_clock_type type,
> - uint32_t min,uint32_t max);
> +int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, enum
> pp_clock_type type,
> + uint32_t *min, uint32_t *max);
> +int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, enum
> pp_clock_type type,
> + uint32_t min, uint32_t max);
> int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
> int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum
> smu_event_type event,
> uint64_t event_arg);
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
@ 2023-07-21 15:59 ` Alex Deucher
0 siblings, 0 replies; 13+ messages in thread
From: Alex Deucher @ 2023-07-21 15:59 UTC (permalink / raw)
To: sunran001; +Cc: alexander.deucher, amd-gfx, dri-devel, linux-kernel
On Thu, Jul 20, 2023 at 11:53 PM <sunran001@208suo.com> wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
The description doesn't match what the patch is doing.
Alex
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> index ddc488251313..0cf564ea1ed8 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> @@ -429,10 +429,10 @@ int amdgpu_pm_load_smu_firmware(struct
> amdgpu_device *adev, uint32_t *smu_versio
> int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool
> enable);
> int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev,
> uint32_t size);
> int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev,
> uint32_t size);
> -int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,enum
> pp_clock_type type,
> - uint32_t *min,uint32_t *max);
> -int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,enum
> pp_clock_type type,
> - uint32_t min,uint32_t max);
> +int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, enum
> pp_clock_type type,
> + uint32_t *min, uint32_t *max);
> +int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, enum
> pp_clock_type type,
> + uint32_t min, uint32_t max);
> int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
> int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum
> smu_event_type event,
> uint64_t event_arg);
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
2023-07-24 9:08 ` sunran001
@ 2023-07-24 21:59 ` Alex Deucher
-1 siblings, 0 replies; 13+ messages in thread
From: Alex Deucher @ 2023-07-24 21:59 UTC (permalink / raw)
To: sunran001; +Cc: alexander.deucher, amd-gfx, dri-devel, linux-kernel
Applied. Thanks!
On Mon, Jul 24, 2023 at 5:08 AM <sunran001@208suo.com> wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
> .../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h | 21 +++++++------------
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> index eadbe0149cae..eb694f9f556d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> @@ -41,8 +41,7 @@
> #define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
> Table Version 0.2
> #define SMU_13_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
> Clock Table Version 1.00
>
> -enum SMU_13_0_7_ODFEATURE_CAP
> -{
> +enum SMU_13_0_7_ODFEATURE_CAP {
> SMU_13_0_7_ODCAP_GFXCLK_LIMITS = 0,
> SMU_13_0_7_ODCAP_UCLK_LIMITS,
> SMU_13_0_7_ODCAP_POWER_LIMIT,
> @@ -62,8 +61,7 @@ enum SMU_13_0_7_ODFEATURE_CAP
> SMU_13_0_7_ODCAP_COUNT,
> };
>
> -enum SMU_13_0_7_ODFEATURE_ID
> -{
> +enum SMU_13_0_7_ODFEATURE_ID {
> SMU_13_0_7_ODFEATURE_GFXCLK_LIMITS = 1 <<
> SMU_13_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
> SMU_13_0_7_ODFEATURE_UCLK_LIMITS = 1 <<
> SMU_13_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature
> SMU_13_0_7_ODFEATURE_POWER_LIMIT = 1 <<
> SMU_13_0_7_ODCAP_POWER_LIMIT, //Power Limit feature
> @@ -85,8 +83,7 @@ enum SMU_13_0_7_ODFEATURE_ID
>
> #define SMU_13_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features
>
> -enum SMU_13_0_7_ODSETTING_ID
> -{
> +enum SMU_13_0_7_ODSETTING_ID {
> SMU_13_0_7_ODSETTING_GFXCLKFMAX = 0,
> SMU_13_0_7_ODSETTING_GFXCLKFMIN,
> SMU_13_0_7_ODSETTING_UCLKFMIN,
> @@ -123,8 +120,7 @@ enum SMU_13_0_7_ODSETTING_ID
> };
> #define SMU_13_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings
>
> -enum SMU_13_0_7_PWRMODE_SETTING
> -{
> +enum SMU_13_0_7_PWRMODE_SETTING {
> SMU_13_0_7_PMSETTING_POWER_LIMIT_QUIET = 0,
> SMU_13_0_7_PMSETTING_POWER_LIMIT_BALANCE,
> SMU_13_0_7_PMSETTING_POWER_LIMIT_TURBO,
> @@ -144,8 +140,7 @@ enum SMU_13_0_7_PWRMODE_SETTING
> };
> #define SMU_13_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode
> Settings
>
> -struct smu_13_0_7_overdrive_table
> -{
> +struct smu_13_0_7_overdrive_table {
> uint8_t revision; //Revision =
> SMU_13_0_7_PP_OVERDRIVE_VERSION
> uint8_t reserve[3]; //Zero filled field
> reserved for future use
> uint32_t feature_count; //Total number of
> supported features
> @@ -156,8 +151,7 @@ struct smu_13_0_7_overdrive_table
> int16_t pm_setting[SMU_13_0_7_MAX_PMSETTING]; //Optimized power
> mode feature settings
> };
>
> -enum SMU_13_0_7_PPCLOCK_ID
> -{
> +enum SMU_13_0_7_PPCLOCK_ID {
> SMU_13_0_7_PPCLOCK_GFXCLK = 0,
> SMU_13_0_7_PPCLOCK_SOCCLK,
> SMU_13_0_7_PPCLOCK_UCLK,
> @@ -175,8 +169,7 @@ enum SMU_13_0_7_PPCLOCK_ID
> };
> #define SMU_13_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
>
> -struct smu_13_0_7_powerplay_table
> -{
> +struct smu_13_0_7_powerplay_table {
> struct atom_common_table_header header; //For PLUM_BONITO,
> header.format_revision = 15, header.content_revision = 0
> uint8_t table_revision; //For PLUM_BONITO,
> table_revision = 2
> uint8_t padding;
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
@ 2023-07-24 21:59 ` Alex Deucher
0 siblings, 0 replies; 13+ messages in thread
From: Alex Deucher @ 2023-07-24 21:59 UTC (permalink / raw)
To: sunran001; +Cc: alexander.deucher, dri-devel, amd-gfx, linux-kernel
Applied. Thanks!
On Mon, Jul 24, 2023 at 5:08 AM <sunran001@208suo.com> wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
> .../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h | 21 +++++++------------
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> index eadbe0149cae..eb694f9f556d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> @@ -41,8 +41,7 @@
> #define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
> Table Version 0.2
> #define SMU_13_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
> Clock Table Version 1.00
>
> -enum SMU_13_0_7_ODFEATURE_CAP
> -{
> +enum SMU_13_0_7_ODFEATURE_CAP {
> SMU_13_0_7_ODCAP_GFXCLK_LIMITS = 0,
> SMU_13_0_7_ODCAP_UCLK_LIMITS,
> SMU_13_0_7_ODCAP_POWER_LIMIT,
> @@ -62,8 +61,7 @@ enum SMU_13_0_7_ODFEATURE_CAP
> SMU_13_0_7_ODCAP_COUNT,
> };
>
> -enum SMU_13_0_7_ODFEATURE_ID
> -{
> +enum SMU_13_0_7_ODFEATURE_ID {
> SMU_13_0_7_ODFEATURE_GFXCLK_LIMITS = 1 <<
> SMU_13_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
> SMU_13_0_7_ODFEATURE_UCLK_LIMITS = 1 <<
> SMU_13_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature
> SMU_13_0_7_ODFEATURE_POWER_LIMIT = 1 <<
> SMU_13_0_7_ODCAP_POWER_LIMIT, //Power Limit feature
> @@ -85,8 +83,7 @@ enum SMU_13_0_7_ODFEATURE_ID
>
> #define SMU_13_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features
>
> -enum SMU_13_0_7_ODSETTING_ID
> -{
> +enum SMU_13_0_7_ODSETTING_ID {
> SMU_13_0_7_ODSETTING_GFXCLKFMAX = 0,
> SMU_13_0_7_ODSETTING_GFXCLKFMIN,
> SMU_13_0_7_ODSETTING_UCLKFMIN,
> @@ -123,8 +120,7 @@ enum SMU_13_0_7_ODSETTING_ID
> };
> #define SMU_13_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings
>
> -enum SMU_13_0_7_PWRMODE_SETTING
> -{
> +enum SMU_13_0_7_PWRMODE_SETTING {
> SMU_13_0_7_PMSETTING_POWER_LIMIT_QUIET = 0,
> SMU_13_0_7_PMSETTING_POWER_LIMIT_BALANCE,
> SMU_13_0_7_PMSETTING_POWER_LIMIT_TURBO,
> @@ -144,8 +140,7 @@ enum SMU_13_0_7_PWRMODE_SETTING
> };
> #define SMU_13_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode
> Settings
>
> -struct smu_13_0_7_overdrive_table
> -{
> +struct smu_13_0_7_overdrive_table {
> uint8_t revision; //Revision =
> SMU_13_0_7_PP_OVERDRIVE_VERSION
> uint8_t reserve[3]; //Zero filled field
> reserved for future use
> uint32_t feature_count; //Total number of
> supported features
> @@ -156,8 +151,7 @@ struct smu_13_0_7_overdrive_table
> int16_t pm_setting[SMU_13_0_7_MAX_PMSETTING]; //Optimized power
> mode feature settings
> };
>
> -enum SMU_13_0_7_PPCLOCK_ID
> -{
> +enum SMU_13_0_7_PPCLOCK_ID {
> SMU_13_0_7_PPCLOCK_GFXCLK = 0,
> SMU_13_0_7_PPCLOCK_SOCCLK,
> SMU_13_0_7_PPCLOCK_UCLK,
> @@ -175,8 +169,7 @@ enum SMU_13_0_7_PPCLOCK_ID
> };
> #define SMU_13_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
>
> -struct smu_13_0_7_powerplay_table
> -{
> +struct smu_13_0_7_powerplay_table {
> struct atom_common_table_header header; //For PLUM_BONITO,
> header.format_revision = 15, header.content_revision = 0
> uint8_t table_revision; //For PLUM_BONITO,
> table_revision = 2
> uint8_t padding;
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
[not found] <20230724090624.9699-1-xujianghui@cdjrlc.com>
@ 2023-07-24 9:08 ` sunran001
0 siblings, 0 replies; 13+ messages in thread
From: sunran001 @ 2023-07-24 9:08 UTC (permalink / raw)
To: alexander.deucher; +Cc: amd-gfx, dri-devel, linux-kernel
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun <sunran001@208suo.com>
---
.../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h | 21 +++++++------------
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
index eadbe0149cae..eb694f9f556d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
@@ -41,8 +41,7 @@
#define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
Table Version 0.2
#define SMU_13_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
Clock Table Version 1.00
-enum SMU_13_0_7_ODFEATURE_CAP
-{
+enum SMU_13_0_7_ODFEATURE_CAP {
SMU_13_0_7_ODCAP_GFXCLK_LIMITS = 0,
SMU_13_0_7_ODCAP_UCLK_LIMITS,
SMU_13_0_7_ODCAP_POWER_LIMIT,
@@ -62,8 +61,7 @@ enum SMU_13_0_7_ODFEATURE_CAP
SMU_13_0_7_ODCAP_COUNT,
};
-enum SMU_13_0_7_ODFEATURE_ID
-{
+enum SMU_13_0_7_ODFEATURE_ID {
SMU_13_0_7_ODFEATURE_GFXCLK_LIMITS = 1 <<
SMU_13_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
SMU_13_0_7_ODFEATURE_UCLK_LIMITS = 1 <<
SMU_13_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature
SMU_13_0_7_ODFEATURE_POWER_LIMIT = 1 <<
SMU_13_0_7_ODCAP_POWER_LIMIT, //Power Limit feature
@@ -85,8 +83,7 @@ enum SMU_13_0_7_ODFEATURE_ID
#define SMU_13_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features
-enum SMU_13_0_7_ODSETTING_ID
-{
+enum SMU_13_0_7_ODSETTING_ID {
SMU_13_0_7_ODSETTING_GFXCLKFMAX = 0,
SMU_13_0_7_ODSETTING_GFXCLKFMIN,
SMU_13_0_7_ODSETTING_UCLKFMIN,
@@ -123,8 +120,7 @@ enum SMU_13_0_7_ODSETTING_ID
};
#define SMU_13_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings
-enum SMU_13_0_7_PWRMODE_SETTING
-{
+enum SMU_13_0_7_PWRMODE_SETTING {
SMU_13_0_7_PMSETTING_POWER_LIMIT_QUIET = 0,
SMU_13_0_7_PMSETTING_POWER_LIMIT_BALANCE,
SMU_13_0_7_PMSETTING_POWER_LIMIT_TURBO,
@@ -144,8 +140,7 @@ enum SMU_13_0_7_PWRMODE_SETTING
};
#define SMU_13_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode
Settings
-struct smu_13_0_7_overdrive_table
-{
+struct smu_13_0_7_overdrive_table {
uint8_t revision; //Revision =
SMU_13_0_7_PP_OVERDRIVE_VERSION
uint8_t reserve[3]; //Zero filled field
reserved for future use
uint32_t feature_count; //Total number of
supported features
@@ -156,8 +151,7 @@ struct smu_13_0_7_overdrive_table
int16_t pm_setting[SMU_13_0_7_MAX_PMSETTING]; //Optimized power
mode feature settings
};
-enum SMU_13_0_7_PPCLOCK_ID
-{
+enum SMU_13_0_7_PPCLOCK_ID {
SMU_13_0_7_PPCLOCK_GFXCLK = 0,
SMU_13_0_7_PPCLOCK_SOCCLK,
SMU_13_0_7_PPCLOCK_UCLK,
@@ -175,8 +169,7 @@ enum SMU_13_0_7_PPCLOCK_ID
};
#define SMU_13_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
-struct smu_13_0_7_powerplay_table
-{
+struct smu_13_0_7_powerplay_table {
struct atom_common_table_header header; //For PLUM_BONITO,
header.format_revision = 15, header.content_revision = 0
uint8_t table_revision; //For PLUM_BONITO,
table_revision = 2
uint8_t padding;
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
@ 2023-07-24 9:08 ` sunran001
0 siblings, 0 replies; 13+ messages in thread
From: sunran001 @ 2023-07-24 9:08 UTC (permalink / raw)
To: alexander.deucher; +Cc: dri-devel, amd-gfx, linux-kernel
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun <sunran001@208suo.com>
---
.../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h | 21 +++++++------------
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
index eadbe0149cae..eb694f9f556d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
@@ -41,8 +41,7 @@
#define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
Table Version 0.2
#define SMU_13_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
Clock Table Version 1.00
-enum SMU_13_0_7_ODFEATURE_CAP
-{
+enum SMU_13_0_7_ODFEATURE_CAP {
SMU_13_0_7_ODCAP_GFXCLK_LIMITS = 0,
SMU_13_0_7_ODCAP_UCLK_LIMITS,
SMU_13_0_7_ODCAP_POWER_LIMIT,
@@ -62,8 +61,7 @@ enum SMU_13_0_7_ODFEATURE_CAP
SMU_13_0_7_ODCAP_COUNT,
};
-enum SMU_13_0_7_ODFEATURE_ID
-{
+enum SMU_13_0_7_ODFEATURE_ID {
SMU_13_0_7_ODFEATURE_GFXCLK_LIMITS = 1 <<
SMU_13_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
SMU_13_0_7_ODFEATURE_UCLK_LIMITS = 1 <<
SMU_13_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature
SMU_13_0_7_ODFEATURE_POWER_LIMIT = 1 <<
SMU_13_0_7_ODCAP_POWER_LIMIT, //Power Limit feature
@@ -85,8 +83,7 @@ enum SMU_13_0_7_ODFEATURE_ID
#define SMU_13_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features
-enum SMU_13_0_7_ODSETTING_ID
-{
+enum SMU_13_0_7_ODSETTING_ID {
SMU_13_0_7_ODSETTING_GFXCLKFMAX = 0,
SMU_13_0_7_ODSETTING_GFXCLKFMIN,
SMU_13_0_7_ODSETTING_UCLKFMIN,
@@ -123,8 +120,7 @@ enum SMU_13_0_7_ODSETTING_ID
};
#define SMU_13_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings
-enum SMU_13_0_7_PWRMODE_SETTING
-{
+enum SMU_13_0_7_PWRMODE_SETTING {
SMU_13_0_7_PMSETTING_POWER_LIMIT_QUIET = 0,
SMU_13_0_7_PMSETTING_POWER_LIMIT_BALANCE,
SMU_13_0_7_PMSETTING_POWER_LIMIT_TURBO,
@@ -144,8 +140,7 @@ enum SMU_13_0_7_PWRMODE_SETTING
};
#define SMU_13_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode
Settings
-struct smu_13_0_7_overdrive_table
-{
+struct smu_13_0_7_overdrive_table {
uint8_t revision; //Revision =
SMU_13_0_7_PP_OVERDRIVE_VERSION
uint8_t reserve[3]; //Zero filled field
reserved for future use
uint32_t feature_count; //Total number of
supported features
@@ -156,8 +151,7 @@ struct smu_13_0_7_overdrive_table
int16_t pm_setting[SMU_13_0_7_MAX_PMSETTING]; //Optimized power
mode feature settings
};
-enum SMU_13_0_7_PPCLOCK_ID
-{
+enum SMU_13_0_7_PPCLOCK_ID {
SMU_13_0_7_PPCLOCK_GFXCLK = 0,
SMU_13_0_7_PPCLOCK_SOCCLK,
SMU_13_0_7_PPCLOCK_UCLK,
@@ -175,8 +169,7 @@ enum SMU_13_0_7_PPCLOCK_ID
};
#define SMU_13_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
-struct smu_13_0_7_powerplay_table
-{
+struct smu_13_0_7_powerplay_table {
struct atom_common_table_header header; //For PLUM_BONITO,
header.format_revision = 15, header.content_revision = 0
uint8_t table_revision; //For PLUM_BONITO,
table_revision = 2
uint8_t padding;
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
2023-07-21 3:27 ` sunran001
(?)
@ 2023-07-21 15:56 ` Alex Deucher
-1 siblings, 0 replies; 13+ messages in thread
From: Alex Deucher @ 2023-07-21 15:56 UTC (permalink / raw)
To: sunran001
Cc: alexander.deucher, airlied, daniel, dri-devel, amd-gfx, linux-kernel
This applied properly. Applied. Thanks!
Alex
On Thu, Jul 20, 2023 at 11:27 PM <sunran001@208suo.com> wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
> .../gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h | 21 +++++++------------
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> index 1dc7a065a6d4..251ed011b3b0 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> @@ -41,8 +41,7 @@
> #define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
> Table Version 0.2
> #define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
> Clock Table Version 1.00
>
> -enum SMU_13_0_0_ODFEATURE_CAP
> -{
> +enum SMU_13_0_0_ODFEATURE_CAP {
> SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
> SMU_13_0_0_ODCAP_UCLK_LIMITS,
> SMU_13_0_0_ODCAP_POWER_LIMIT,
> @@ -62,8 +61,7 @@ enum SMU_13_0_0_ODFEATURE_CAP
> SMU_13_0_0_ODCAP_COUNT,
> };
>
> -enum SMU_13_0_0_ODFEATURE_ID
> -{
> +enum SMU_13_0_0_ODFEATURE_ID {
> SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS = 1 <<
> SMU_13_0_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
> SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 <<
> SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature
> SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 <<
> SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature
> @@ -85,8 +83,7 @@ enum SMU_13_0_0_ODFEATURE_ID
>
> #define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
>
> -enum SMU_13_0_0_ODSETTING_ID
> -{
> +enum SMU_13_0_0_ODSETTING_ID {
> SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
> SMU_13_0_0_ODSETTING_GFXCLKFMIN,
> SMU_13_0_0_ODSETTING_UCLKFMIN,
> @@ -123,8 +120,7 @@ enum SMU_13_0_0_ODSETTING_ID
> };
> #define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings
>
> -enum SMU_13_0_0_PWRMODE_SETTING
> -{
> +enum SMU_13_0_0_PWRMODE_SETTING {
> SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0,
> SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE,
> SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO,
> @@ -144,8 +140,7 @@ enum SMU_13_0_0_PWRMODE_SETTING
> };
> #define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode
> Settings
>
> -struct smu_13_0_0_overdrive_table
> -{
> +struct smu_13_0_0_overdrive_table {
> uint8_t revision; //Revision =
> SMU_13_0_0_PP_OVERDRIVE_VERSION
> uint8_t reserve[3]; //Zero filled field
> reserved for future use
> uint32_t feature_count; //Total number of
> supported features
> @@ -156,8 +151,7 @@ struct smu_13_0_0_overdrive_table
> int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power
> mode feature settings
> };
>
> -enum SMU_13_0_0_PPCLOCK_ID
> -{
> +enum SMU_13_0_0_PPCLOCK_ID {
> SMU_13_0_0_PPCLOCK_GFXCLK = 0,
> SMU_13_0_0_PPCLOCK_SOCCLK,
> SMU_13_0_0_PPCLOCK_UCLK,
> @@ -175,8 +169,7 @@ enum SMU_13_0_0_PPCLOCK_ID
> };
> #define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
>
> -struct smu_13_0_0_powerplay_table
> -{
> +struct smu_13_0_0_powerplay_table {
> struct atom_common_table_header header; //For SMU13,
> header.format_revision = 15, header.content_revision = 0
> uint8_t table_revision; //For SMU13, table_revision
> = 2
> uint8_t padding;
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
@ 2023-07-21 15:56 ` Alex Deucher
0 siblings, 0 replies; 13+ messages in thread
From: Alex Deucher @ 2023-07-21 15:56 UTC (permalink / raw)
To: sunran001; +Cc: linux-kernel, amd-gfx, dri-devel, alexander.deucher
This applied properly. Applied. Thanks!
Alex
On Thu, Jul 20, 2023 at 11:27 PM <sunran001@208suo.com> wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
> .../gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h | 21 +++++++------------
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> index 1dc7a065a6d4..251ed011b3b0 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> @@ -41,8 +41,7 @@
> #define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
> Table Version 0.2
> #define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
> Clock Table Version 1.00
>
> -enum SMU_13_0_0_ODFEATURE_CAP
> -{
> +enum SMU_13_0_0_ODFEATURE_CAP {
> SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
> SMU_13_0_0_ODCAP_UCLK_LIMITS,
> SMU_13_0_0_ODCAP_POWER_LIMIT,
> @@ -62,8 +61,7 @@ enum SMU_13_0_0_ODFEATURE_CAP
> SMU_13_0_0_ODCAP_COUNT,
> };
>
> -enum SMU_13_0_0_ODFEATURE_ID
> -{
> +enum SMU_13_0_0_ODFEATURE_ID {
> SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS = 1 <<
> SMU_13_0_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
> SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 <<
> SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature
> SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 <<
> SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature
> @@ -85,8 +83,7 @@ enum SMU_13_0_0_ODFEATURE_ID
>
> #define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
>
> -enum SMU_13_0_0_ODSETTING_ID
> -{
> +enum SMU_13_0_0_ODSETTING_ID {
> SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
> SMU_13_0_0_ODSETTING_GFXCLKFMIN,
> SMU_13_0_0_ODSETTING_UCLKFMIN,
> @@ -123,8 +120,7 @@ enum SMU_13_0_0_ODSETTING_ID
> };
> #define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings
>
> -enum SMU_13_0_0_PWRMODE_SETTING
> -{
> +enum SMU_13_0_0_PWRMODE_SETTING {
> SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0,
> SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE,
> SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO,
> @@ -144,8 +140,7 @@ enum SMU_13_0_0_PWRMODE_SETTING
> };
> #define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode
> Settings
>
> -struct smu_13_0_0_overdrive_table
> -{
> +struct smu_13_0_0_overdrive_table {
> uint8_t revision; //Revision =
> SMU_13_0_0_PP_OVERDRIVE_VERSION
> uint8_t reserve[3]; //Zero filled field
> reserved for future use
> uint32_t feature_count; //Total number of
> supported features
> @@ -156,8 +151,7 @@ struct smu_13_0_0_overdrive_table
> int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power
> mode feature settings
> };
>
> -enum SMU_13_0_0_PPCLOCK_ID
> -{
> +enum SMU_13_0_0_PPCLOCK_ID {
> SMU_13_0_0_PPCLOCK_GFXCLK = 0,
> SMU_13_0_0_PPCLOCK_SOCCLK,
> SMU_13_0_0_PPCLOCK_UCLK,
> @@ -175,8 +169,7 @@ enum SMU_13_0_0_PPCLOCK_ID
> };
> #define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
>
> -struct smu_13_0_0_powerplay_table
> -{
> +struct smu_13_0_0_powerplay_table {
> struct atom_common_table_header header; //For SMU13,
> header.format_revision = 15, header.content_revision = 0
> uint8_t table_revision; //For SMU13, table_revision
> = 2
> uint8_t padding;
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
@ 2023-07-21 15:56 ` Alex Deucher
0 siblings, 0 replies; 13+ messages in thread
From: Alex Deucher @ 2023-07-21 15:56 UTC (permalink / raw)
To: sunran001
Cc: linux-kernel, amd-gfx, dri-devel, daniel, alexander.deucher, airlied
This applied properly. Applied. Thanks!
Alex
On Thu, Jul 20, 2023 at 11:27 PM <sunran001@208suo.com> wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
> .../gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h | 21 +++++++------------
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> index 1dc7a065a6d4..251ed011b3b0 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
> @@ -41,8 +41,7 @@
> #define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
> Table Version 0.2
> #define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
> Clock Table Version 1.00
>
> -enum SMU_13_0_0_ODFEATURE_CAP
> -{
> +enum SMU_13_0_0_ODFEATURE_CAP {
> SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
> SMU_13_0_0_ODCAP_UCLK_LIMITS,
> SMU_13_0_0_ODCAP_POWER_LIMIT,
> @@ -62,8 +61,7 @@ enum SMU_13_0_0_ODFEATURE_CAP
> SMU_13_0_0_ODCAP_COUNT,
> };
>
> -enum SMU_13_0_0_ODFEATURE_ID
> -{
> +enum SMU_13_0_0_ODFEATURE_ID {
> SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS = 1 <<
> SMU_13_0_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
> SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 <<
> SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature
> SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 <<
> SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature
> @@ -85,8 +83,7 @@ enum SMU_13_0_0_ODFEATURE_ID
>
> #define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
>
> -enum SMU_13_0_0_ODSETTING_ID
> -{
> +enum SMU_13_0_0_ODSETTING_ID {
> SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
> SMU_13_0_0_ODSETTING_GFXCLKFMIN,
> SMU_13_0_0_ODSETTING_UCLKFMIN,
> @@ -123,8 +120,7 @@ enum SMU_13_0_0_ODSETTING_ID
> };
> #define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings
>
> -enum SMU_13_0_0_PWRMODE_SETTING
> -{
> +enum SMU_13_0_0_PWRMODE_SETTING {
> SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0,
> SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE,
> SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO,
> @@ -144,8 +140,7 @@ enum SMU_13_0_0_PWRMODE_SETTING
> };
> #define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode
> Settings
>
> -struct smu_13_0_0_overdrive_table
> -{
> +struct smu_13_0_0_overdrive_table {
> uint8_t revision; //Revision =
> SMU_13_0_0_PP_OVERDRIVE_VERSION
> uint8_t reserve[3]; //Zero filled field
> reserved for future use
> uint32_t feature_count; //Total number of
> supported features
> @@ -156,8 +151,7 @@ struct smu_13_0_0_overdrive_table
> int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power
> mode feature settings
> };
>
> -enum SMU_13_0_0_PPCLOCK_ID
> -{
> +enum SMU_13_0_0_PPCLOCK_ID {
> SMU_13_0_0_PPCLOCK_GFXCLK = 0,
> SMU_13_0_0_PPCLOCK_SOCCLK,
> SMU_13_0_0_PPCLOCK_UCLK,
> @@ -175,8 +169,7 @@ enum SMU_13_0_0_PPCLOCK_ID
> };
> #define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
>
> -struct smu_13_0_0_powerplay_table
> -{
> +struct smu_13_0_0_powerplay_table {
> struct atom_common_table_header header; //For SMU13,
> header.format_revision = 15, header.content_revision = 0
> uint8_t table_revision; //For SMU13, table_revision
> = 2
> uint8_t padding;
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
[not found] <20230721032537.4727-1-xujianghui@cdjrlc.com>
@ 2023-07-21 3:27 ` sunran001
0 siblings, 0 replies; 13+ messages in thread
From: sunran001 @ 2023-07-21 3:27 UTC (permalink / raw)
To: alexander.deucher, airlied, daniel; +Cc: amd-gfx, dri-devel, linux-kernel
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun <sunran001@208suo.com>
---
.../gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h | 21 +++++++------------
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
index 1dc7a065a6d4..251ed011b3b0 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
@@ -41,8 +41,7 @@
#define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
Table Version 0.2
#define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
Clock Table Version 1.00
-enum SMU_13_0_0_ODFEATURE_CAP
-{
+enum SMU_13_0_0_ODFEATURE_CAP {
SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
SMU_13_0_0_ODCAP_UCLK_LIMITS,
SMU_13_0_0_ODCAP_POWER_LIMIT,
@@ -62,8 +61,7 @@ enum SMU_13_0_0_ODFEATURE_CAP
SMU_13_0_0_ODCAP_COUNT,
};
-enum SMU_13_0_0_ODFEATURE_ID
-{
+enum SMU_13_0_0_ODFEATURE_ID {
SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS = 1 <<
SMU_13_0_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 <<
SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature
SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 <<
SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature
@@ -85,8 +83,7 @@ enum SMU_13_0_0_ODFEATURE_ID
#define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
-enum SMU_13_0_0_ODSETTING_ID
-{
+enum SMU_13_0_0_ODSETTING_ID {
SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
SMU_13_0_0_ODSETTING_GFXCLKFMIN,
SMU_13_0_0_ODSETTING_UCLKFMIN,
@@ -123,8 +120,7 @@ enum SMU_13_0_0_ODSETTING_ID
};
#define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings
-enum SMU_13_0_0_PWRMODE_SETTING
-{
+enum SMU_13_0_0_PWRMODE_SETTING {
SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0,
SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE,
SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO,
@@ -144,8 +140,7 @@ enum SMU_13_0_0_PWRMODE_SETTING
};
#define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode
Settings
-struct smu_13_0_0_overdrive_table
-{
+struct smu_13_0_0_overdrive_table {
uint8_t revision; //Revision =
SMU_13_0_0_PP_OVERDRIVE_VERSION
uint8_t reserve[3]; //Zero filled field
reserved for future use
uint32_t feature_count; //Total number of
supported features
@@ -156,8 +151,7 @@ struct smu_13_0_0_overdrive_table
int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power
mode feature settings
};
-enum SMU_13_0_0_PPCLOCK_ID
-{
+enum SMU_13_0_0_PPCLOCK_ID {
SMU_13_0_0_PPCLOCK_GFXCLK = 0,
SMU_13_0_0_PPCLOCK_SOCCLK,
SMU_13_0_0_PPCLOCK_UCLK,
@@ -175,8 +169,7 @@ enum SMU_13_0_0_PPCLOCK_ID
};
#define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
-struct smu_13_0_0_powerplay_table
-{
+struct smu_13_0_0_powerplay_table {
struct atom_common_table_header header; //For SMU13,
header.format_revision = 15, header.content_revision = 0
uint8_t table_revision; //For SMU13, table_revision
= 2
uint8_t padding;
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
@ 2023-07-21 3:27 ` sunran001
0 siblings, 0 replies; 13+ messages in thread
From: sunran001 @ 2023-07-21 3:27 UTC (permalink / raw)
To: alexander.deucher, airlied, daniel; +Cc: dri-devel, amd-gfx, linux-kernel
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun <sunran001@208suo.com>
---
.../gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h | 21 +++++++------------
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
index 1dc7a065a6d4..251ed011b3b0 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
@@ -41,8 +41,7 @@
#define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8
Table Version 0.2
#define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
Clock Table Version 1.00
-enum SMU_13_0_0_ODFEATURE_CAP
-{
+enum SMU_13_0_0_ODFEATURE_CAP {
SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
SMU_13_0_0_ODCAP_UCLK_LIMITS,
SMU_13_0_0_ODCAP_POWER_LIMIT,
@@ -62,8 +61,7 @@ enum SMU_13_0_0_ODFEATURE_CAP
SMU_13_0_0_ODCAP_COUNT,
};
-enum SMU_13_0_0_ODFEATURE_ID
-{
+enum SMU_13_0_0_ODFEATURE_ID {
SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS = 1 <<
SMU_13_0_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 <<
SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature
SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 <<
SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature
@@ -85,8 +83,7 @@ enum SMU_13_0_0_ODFEATURE_ID
#define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
-enum SMU_13_0_0_ODSETTING_ID
-{
+enum SMU_13_0_0_ODSETTING_ID {
SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
SMU_13_0_0_ODSETTING_GFXCLKFMIN,
SMU_13_0_0_ODSETTING_UCLKFMIN,
@@ -123,8 +120,7 @@ enum SMU_13_0_0_ODSETTING_ID
};
#define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings
-enum SMU_13_0_0_PWRMODE_SETTING
-{
+enum SMU_13_0_0_PWRMODE_SETTING {
SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0,
SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE,
SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO,
@@ -144,8 +140,7 @@ enum SMU_13_0_0_PWRMODE_SETTING
};
#define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode
Settings
-struct smu_13_0_0_overdrive_table
-{
+struct smu_13_0_0_overdrive_table {
uint8_t revision; //Revision =
SMU_13_0_0_PP_OVERDRIVE_VERSION
uint8_t reserve[3]; //Zero filled field
reserved for future use
uint32_t feature_count; //Total number of
supported features
@@ -156,8 +151,7 @@ struct smu_13_0_0_overdrive_table
int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power
mode feature settings
};
-enum SMU_13_0_0_PPCLOCK_ID
-{
+enum SMU_13_0_0_PPCLOCK_ID {
SMU_13_0_0_PPCLOCK_GFXCLK = 0,
SMU_13_0_0_PPCLOCK_SOCCLK,
SMU_13_0_0_PPCLOCK_UCLK,
@@ -175,8 +169,7 @@ enum SMU_13_0_0_PPCLOCK_ID
};
#define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
-struct smu_13_0_0_powerplay_table
-{
+struct smu_13_0_0_powerplay_table {
struct atom_common_table_header header; //For SMU13,
header.format_revision = 15, header.content_revision = 0
uint8_t table_revision; //For SMU13, table_revision
= 2
uint8_t padding;
^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-07-24 22:00 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <20230721035225.4986-1-xujianghui@cdjrlc.com>
2023-07-21 3:53 ` [PATCH] drm/amd/pm: open brace '{' following struct go on the same line sunran001
2023-07-21 3:53 ` sunran001
2023-07-21 15:59 ` Alex Deucher
2023-07-21 15:59 ` Alex Deucher
[not found] <20230724090624.9699-1-xujianghui@cdjrlc.com>
2023-07-24 9:08 ` sunran001
2023-07-24 9:08 ` sunran001
2023-07-24 21:59 ` Alex Deucher
2023-07-24 21:59 ` Alex Deucher
[not found] <20230721032537.4727-1-xujianghui@cdjrlc.com>
2023-07-21 3:27 ` sunran001
2023-07-21 3:27 ` sunran001
2023-07-21 15:56 ` Alex Deucher
2023-07-21 15:56 ` Alex Deucher
2023-07-21 15:56 ` Alex Deucher
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