* [PATCH] target/avr: Optimize various functions using extract opcode
@ 2021-10-03 14:21 Philippe Mathieu-Daudé
2021-10-03 15:24 ` Richard Henderson
0 siblings, 1 reply; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-03 14:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Michael Rolnik, Richard Henderson, Philippe Mathieu-Daudé
When running the scripts/coccinelle/tcg_gen_extract.cocci
Coccinelle semantic patch on target/avr/, we get:
[DBG] candidate at target/avr/translate.c:228
[DBG] candidate at target/avr/translate.c:266
[DBG] candidate at target/avr/translate.c:885
[DBG] candidate at target/avr/translate.c:924
[DBG] candidate at target/avr/translate.c:962
Manually inspect and replace combinations of (shri, andi)
opcodes by the extract opcode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/avr/translate.c | 16 +++++-----------
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 438e7b13c18..246cbfba1cd 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -225,8 +225,7 @@ static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)
tcg_gen_or_tl(t1, t1, t3);
tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */
- tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */
- tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+ tcg_gen_extract_tl(cpu_Hf, t1, 3, 1); /* Hf = t1(3) */
tcg_temp_free_i32(t3);
tcg_temp_free_i32(t2);
@@ -263,8 +262,7 @@ static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)
tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */
- tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */
- tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+ tcg_gen_extract_tl(cpu_Hf, t2, 3, 1); /* Hf = t2(3) */
tcg_temp_free_i32(t3);
tcg_temp_free_i32(t2);
@@ -882,9 +880,7 @@ static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a)
/* update output registers */
tcg_gen_shli_tl(R, R, 1);
tcg_gen_andi_tl(R0, R, 0xff);
- tcg_gen_shri_tl(R1, R, 8);
- tcg_gen_andi_tl(R1, R1, 0xff);
-
+ tcg_gen_extract_tl(R1, R, 8, 8);
tcg_temp_free_i32(R);
@@ -921,8 +917,7 @@ static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a)
/* update output registers */
tcg_gen_shli_tl(R, R, 1);
tcg_gen_andi_tl(R0, R, 0xff);
- tcg_gen_shri_tl(R1, R, 8);
- tcg_gen_andi_tl(R1, R1, 0xff);
+ tcg_gen_extract_tl(R1, R, 8, 8);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t0);
@@ -959,8 +954,7 @@ static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a)
/* update output registers */
tcg_gen_shli_tl(R, R, 1);
tcg_gen_andi_tl(R0, R, 0xff);
- tcg_gen_shri_tl(R1, R, 8);
- tcg_gen_andi_tl(R1, R1, 0xff);
+ tcg_gen_extract_tl(R1, R, 8, 8);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(R);
--
2.31.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/avr: Optimize various functions using extract opcode
2021-10-03 14:21 [PATCH] target/avr: Optimize various functions using extract opcode Philippe Mathieu-Daudé
@ 2021-10-03 15:24 ` Richard Henderson
2021-10-27 4:39 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 4+ messages in thread
From: Richard Henderson @ 2021-10-03 15:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Michael Rolnik
On 10/3/21 10:21 AM, Philippe Mathieu-Daudé wrote:
> When running the scripts/coccinelle/tcg_gen_extract.cocci
> Coccinelle semantic patch on target/avr/, we get:
>
> [DBG] candidate at target/avr/translate.c:228
> [DBG] candidate at target/avr/translate.c:266
> [DBG] candidate at target/avr/translate.c:885
> [DBG] candidate at target/avr/translate.c:924
> [DBG] candidate at target/avr/translate.c:962
>
> Manually inspect and replace combinations of (shri, andi)
> opcodes by the extract opcode.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/avr/translate.c | 16 +++++-----------
> 1 file changed, 5 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/avr: Optimize various functions using extract opcode
2021-10-03 15:24 ` Richard Henderson
@ 2021-10-27 4:39 ` Philippe Mathieu-Daudé
2021-10-27 9:28 ` Michael Rolnik
0 siblings, 1 reply; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-27 4:39 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Michael Rolnik
Hi Richard,
On 10/3/21 17:24, Richard Henderson wrote:
> On 10/3/21 10:21 AM, Philippe Mathieu-Daudé wrote:
>> When running the scripts/coccinelle/tcg_gen_extract.cocci
>> Coccinelle semantic patch on target/avr/, we get:
>>
>> [DBG] candidate at target/avr/translate.c:228
>> [DBG] candidate at target/avr/translate.c:266
>> [DBG] candidate at target/avr/translate.c:885
>> [DBG] candidate at target/avr/translate.c:924
>> [DBG] candidate at target/avr/translate.c:962
>>
>> Manually inspect and replace combinations of (shri, andi)
>> opcodes by the extract opcode.
>>
>> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
>> ---
>> target/avr/translate.c | 16 +++++-----------
>> 1 file changed, 5 insertions(+), 11 deletions(-)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Do you mind taking this patch via tcg-next?
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/avr: Optimize various functions using extract opcode
2021-10-27 4:39 ` Philippe Mathieu-Daudé
@ 2021-10-27 9:28 ` Michael Rolnik
0 siblings, 0 replies; 4+ messages in thread
From: Michael Rolnik @ 2021-10-27 9:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: Richard Henderson, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1104 bytes --]
hi Philippe
how was it tested?
On Wed, Oct 27, 2021 at 7:42 AM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Richard,
>
> On 10/3/21 17:24, Richard Henderson wrote:
> > On 10/3/21 10:21 AM, Philippe Mathieu-Daudé wrote:
> >> When running the scripts/coccinelle/tcg_gen_extract.cocci
> >> Coccinelle semantic patch on target/avr/, we get:
> >>
> >> [DBG] candidate at target/avr/translate.c:228
> >> [DBG] candidate at target/avr/translate.c:266
> >> [DBG] candidate at target/avr/translate.c:885
> >> [DBG] candidate at target/avr/translate.c:924
> >> [DBG] candidate at target/avr/translate.c:962
> >>
> >> Manually inspect and replace combinations of (shri, andi)
> >> opcodes by the extract opcode.
> >>
> >> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> >> ---
> >> target/avr/translate.c | 16 +++++-----------
> >> 1 file changed, 5 insertions(+), 11 deletions(-)
> >
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Do you mind taking this patch via tcg-next?
>
--
Best Regards,
Michael Rolnik
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2021-10-03 14:21 [PATCH] target/avr: Optimize various functions using extract opcode Philippe Mathieu-Daudé
2021-10-03 15:24 ` Richard Henderson
2021-10-27 4:39 ` Philippe Mathieu-Daudé
2021-10-27 9:28 ` Michael Rolnik
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