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From: Dmitry Osipenko <digetx@gmail.com>
To: Akhil R <akhilrajeev@nvidia.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Krishna Yarlagadda <kyarlagadda@nvidia.com>,
	Laxman Dewangan <ldewangan@nvidia.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	Rajesh Gumasta <rgumasta@nvidia.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"thierry.reding@gmail.com" <thierry.reding@gmail.com>,
	"vkoul@kernel.org" <vkoul@kernel.org>
Cc: Pavan Kunapuli <pkunapuli@nvidia.com>
Subject: Re: [PATCH v17 2/4] dmaengine: tegra: Add tegra gpcdma driver
Date: Mon, 31 Jan 2022 02:23:28 +0300	[thread overview]
Message-ID: <f3ffb863-7a78-414c-bee2-09293b28a9da@gmail.com> (raw)
In-Reply-To: <DM5PR12MB1850C29D41F50FA6850C89DDC0249@DM5PR12MB1850.namprd12.prod.outlook.com>

30.01.2022 19:43, Akhil R пишет:
>> 30.01.2022 13:26, Dmitry Osipenko пишет:
>>> 30.01.2022 13:05, Dmitry Osipenko пишет:
>>>> Still nothing prevents interrupt handler to fire during the pause.
>>>>
>>>> What you actually need to do is to disable/enable interrupt. This
>>>> will prevent the interrupt racing and then pause/resume may look like this:
>>>
>>> Although, seems this won't work, unfortunately. I see now that
>>> device_pause() doesn't have might_sleep().
>>>
>>
>> Ah, I see now that the pause/unpause is actually a separate control and doesn't
>> conflict with "start next transfer".
>>
>> So you just need to set/unset the pause under lock. And don't touch
>> tdc->dma_desc. That's it.
>>
>> static int tegra_dma_device_pause(struct dma_chan *dc) {
>>         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
>>         unsigned long flags;
>>         u32 val;
>>
>>         if (!tdc->tdma->chip_data->hw_support_pause)
>>                 return -ENOSYS;
>>
>>         spin_lock_irqsave(&tdc->vc.lock, flags);
>>
>>         val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
>>         val |= TEGRA_GPCDMA_CHAN_CSRE_PAUSE;
>>         tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
>>
>>         spin_unlock_irqrestore(&tdc->vc.lock, flags);
>>
>>         return 0;
>> }
>>
>> static int tegra_dma_device_resume(struct dma_chan *dc) {
>>         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
>>         unsigned long flags;
>>         u32 val;
>>
>>         if (!tdc->tdma->chip_data->hw_support_pause)
>>                 return -ENOSYS;
>>
>>         spin_lock_irqsave(&tdc->vc.lock, flags);
>>
>>         val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
>>         val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE;
>>         tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
>>
>>         spin_unlock_irqrestore(&tdc->vc.lock, flags);
>>
>>         return 0;
>> }
> 
> The reason I separated out register writes was to conveniently call those
> in dma_start() and terminate_all(). Do you see any issue there?
> The recommended way of terminating a transfer in between is to pause
> it before disabling the channel.

This is a sample code, feel free to adjust it as needed.

> dma_desc could be NULL while these functions are called. pause() or
> resume() is unneeded if there isn't any transfer going on. Moreover,
> if we are to calculate the xfer_size, the check would be mandatory.

For now looks like it should be better to move the xfer_size updating to
other places, like terminate_all() and tx_status().

I also see now that you have
residue_granularity=DMA_RESIDUE_GRANULARITY_BURST, while tx_status()  in
fact uses segment granularity. This needs to be corrected.

You also must add locking to tx_status(), to protect tdc->dma_desc
pointer updates.

  reply	other threads:[~2022-01-30 23:23 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-29 16:40 [PATCH v17 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
2022-01-29 16:40 ` [PATCH v17 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
2022-01-29 16:40 ` [PATCH v17 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
2022-01-29 18:42   ` kernel test robot
2022-01-29 19:23   ` kernel test robot
2022-01-29 19:23     ` kernel test robot
2022-01-30 10:05   ` Dmitry Osipenko
2022-01-30 10:08     ` Dmitry Osipenko
2022-01-30 10:13       ` Dmitry Osipenko
2022-01-30 10:17         ` Dmitry Osipenko
2022-01-30 10:26     ` Dmitry Osipenko
2022-01-30 10:33       ` Dmitry Osipenko
2022-01-30 16:43         ` Akhil R
2022-01-30 23:23           ` Dmitry Osipenko [this message]
2022-01-30 16:34     ` Akhil R
2022-01-30 23:11       ` Dmitry Osipenko
2022-01-31  4:25         ` Akhil R
2022-01-31  6:42           ` Dmitry Osipenko
2022-01-31  9:09             ` Akhil R
2022-01-31  9:16               ` Dmitry Osipenko
2022-01-31 15:38                 ` Akhil R
2022-01-31 16:08                   ` Dmitry Osipenko
2022-02-01 12:05                     ` Akhil R
2022-02-01 13:06                       ` Dmitry Osipenko
2022-01-30 10:38   ` Dmitry Osipenko
2022-01-30 10:39   ` Dmitry Osipenko
2022-01-29 16:40 ` [PATCH v17 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
2022-01-29 16:40 ` [PATCH v17 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R

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