* Re: [PATCH] arm: imx8mp-evk: CLOCK Enable SPI and QOS clock
[not found] ` <AS8P195MB120741DE6EC136C5C7FF530DF3D49@AS8P195MB1207.EURP195.PROD.OUTLOOK.COM>
@ 2021-09-08 13:02 ` Ramon Fried
2021-09-15 2:55 ` Peng Fan (OSS)
1 sibling, 0 replies; 2+ messages in thread
From: Ramon Fried @ 2021-09-08 13:02 UTC (permalink / raw)
To: Arendt, Steffen
Cc: Ye Li, sbabic, u-boot, festevam, peng.fan, uboot-imx, marex
On Wed, Sep 8, 2021 at 8:27 AM Arendt, Steffen <s.arendt@sensopart.de>
wrote:
> Enable clocks for SPI and QOS (Ethernet) for the imx8mp SoC
>
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index c77500bcce..1ab5587e4e 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -116,6 +116,30 @@ static const char *imx8mp_i2c6_sels[] =
> {"clock-osc-24m", "sys_pll1_160m", "sys_
> "sys_pll3_out", "audio_pll1_out",
> "video_pll1_out",
> "audio_pll2_out",
> "sys_pll1_133m", };
>
> +#if CONFIG_IS_ENABLED(DM_SPI)
> +static const char *imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m",
> "sys_pll1_800m", "sys_pll3_out",
> + "sys_pll2_250m",
> "audio_pll2_out", };
> +
> +static const char *imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m",
> "sys_pll1_800m", "sys_pll3_out",
> + "sys_pll2_250m",
> "audio_pll2_out", };
> +
> +static const char *imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m",
> "sys_pll1_800m", "sys_pll3_out",
> + "sys_pll2_250m",
> "audio_pll2_out", };
> +#endif
> +
> +#if CONFIG_IS_ENABLED(DWC_ETH_QOS)
> +static const char *imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m",
> "sys_pll2_50m",
> + "sys_pll2_100m",
> "sys_pll1_160m", "audio_pll1_out",
> + "video_pll1_out", "clk_ext4",
> };
> +
> +static const char *imx8mp_enet_qos_timer_sels[] = {"osc_24m",
> "sys_pll2_100m", "audio_pll1_out",
> + "clk_ext1", "clk_ext2",
> "clk_ext3",
> + "clk_ext4",
> "video_pll1_out", };
> +#endif
> +
> static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m",
> "sys_pll1_400m", "sys_pll1_800m",
> "sys_pll2_500m",
> "sys_pll3_out", "sys_pll1_266m",
> "audio_pll2_out",
> "sys_pll1_100m", };
> @@ -397,6 +421,28 @@ static int imx8mp_clk_probe(struct udevice *dev)
>
> clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk",
> "usdhc3", base + 0x45e0, 0));
>
> +#if CONFIG_IS_ENABLED(DM_SPI)
> + clk_dm(IMX8MP_CLK_ECSPI1,
> + imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base +
> 0xb280));
> + clk_dm(IMX8MP_CLK_ECSPI2,
> + imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base +
> 0xb300));
> + clk_dm(IMX8MP_CLK_ECSPI3,
> + imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base +
> 0xc180));
> + clk_dm(IMX8MP_CLK_ECSPI1_ROOT,
> + imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070,
> 0));
> + clk_dm(IMX8MP_CLK_ECSPI2_ROOT,
> + imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080,
> 0));
> + clk_dm(IMX8MP_CLK_ECSPI3_ROOT,
> + imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090,
> 0));
> +#endif
> +
> +#if CONFIG_IS_ENABLED(DWC_ETH_QOS)
> + clk_dm(IMX8MP_CLK_ENET_QOS,
> + imx8m_clk_composite("enet_qos",
> imx8mp_enet_qos_sels, base + 0xa880));
> + clk_dm(IMX8MP_CLK_ENET_QOS_TIMER,
> + imx8m_clk_composite("enet_qos_timer",
> imx8mp_enet_qos_timer_sels, base + 0xa900));
> +#endif
> +
> return 0;
> }
>
>
> [image: SensoPart] <https://www.sensopart.com/>
> <https://www.linkedin.com/company/sensopart>
> <https://www.youtube.com/user/sensopart>
> <https://www.xing.com/pages/sensopartindustriesensorikgmbh>
>
> *SensoPart Industriesensorik GmbH*
> Am Wiedenbach 1
> 79695 Wieden
> Deutschland
>
> Eingetragen im Amtsgericht Freiburg i.Br.
> Registernummer: HRB 660163
> USt-IdNr.: DE 811614252
> Geschäftsführer: Dr. Theodor Wanner, Thorsten Wanner
>
> Informationen gem. Art. 13 DSGVO für unsere Kunden, Partner, Lieferanten
> finden Sie in unserer Erklärung zum Datenschutz unter
> https://www.sensopart.com/de/datenschutz
>
>
>
Please make sure not to send signatures when you send patches.
Thanks,
Ramon.
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] arm: imx8mp-evk: CLOCK Enable SPI and QOS clock
[not found] ` <AS8P195MB120741DE6EC136C5C7FF530DF3D49@AS8P195MB1207.EURP195.PROD.OUTLOOK.COM>
2021-09-08 13:02 ` [PATCH] arm: imx8mp-evk: CLOCK Enable SPI and QOS clock Ramon Fried
@ 2021-09-15 2:55 ` Peng Fan (OSS)
1 sibling, 0 replies; 2+ messages in thread
From: Peng Fan (OSS) @ 2021-09-15 2:55 UTC (permalink / raw)
To: Arendt, Steffen, Ye Li, sbabic, u-boot, festevam, Peng Fan
Cc: dl-uboot-imx, marex, rfried.dev
Please resend with plain text.
On 2021/9/8 13:26, Arendt, Steffen wrote:
> Enable clocks for SPI and QOS (Ethernet) for the imx8mp SoC
>
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index c77500bcce..1ab5587e4e 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -116,6 +116,30 @@ static const char *imx8mp_i2c6_sels[] =
> {"clock-osc-24m", "sys_pll1_160m", "sys_
> "sys_pll3_out",
> "audio_pll1_out", "video_pll1_out",
> "audio_pll2_out",
> "sys_pll1_133m", };
>
> +#if CONFIG_IS_ENABLED(DM_SPI)
> +static const char *imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m",
> "sys_pll1_800m", "sys_pll3_out",
> + "sys_pll2_250m",
> "audio_pll2_out", };
> +
> +static const char *imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m",
> "sys_pll1_800m", "sys_pll3_out",
> + "sys_pll2_250m",
> "audio_pll2_out", };
> +
> +static const char *imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll1_40m",
> + "sys_pll1_160m",
> "sys_pll1_800m", "sys_pll3_out",
> + "sys_pll2_250m",
> "audio_pll2_out", };
> +#endif
> +
> +#if CONFIG_IS_ENABLED(DWC_ETH_QOS)
> +static const char *imx8mp_enet_qos_sels[] = {"osc_24m",
> "sys_pll2_125m", "sys_pll2_50m",
> + "sys_pll2_100m",
> "sys_pll1_160m", "audio_pll1_out",
> + "video_pll1_out",
> "clk_ext4", };
> +
> +static const char *imx8mp_enet_qos_timer_sels[] = {"osc_24m",
> "sys_pll2_100m", "audio_pll1_out",
> + "clk_ext1",
> "clk_ext2", "clk_ext3",
> + "clk_ext4",
> "video_pll1_out", };
> +#endif
> +
> static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m",
> "sys_pll1_400m", "sys_pll1_800m",
> "sys_pll2_500m",
> "sys_pll3_out", "sys_pll1_266m",
> "audio_pll2_out",
> "sys_pll1_100m", };
> @@ -397,6 +421,28 @@ static int imx8mp_clk_probe(struct udevice *dev)
>
> clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk",
> "usdhc3", base + 0x45e0, 0));
>
> +#if CONFIG_IS_ENABLED(DM_SPI)
> + clk_dm(IMX8MP_CLK_ECSPI1,
> + imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base +
> 0xb280));
> + clk_dm(IMX8MP_CLK_ECSPI2,
> + imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base +
> 0xb300));
> + clk_dm(IMX8MP_CLK_ECSPI3,
> + imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base +
> 0xc180));
> + clk_dm(IMX8MP_CLK_ECSPI1_ROOT,
> + imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070,
> 0));
> + clk_dm(IMX8MP_CLK_ECSPI2_ROOT,
> + imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080,
> 0));
> + clk_dm(IMX8MP_CLK_ECSPI3_ROOT,
> + imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090,
> 0));
> +#endif
> +
> +#if CONFIG_IS_ENABLED(DWC_ETH_QOS)
> + clk_dm(IMX8MP_CLK_ENET_QOS,
> + imx8m_clk_composite("enet_qos",
> imx8mp_enet_qos_sels, base + 0xa880));
> + clk_dm(IMX8MP_CLK_ENET_QOS_TIMER,
> + imx8m_clk_composite("enet_qos_timer",
> imx8mp_enet_qos_timer_sels, base + 0xa900));
> +#endif
> +
> return 0;
> }
>
> SensoPart
> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.sensopart.com%2F&data=04%7C01%7Cpeng.fan%40nxp.com%7Cfa5f2316b06247c60c7608d972894c78%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637666756288632363%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=mxpJJ2EOdYXMM2lp6e7l7Q1NbqhxJiV5O4lhxtq4FpM%3D&reserved=0>
> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.linkedin.com%2Fcompany%2Fsensopart&data=04%7C01%7Cpeng.fan%40nxp.com%7Cfa5f2316b06247c60c7608d972894c78%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637666756288642359%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=ozuXYmIdc5X5pfGFku8fVAGDSbKNnM7t6rTuzcNxIeI%3D&reserved=0>
> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.youtube.com%2Fuser%2Fsensopart&data=04%7C01%7Cpeng.fan%40nxp.com%7Cfa5f2316b06247c60c7608d972894c78%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637666756288652362%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=x6KKombmZ6taVmgZ76bRjnEa4gQA6JsozgojPrGJY9Q%3D&reserved=0>
> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.xing.com%2Fpages%2Fsensopartindustriesensorikgmbh&data=04%7C01%7Cpeng.fan%40nxp.com%7Cfa5f2316b06247c60c7608d972894c78%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637666756288652362%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=AkIv75Yn4FUK2FiHuUkf0AOGSF3t7DRKl9KRcq1r6Q8%3D&reserved=0>
>
>
>
> *SensoPart Industriesensorik GmbH*
> Am Wiedenbach 1
> 79695 Wieden
> Deutschland
>
> Eingetragen im Amtsgericht Freiburg i.Br.
> Registernummer: HRB 660163
> USt-IdNr.: DE 811614252
> Geschäftsführer: Dr. Theodor Wanner, Thorsten Wanner
>
> Informationen gem. Art. 13 DSGVO für unsere Kunden, Partner, Lieferanten
> finden Sie in unserer Erklärung zum Datenschutz unter
> https://www.sensopart.com/de/datenschutz
> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.sensopart.com%2Fde%2Fdatenschutz%2F&data=04%7C01%7Cpeng.fan%40nxp.com%7Cfa5f2316b06247c60c7608d972894c78%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637666756288662353%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=zgAxcxaLWwItRRjCOvmekQZF6iJ%2FKTbju1DFpimn%2FgM%3D&reserved=0>
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-09-15 2:55 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <8a2f9ac4-da39-4a7b-9a12-0e500cdd78e6.996a82c2-2270-442c-9415-13a10d4974d4.13e1d281-49f5-4e53-b601-a507913f0011@emailsignatures365.codetwo.com>
[not found] ` <AS8P195MB120741DE6EC136C5C7FF530DF3D49@AS8P195MB1207.EURP195.PROD.OUTLOOK.COM>
2021-09-08 13:02 ` [PATCH] arm: imx8mp-evk: CLOCK Enable SPI and QOS clock Ramon Fried
2021-09-15 2:55 ` Peng Fan (OSS)
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.