[PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler

[PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler

[Philippe Mathieu-Daudé]

Hi,

This series introduce a generic get_cpu_state() handler in
TCGCPUOps and convert each target to it.

This is required to get a single cpu_get_tb_cpu_state()
for heterogeneous emulation (since this method is called
by accel/tcg/).

Regards,

Phil.

Philippe Mathieu-Daudé (27):
  accel/tcg: Ensure frontends define restore_state_to_opc handler
  accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler
  target/alpha: Convert to TCGCPUOps::get_cpu_state()
  target/arm: Restrict TCG-specific declarations
  target/arm: Convert to TCGCPUOps::get_cpu_state()
  target/avr: Convert to TCGCPUOps::get_cpu_state()
  target/cris: Convert to TCGCPUOps::get_cpu_state()
  target/hexagon: Convert to TCGCPUOps::get_cpu_state()
  target/hppa: Convert to TCGCPUOps::get_cpu_state()
  target/i386: Convert to TCGCPUOps::get_cpu_state()
  target/loongarch: Convert to TCGCPUOps::get_cpu_state()
  target/m68k: Convert to TCGCPUOps::get_cpu_state()
  target/microblaze: Convert to TCGCPUOps::get_cpu_state()
  target/mips: Convert to TCGCPUOps::get_cpu_state()
  target/nios2: Convert to TCGCPUOps::get_cpu_state()
  target/openrisc: Convert to TCGCPUOps::get_cpu_state()
  target/ppc: Indent ppc_tcg_ops[] with 4 spaces
  target/ppc: Convert to TCGCPUOps::get_cpu_state()
  target/riscv: Convert to TCGCPUOps::get_cpu_state()
  target/rx: Convert to TCGCPUOps::get_cpu_state()
  target/s390x: Restrict TCG-specific declarations
  target/s390x: Convert to TCGCPUOps::get_cpu_state()
  target/sh4: Convert to TCGCPUOps::get_cpu_state()
  target/sparc: Convert to TCGCPUOps::get_cpu_state()
  target/tricore: Convert to TCGCPUOps::get_cpu_state()
  target/xtensa: Convert to TCGCPUOps::get_cpu_state()
  accel/tcg: Remove check on TARGET_HAS_CPU_GET_TB_CPU_STATE

 accel/tcg/internal-target.h             |   2 +
 include/hw/core/tcg-cpu-ops.h           |   3 +
 target/alpha/cpu.h                      |  11 ---
 target/arm/cpu.h                        |   3 -
 target/arm/internals.h                  |   6 +-
 target/avr/cpu.h                        |  18 ----
 target/cris/cpu.h                       |  10 ---
 target/hexagon/cpu.h                    |  12 ---
 target/hppa/cpu.h                       |  42 ---------
 target/i386/cpu.h                       |  14 ---
 target/loongarch/cpu.h                  |  12 ---
 target/m68k/cpu.h                       |  16 ----
 target/microblaze/cpu.h                 |   8 --
 target/mips/cpu.h                       |   9 --
 target/mips/tcg/tcg-internal.h          |   2 +
 target/nios2/cpu.h                      |  12 ---
 target/openrisc/cpu.h                   |  10 ---
 target/ppc/cpu.h                        |  14 +--
 target/riscv/cpu.h                      |   3 -
 target/rx/cpu.h                         |   9 --
 target/s390x/cpu.h                      |  28 ------
 target/s390x/s390x-internal.h           |   4 +
 target/sh4/cpu.h                        |  15 ----
 target/sparc/cpu.h                      |  35 +-------
 target/tricore/cpu.h                    |  12 ---
 target/xtensa/cpu.h                     |  68 ---------------
 accel/tcg/cpu-exec.c                    |   6 +-
 accel/tcg/translate-all.c               |   8 ++
 target/alpha/cpu.c                      |  12 +++
 target/arm/cpu.c                        | 110 ++++++++++++++++++++++++
 target/arm/helper.c                     | 109 -----------------------
 target/arm/tcg-stubs.c                  |   4 -
 target/arm/tcg/cpu-v7m.c                |   1 +
 target/avr/cpu.c                        |  19 ++++
 target/cris/cpu.c                       |  11 +++
 target/hexagon/cpu.c                    |  13 +++
 target/hppa/cpu.c                       |  43 +++++++++
 target/i386/cpu.c                       |   2 +-
 target/i386/tcg/tcg-cpu.c               |  15 ++++
 target/loongarch/cpu.c                  |  15 ++++
 target/m68k/cpu.c                       |  17 ++++
 target/microblaze/cpu.c                 |   9 ++
 target/mips/cpu.c                       |   1 +
 target/mips/tcg/translate.c             |   9 ++
 target/nios2/cpu.c                      |  13 +++
 target/openrisc/cpu.c                   |  11 +++
 target/ppc/cpu_init.c                   |  27 +++---
 target/ppc/helper_regs.c                |  13 +--
 target/riscv/cpu.c                      |   2 +-
 target/riscv/cpu_helper.c               |  87 -------------------
 target/riscv/tcg/tcg-cpu.c              |  88 +++++++++++++++++++
 target/rx/cpu.c                         |  10 +++
 target/s390x/cpu.c                      |   1 +
 target/s390x/tcg/mem_helper.c           |   2 +-
 target/s390x/tcg/translate.c            |  23 +++++
 target/sh4/cpu.c                        |  16 ++++
 target/sparc/cpu.c                      |   1 +
 target/sparc/translate.c                |  33 +++++++
 target/tricore/cpu.c                    |  13 +++
 target/xtensa/cpu.c                     |  69 +++++++++++++++
 target/riscv/insn_trans/trans_rvv.c.inc |   2 +-
 61 files changed, 611 insertions(+), 582 deletions(-)

-- 
2.41.0

[PATCH-for-9.1 01/27] accel/tcg: Ensure frontends define restore_state_to_opc handler

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 accel/tcg/cpu-exec.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 5c70748060..987e6164f7 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -1069,7 +1069,10 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp)
     static bool tcg_target_initialized;
 
     if (!tcg_target_initialized) {
-        cpu->cc->tcg_ops->initialize();
+        const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
+
+        assert(tcg_ops->restore_state_to_opc);
+        tcg_ops->initialize();
         tcg_target_initialized = true;
     }
 
-- 
2.41.0

[PATCH-for-9.1 02/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler

[Philippe Mathieu-Daudé]

We want a single cpu_get_tb_cpu_state() for all targets,
but each of them already define it.

Introduce a generic target-agnostic cpu_get_tb_cpu_state()
method when per-target TARGET_HAS_CPU_GET_TB_CPU_STATE
is not defined. Currently all targets define it, but they
are going to be converted one by one.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 accel/tcg/internal-target.h   |  2 ++
 include/hw/core/tcg-cpu-ops.h |  3 +++
 target/alpha/cpu.h            |  2 ++
 target/arm/cpu.h              |  2 ++
 target/avr/cpu.h              |  2 ++
 target/cris/cpu.h             |  2 ++
 target/hexagon/cpu.h          |  2 ++
 target/hppa/cpu.h             |  2 ++
 target/i386/cpu.h             |  2 ++
 target/loongarch/cpu.h        |  2 ++
 target/m68k/cpu.h             |  2 ++
 target/microblaze/cpu.h       |  2 ++
 target/mips/cpu.h             |  2 ++
 target/nios2/cpu.h            |  2 ++
 target/openrisc/cpu.h         |  2 ++
 target/ppc/cpu.h              |  2 ++
 target/rx/cpu.h               |  2 ++
 target/s390x/cpu.h            |  2 ++
 target/sparc/cpu.h            |  2 ++
 target/xtensa/cpu.h           |  2 ++
 accel/tcg/translate-all.c     | 10 ++++++++++
 21 files changed, 51 insertions(+)

diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index 4e36cf858e..10a45d3b9c 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -79,6 +79,8 @@ TranslationBlock *tb_link_page(TranslationBlock *tb);
 bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc);
 void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
                                uintptr_t host_pc);
+void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc,
+                          uint64_t *cs_base, uint32_t *flags);
 
 bool tcg_exec_realizefn(CPUState *cpu, Error **errp);
 void tcg_exec_unrealizefn(CPUState *cpu);
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index bf8ff8e3ee..0ad9949950 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -49,6 +49,9 @@ struct TCGCPUOps {
     /** @debug_excp_handler: Callback for handling debug exceptions */
     void (*debug_excp_handler)(CPUState *cpu);
 
+    void (*get_cpu_state)(CPUArchState *cpu, vaddr *pc,
+                          uint64_t *cs_base, uint32_t *flags);
+
 #ifdef NEED_CPU_H
 #ifdef CONFIG_USER_ONLY
     /**
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 7188a409a0..16b0f8a097 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -467,6 +467,8 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                      MemTxResult response, uintptr_t retaddr);
 #endif
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *pflags)
 {
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index bc0c84873f..d20e2bd90e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3151,6 +3151,8 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
 }
 #endif
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
                           uint64_t *cs_base, uint32_t *flags);
 
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d185d20dcb..0c0aa580f5 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -193,6 +193,8 @@ enum {
     TB_FLAGS_SKIP = 2,
 };
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *pflags)
 {
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 3904e5448c..dbd6fb05f0 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -273,6 +273,8 @@ enum {
 
 #include "exec/cpu-all.h"
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 3eef58fe8f..935a9c3276 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -134,6 +134,8 @@ struct ArchCPU {
 
 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index a92dc352cb..cdb2904936 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -314,6 +314,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);
 #define TB_FLAG_PRIV_SHIFT  8
 #define TB_FLAG_UNALIGN     0x400
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *pflags)
 {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 952174bb6f..954495fff0 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2354,6 +2354,8 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
 #include "hw/i386/apic.h"
 #endif
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ec37579fd6..d814ba08dd 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -443,6 +443,8 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
 #define HW_FLAGS_VA32       0x20
 #define HW_FLAGS_EUEN_ASXE  0x40
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 346427e144..2790d61115 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -604,6 +604,8 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
 #define TB_FLAGS_TRACE          16
 #define TB_FLAGS_TRACE_BIT      (1 << TB_FLAGS_TRACE)
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index c0c7574dbd..8058dcac7f 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -415,6 +415,8 @@ void mb_tcg_init(void);
 /* Ensure there is no overlap between the two masks. */
 QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7329226d39..caa12a2dd3 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1362,6 +1362,8 @@ void cpu_mips_clock_init(MIPSCPU *cpu);
 /* helper.c */
 target_ulong exception_resume_pc(CPUMIPSState *env);
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 4164a3432e..32002b819a 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -286,6 +286,8 @@ FIELD(TBFLAGS, CRS0, 0, 1)  /* Set if CRS == 0. */
 FIELD(TBFLAGS, U, 1, 1)     /* Overlaps CR_STATUS_U */
 FIELD(TBFLAGS, R0_0, 2, 1)  /* Set if R0 == 0. */
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b1b7db5cbd..d42800242f 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -351,6 +351,8 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
     env->shadow_gpr[0][i] = val;
 }
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 67e6b2effd..ced4e53024 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2716,6 +2716,8 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer);
  */
 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 #ifdef CONFIG_DEBUG_TCG
 void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
                           uint64_t *cs_base, uint32_t *flags);
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index c53593d7aa..996f121bcd 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -149,6 +149,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
 #define RX_CPU_IRQ 0
 #define RX_CPU_FIR 1
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 43a46a5a06..2e184aabf5 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -416,6 +416,8 @@ static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch)
 
 #include "tcg/tcg_s390x.h"
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index f3cdd17c62..ae55cd15a4 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -747,6 +747,8 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
 #define TB_FLAG_HYPER        (1 << 7)
 #define TB_FLAG_ASI_SHIFT    24
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *pflags)
 {
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 6b8d0636d2..3826b779e4 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -734,6 +734,8 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
 
 #include "exec/cpu-all.h"
 
+#define TARGET_HAS_CPU_GET_TB_CPU_STATE
+
 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index c1f57e894a..7b538d2b9c 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -221,6 +221,16 @@ void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
     cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
 }
 
+#ifndef TARGET_HAS_CPU_GET_TB_CPU_STATE
+void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc,
+                          uint64_t *cs_base, uint32_t *flags)
+{
+    CPUState *cpu = env_cpu(env);
+
+    cpu->cc->tcg_ops->get_cpu_state(env, pc, cs_base, flags);
+}
+#endif
+
 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
 {
     /*
-- 
2.41.0

[PATCH-for-9.1 03/27] target/alpha: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/alpha/cpu.h | 13 -------------
 target/alpha/cpu.c | 12 ++++++++++++
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 16b0f8a097..b7f294d08a 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -467,19 +467,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                      MemTxResult response, uintptr_t retaddr);
 #endif
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *pflags)
-{
-    *pc = env->pc;
-    *cs_base = 0;
-    *pflags = env->flags & ENV_FLAG_TB_MASK;
-#ifdef CONFIG_USER_ONLY
-    *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#endif
-}
-
 #ifdef CONFIG_USER_ONLY
 /* Copied from linux ieee_swcr_to_fpcr.  */
 static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 05f9ee41e9..7efeda02dc 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -49,6 +49,17 @@ static void alpha_restore_state_to_opc(CPUState *cs,
     cpu->env.pc = data[0];
 }
 
+static void alpha_get_cpu_state(CPUAlphaState *env, vaddr *pc,
+                                uint64_t *cs_base, uint32_t *pflags)
+{
+    *pc = env->pc;
+    *cs_base = 0;
+    *pflags = env->flags & ENV_FLAG_TB_MASK;
+#ifdef CONFIG_USER_ONLY
+    *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
+}
+
 static bool alpha_cpu_has_work(CPUState *cs)
 {
     /* Here we are checking to see if the CPU should wake up from HALT.
@@ -194,6 +205,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
 static const TCGCPUOps alpha_tcg_ops = {
     .initialize = alpha_translate_init,
     .restore_state_to_opc = alpha_restore_state_to_opc,
+    .get_cpu_state = alpha_get_cpu_state,
 
 #ifdef CONFIG_USER_ONLY
     .record_sigsegv = alpha_cpu_record_sigsegv,
-- 
2.41.0

[PATCH-for-9.1 04/27] target/arm: Restrict TCG-specific declarations

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/internals.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index dd3da211a3..087caaf2bd 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -346,13 +346,13 @@ void register_cp_regs_for_features(ARMCPU *cpu);
 void init_cpreg_list(ARMCPU *cpu);
 
 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
+
+#ifdef CONFIG_TCG
 void arm_translate_init(void);
 
 void arm_restore_state_to_opc(CPUState *cs,
                               const TranslationBlock *tb,
                               const uint64_t *data);
-
-#ifdef CONFIG_TCG
 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 #endif /* CONFIG_TCG */
 
-- 
2.41.0

[PATCH-for-9.1 05/27] target/arm: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Move mve_no_pred() along because it is only used by
arm_get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu.h         |   5 --
 target/arm/internals.h   |   2 +
 target/arm/cpu.c         | 110 +++++++++++++++++++++++++++++++++++++++
 target/arm/helper.c      | 109 --------------------------------------
 target/arm/tcg-stubs.c   |   4 --
 target/arm/tcg/cpu-v7m.c |   1 +
 6 files changed, 113 insertions(+), 118 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d20e2bd90e..c563ff2b77 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3151,11 +3151,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
 }
 #endif
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
-                          uint64_t *cs_base, uint32_t *flags);
-
 enum {
     QEMU_PSCI_CONDUIT_DISABLED = 0,
     QEMU_PSCI_CONDUIT_SMC = 1,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 087caaf2bd..5daef30569 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -353,6 +353,8 @@ void arm_translate_init(void);
 void arm_restore_state_to_opc(CPUState *cs,
                               const TranslationBlock *tb,
                               const uint64_t *data);
+void arm_get_cpu_state(CPUARMState *env, vaddr *pc,
+                       uint64_t *cs_base, uint32_t *flags);
 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 #endif /* CONFIG_TCG */
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ab8d007a86..8e41e1c427 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -120,6 +120,115 @@ void arm_restore_state_to_opc(CPUState *cs,
         env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
     }
 }
+
+static bool mve_no_pred(CPUARMState *env)
+{
+    /*
+     * Return true if there is definitely no predication of MVE
+     * instructions by VPR or LTPSIZE. (Returning false even if there
+     * isn't any predication is OK; generated code will just be
+     * a little worse.)
+     * If the CPU does not implement MVE then this TB flag is always 0.
+     *
+     * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
+     * logic in gen_update_fp_context() needs to be updated to match.
+     *
+     * We do not include the effect of the ECI bits here -- they are
+     * tracked in other TB flags. This simplifies the logic for
+     * "when did we emit code that changes the MVE_NO_PRED TB flag
+     * and thus need to end the TB?".
+     */
+    if (cpu_isar_feature(aa32_mve, env_archcpu(env))) {
+        return false;
+    }
+    if (env->v7m.vpr) {
+        return false;
+    }
+    if (env->v7m.ltpsize < 4) {
+        return false;
+    }
+    return true;
+}
+
+void arm_get_cpu_state(CPUARMState *env, vaddr *pc,
+                       uint64_t *cs_base, uint32_t *pflags)
+{
+    CPUARMTBFlags flags;
+
+    assert_hflags_rebuild_correctly(env);
+    flags = env->hflags;
+
+    if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) {
+        *pc = env->pc;
+        if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
+            DP_TBFLAG_A64(flags, BTYPE, env->btype);
+        }
+    } else {
+        *pc = env->regs[15];
+
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
+                FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
+                != env->v7m.secure) {
+                DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1);
+            }
+
+            if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
+                (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
+                 (env->v7m.secure &&
+                  !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
+                /*
+                 * ASPEN is set, but FPCA/SFPA indicate that there is no
+                 * active FP context; we must create a new FP context before
+                 * executing any FP insn.
+                 */
+                DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1);
+            }
+
+            bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
+            if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
+                DP_TBFLAG_M32(flags, LSPACT, 1);
+            }
+
+            if (mve_no_pred(env)) {
+                DP_TBFLAG_M32(flags, MVE_NO_PRED, 1);
+            }
+        } else {
+            /*
+             * Note that XSCALE_CPAR shares bits with VECSTRIDE.
+             * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
+             */
+            if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+                DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar);
+            } else {
+                DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len);
+                DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride);
+            }
+            if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
+                DP_TBFLAG_A32(flags, VFPEN, 1);
+            }
+        }
+
+        DP_TBFLAG_AM32(flags, THUMB, env->thumb);
+        DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits);
+    }
+
+    /*
+     * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
+     * states defined in the ARM ARM for software singlestep:
+     *  SS_ACTIVE   PSTATE.SS   State
+     *     0            x       Inactive (the TB flag for SS is always 0)
+     *     1            0       Active-pending
+     *     1            1       Active-not-pending
+     * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
+     */
+    if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) {
+        DP_TBFLAG_ANY(flags, PSTATE__SS, 1);
+    }
+
+    *pflags = flags.flags;
+    *cs_base = flags.flags2;
+}
 #endif /* CONFIG_TCG */
 
 static bool arm_cpu_has_work(CPUState *cs)
@@ -2479,6 +2588,7 @@ static const TCGCPUOps arm_tcg_ops = {
     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
     .debug_excp_handler = arm_debug_excp_handler,
     .restore_state_to_opc = arm_restore_state_to_opc,
+    .get_cpu_state = arm_get_cpu_state,
 
 #ifdef CONFIG_USER_ONLY
     .record_sigsegv = arm_cpu_record_sigsegv,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3f3a5b55d4..e50bec27d9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12509,115 +12509,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
     return arm_mmu_idx_el(env, arm_current_el(env));
 }
 
-static bool mve_no_pred(CPUARMState *env)
-{
-    /*
-     * Return true if there is definitely no predication of MVE
-     * instructions by VPR or LTPSIZE. (Returning false even if there
-     * isn't any predication is OK; generated code will just be
-     * a little worse.)
-     * If the CPU does not implement MVE then this TB flag is always 0.
-     *
-     * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
-     * logic in gen_update_fp_context() needs to be updated to match.
-     *
-     * We do not include the effect of the ECI bits here -- they are
-     * tracked in other TB flags. This simplifies the logic for
-     * "when did we emit code that changes the MVE_NO_PRED TB flag
-     * and thus need to end the TB?".
-     */
-    if (cpu_isar_feature(aa32_mve, env_archcpu(env))) {
-        return false;
-    }
-    if (env->v7m.vpr) {
-        return false;
-    }
-    if (env->v7m.ltpsize < 4) {
-        return false;
-    }
-    return true;
-}
-
-void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
-                          uint64_t *cs_base, uint32_t *pflags)
-{
-    CPUARMTBFlags flags;
-
-    assert_hflags_rebuild_correctly(env);
-    flags = env->hflags;
-
-    if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) {
-        *pc = env->pc;
-        if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
-            DP_TBFLAG_A64(flags, BTYPE, env->btype);
-        }
-    } else {
-        *pc = env->regs[15];
-
-        if (arm_feature(env, ARM_FEATURE_M)) {
-            if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
-                FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
-                != env->v7m.secure) {
-                DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1);
-            }
-
-            if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
-                (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
-                 (env->v7m.secure &&
-                  !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
-                /*
-                 * ASPEN is set, but FPCA/SFPA indicate that there is no
-                 * active FP context; we must create a new FP context before
-                 * executing any FP insn.
-                 */
-                DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1);
-            }
-
-            bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
-            if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
-                DP_TBFLAG_M32(flags, LSPACT, 1);
-            }
-
-            if (mve_no_pred(env)) {
-                DP_TBFLAG_M32(flags, MVE_NO_PRED, 1);
-            }
-        } else {
-            /*
-             * Note that XSCALE_CPAR shares bits with VECSTRIDE.
-             * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
-             */
-            if (arm_feature(env, ARM_FEATURE_XSCALE)) {
-                DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar);
-            } else {
-                DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len);
-                DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride);
-            }
-            if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
-                DP_TBFLAG_A32(flags, VFPEN, 1);
-            }
-        }
-
-        DP_TBFLAG_AM32(flags, THUMB, env->thumb);
-        DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits);
-    }
-
-    /*
-     * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
-     * states defined in the ARM ARM for software singlestep:
-     *  SS_ACTIVE   PSTATE.SS   State
-     *     0            x       Inactive (the TB flag for SS is always 0)
-     *     1            0       Active-pending
-     *     1            1       Active-not-pending
-     * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
-     */
-    if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) {
-        DP_TBFLAG_ANY(flags, PSTATE__SS, 1);
-    }
-
-    *pflags = flags.flags;
-    *cs_base = flags.flags2;
-}
-
 #ifdef TARGET_AARCH64
 /*
  * The manual says that when SVE is enabled and VQ is widened the
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
index 152b172e24..1a7ddb3664 100644
--- a/target/arm/tcg-stubs.c
+++ b/target/arm/tcg-stubs.c
@@ -21,7 +21,3 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
 {
     g_assert_not_reached();
 }
-/* Temporarily while cpu_get_tb_cpu_state() is still in common code */
-void assert_hflags_rebuild_correctly(CPUARMState *env)
-{
-}
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index c059c681e9..de4a1ff81b 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -237,6 +237,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = {
     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
     .debug_excp_handler = arm_debug_excp_handler,
     .restore_state_to_opc = arm_restore_state_to_opc,
+    .get_cpu_state = arm_get_cpu_state,
 
 #ifdef CONFIG_USER_ONLY
     .record_sigsegv = arm_cpu_record_sigsegv,
-- 
2.41.0

[PATCH-for-9.1 06/27] target/avr: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/avr/cpu.h | 20 --------------------
 target/avr/cpu.c | 19 +++++++++++++++++++
 2 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 0c0aa580f5..284041a87a 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -193,26 +193,6 @@ enum {
     TB_FLAGS_SKIP = 2,
 };
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *pflags)
-{
-    uint32_t flags = 0;
-
-    *pc = env->pc_w * 2;
-    *cs_base = 0;
-
-    if (env->fullacc) {
-        flags |= TB_FLAGS_FULL_ACCESS;
-    }
-    if (env->skip) {
-        flags |= TB_FLAGS_SKIP;
-    }
-
-    *pflags = flags;
-}
-
 static inline int cpu_interrupts_enabled(CPUAVRState *env)
 {
     return env->sregI != 0;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 45ee1b5f89..c765f49c9f 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -66,6 +66,24 @@ static void avr_restore_state_to_opc(CPUState *cs,
     cpu_env(cs)->pc_w = data[0];
 }
 
+static void avr_get_cpu_state(CPUAVRState *env, vaddr *pc,
+                              uint64_t *cs_base, uint32_t *pflags)
+{
+    uint32_t flags = 0;
+
+    *pc = env->pc_w * 2;
+    *cs_base = 0;
+
+    if (env->fullacc) {
+        flags |= TB_FLAGS_FULL_ACCESS;
+    }
+    if (env->skip) {
+        flags |= TB_FLAGS_SKIP;
+    }
+
+    *pflags = flags;
+}
+
 static void avr_cpu_reset_hold(Object *obj)
 {
     CPUState *cs = CPU(obj);
@@ -209,6 +227,7 @@ static const TCGCPUOps avr_tcg_ops = {
     .initialize = avr_cpu_tcg_init,
     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
     .restore_state_to_opc = avr_restore_state_to_opc,
+    .get_cpu_state = avr_get_cpu_state,
     .cpu_exec_interrupt = avr_cpu_exec_interrupt,
     .tlb_fill = avr_cpu_tlb_fill,
     .do_interrupt = avr_cpu_do_interrupt,
-- 
2.41.0

[PATCH-for-9.1 07/27] target/cris: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/cris/cpu.h | 12 ------------
 target/cris/cpu.c | 11 +++++++++++
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index dbd6fb05f0..6df53f49c4 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -273,16 +273,4 @@ enum {
 
 #include "exec/cpu-all.h"
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->pc;
-    *cs_base = 0;
-    *flags = env->dslot |
-            (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
-				     | X_FLAG | PFIX_FLAG));
-}
-
 #endif
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index eb4bddcb7e..8d0b92b96d 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -51,6 +51,15 @@ static void cris_restore_state_to_opc(CPUState *cs,
     cpu->env.pc = data[0];
 }
 
+static void cris_get_cpu_state(CPUCRISState *env, vaddr *pc,
+                               uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->pc;
+    *cs_base = 0;
+    *flags = env->dslot |
+        (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG | PFIX_FLAG));
+}
+
 static bool cris_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -182,6 +191,7 @@ static const struct SysemuCPUOps cris_sysemu_ops = {
 static const TCGCPUOps crisv10_tcg_ops = {
     .initialize = cris_initialize_crisv10_tcg,
     .restore_state_to_opc = cris_restore_state_to_opc,
+    .get_cpu_state = cris_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = cris_cpu_tlb_fill,
@@ -193,6 +203,7 @@ static const TCGCPUOps crisv10_tcg_ops = {
 static const TCGCPUOps crisv32_tcg_ops = {
     .initialize = cris_initialize_tcg,
     .restore_state_to_opc = cris_restore_state_to_opc,
+    .get_cpu_state = cris_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = cris_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 08/27] target/hexagon: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/hexagon/cpu.h | 14 --------------
 target/hexagon/cpu.c | 13 +++++++++++++
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 935a9c3276..1d42c33827 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -134,20 +134,6 @@ struct ArchCPU {
 
 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    uint32_t hex_flags = 0;
-    *pc = env->gpr[HEX_REG_PC];
-    *cs_base = 0;
-    if (*pc == env->gpr[HEX_REG_SA0]) {
-        hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
-    }
-    *flags = hex_flags;
-}
-
 typedef HexagonCPU ArchCPU;
 
 void hexagon_translate_init(void);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 3a716b9be3..5e0a9441f2 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -273,6 +273,18 @@ static void hexagon_restore_state_to_opc(CPUState *cs,
     cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
 }
 
+static void hexagon_get_cpu_state(CPUHexagonState *env, vaddr *pc,
+                                  uint64_t *cs_base, uint32_t *flags)
+{
+    uint32_t hex_flags = 0;
+    *pc = env->gpr[HEX_REG_PC];
+    *cs_base = 0;
+    if (*pc == env->gpr[HEX_REG_SA0]) {
+        hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
+    }
+    *flags = hex_flags;
+}
+
 static void hexagon_cpu_reset_hold(Object *obj)
 {
     CPUState *cs = CPU(obj);
@@ -327,6 +339,7 @@ static const TCGCPUOps hexagon_tcg_ops = {
     .initialize = hexagon_translate_init,
     .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
     .restore_state_to_opc = hexagon_restore_state_to_opc,
+    .get_cpu_state = hexagon_get_cpu_state,
 };
 
 static void hexagon_cpu_class_init(ObjectClass *c, void *data)
-- 
2.41.0

[PATCH-for-9.1 09/27] target/hppa: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/hppa/cpu.h | 44 --------------------------------------------
 target/hppa/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 44 deletions(-)

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index cdb2904936..9bc54124c1 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -314,50 +314,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);
 #define TB_FLAG_PRIV_SHIFT  8
 #define TB_FLAG_UNALIGN     0x400
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *pflags)
-{
-    uint32_t flags = env->psw_n * PSW_N;
-
-    /* TB lookup assumes that PC contains the complete virtual address.
-       If we leave space+offset separate, we'll get ITLB misses to an
-       incomplete virtual address.  This also means that we must separate
-       out current cpu privilege from the low bits of IAOQ_F.  */
-#ifdef CONFIG_USER_ONLY
-    *pc = env->iaoq_f & -4;
-    *cs_base = env->iaoq_b & -4;
-    flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#else
-    /* ??? E, T, H, L, B bits need to be here, when implemented.  */
-    flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
-    flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
-
-    *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
-                            env->iaoq_f & -4);
-    *cs_base = env->iasq_f;
-
-    /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
-       low 32-bits of CS_BASE.  This will succeed for all direct branches,
-       which is the primary case we care about -- using goto_tb within a page.
-       Failure is indicated by a zero difference.  */
-    if (env->iasq_f == env->iasq_b) {
-        target_long diff = env->iaoq_b - env->iaoq_f;
-        if (diff == (int32_t)diff) {
-            *cs_base |= (uint32_t)diff;
-        }
-    }
-    if ((env->sr[4] == env->sr[5])
-        & (env->sr[4] == env->sr[6])
-        & (env->sr[4] == env->sr[7])) {
-        flags |= TB_FLAG_SR_SAME;
-    }
-#endif
-
-    *pflags = flags;
-}
-
 target_ulong cpu_hppa_get_psw(CPUHPPAState *env);
 void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong);
 void cpu_hppa_loaded_fr0(CPUHPPAState *env);
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 3831cb6db2..f2dc1e79e9 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -89,6 +89,48 @@ static void hppa_restore_state_to_opc(CPUState *cs,
     cpu->env.psw_n = 0;
 }
 
+static void hppa_get_cpu_state(CPUHPPAState *env, vaddr *pc,
+                               uint64_t *cs_base, uint32_t *pflags)
+{
+    uint32_t flags = env->psw_n * PSW_N;
+
+    /* TB lookup assumes that PC contains the complete virtual address.
+       If we leave space+offset separate, we'll get ITLB misses to an
+       incomplete virtual address.  This also means that we must separate
+       out current cpu privilege from the low bits of IAOQ_F.  */
+#ifdef CONFIG_USER_ONLY
+    *pc = env->iaoq_f & -4;
+    *cs_base = env->iaoq_b & -4;
+    flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#else
+    /* ??? E, T, H, L, B bits need to be here, when implemented.  */
+    flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
+    flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
+
+    *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
+                            env->iaoq_f & -4);
+    *cs_base = env->iasq_f;
+
+    /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
+       low 32-bits of CS_BASE.  This will succeed for all direct branches,
+       which is the primary case we care about -- using goto_tb within a page.
+       Failure is indicated by a zero difference.  */
+    if (env->iasq_f == env->iasq_b) {
+        target_long diff = env->iaoq_b - env->iaoq_f;
+        if (diff == (int32_t)diff) {
+            *cs_base |= (uint32_t)diff;
+        }
+    }
+    if ((env->sr[4] == env->sr[5])
+        & (env->sr[4] == env->sr[6])
+        & (env->sr[4] == env->sr[7])) {
+        flags |= TB_FLAG_SR_SAME;
+    }
+#endif
+
+    *pflags = flags;
+}
+
 static bool hppa_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -186,6 +228,7 @@ static const TCGCPUOps hppa_tcg_ops = {
     .initialize = hppa_translate_init,
     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
     .restore_state_to_opc = hppa_restore_state_to_opc,
+    .get_cpu_state = hppa_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = hppa_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 10/27] target/i386: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Note, now x86_get_cpu_state() is restricted to TCG.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/i386/cpu.h         | 16 ----------------
 target/i386/cpu.c         |  2 +-
 target/i386/tcg/tcg-cpu.c | 15 +++++++++++++++
 3 files changed, 16 insertions(+), 17 deletions(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 954495fff0..390abc969e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2354,22 +2354,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
 #include "hw/i386/apic.h"
 #endif
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *flags = env->hflags |
-        (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
-    if (env->hflags & HF_CS64_MASK) {
-        *cs_base = 0;
-        *pc = env->eip;
-    } else {
-        *cs_base = env->segs[R_CS].base;
-        *pc = (uint32_t)(*cs_base + env->eip);
-    }
-}
-
 void do_cpu_init(X86CPU *cpu);
 
 #define MCE_INJECT_BROADCAST    1
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9a210d8d92..249b6fe0bb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7679,7 +7679,7 @@ static vaddr x86_cpu_get_pc(CPUState *cs)
 {
     X86CPU *cpu = X86_CPU(cs);
 
-    /* Match cpu_get_tb_cpu_state. */
+    /* Match x86_get_cpu_state. */
     return cpu->env.eip + cpu->env.segs[R_CS].base;
 }
 
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index cca19cd40e..a89c11a34b 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -93,6 +93,20 @@ static void x86_restore_state_to_opc(CPUState *cs,
     }
 }
 
+static inline void x86_get_cpu_state(CPUX86State *env, vaddr *pc,
+                                     uint64_t *cs_base, uint32_t *flags)
+{
+    *flags = env->hflags |
+        (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
+    if (env->hflags & HF_CS64_MASK) {
+        *cs_base = 0;
+        *pc = env->eip;
+    } else {
+        *cs_base = env->segs[R_CS].base;
+        *pc = (uint32_t)(*cs_base + env->eip);
+    }
+}
+
 #ifndef CONFIG_USER_ONLY
 static bool x86_debug_check_breakpoint(CPUState *cs)
 {
@@ -110,6 +124,7 @@ static const TCGCPUOps x86_tcg_ops = {
     .initialize = tcg_x86_init,
     .synchronize_from_tb = x86_cpu_synchronize_from_tb,
     .restore_state_to_opc = x86_restore_state_to_opc,
+    .get_cpu_state = x86_get_cpu_state,
     .cpu_exec_enter = x86_cpu_exec_enter,
     .cpu_exec_exit = x86_cpu_exec_exit,
 #ifdef CONFIG_USER_ONLY
-- 
2.41.0

[PATCH-for-9.1 11/27] target/loongarch: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/loongarch/cpu.h | 14 --------------
 target/loongarch/cpu.c | 15 +++++++++++++++
 2 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index d814ba08dd..14f1d37606 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -443,20 +443,6 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
 #define HW_FLAGS_VA32       0x20
 #define HW_FLAGS_EUEN_ASXE  0x40
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->pc;
-    *cs_base = 0;
-    *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
-    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
-    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
-    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
-    *flags |= is_va32(env) * HW_FLAGS_VA32;
-}
-
 #include "exec/cpu-all.h"
 
 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index f6ffb3aadb..a2d772ca5f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -340,6 +340,20 @@ static void loongarch_restore_state_to_opc(CPUState *cs,
 {
     set_pc(cpu_env(cs), data[0]);
 }
+
+static void loongarch_get_cpu_state(CPULoongArchState *env, vaddr *pc,
+                                    uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->pc;
+    *cs_base = 0;
+    *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
+    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
+    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
+    *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
+    *flags |= is_va32(env) * HW_FLAGS_VA32;
+}
+
+
 #endif /* CONFIG_TCG */
 
 static bool loongarch_cpu_has_work(CPUState *cs)
@@ -729,6 +743,7 @@ static const TCGCPUOps loongarch_tcg_ops = {
     .initialize = loongarch_translate_init,
     .synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
     .restore_state_to_opc = loongarch_restore_state_to_opc,
+    .get_cpu_state = loongarch_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = loongarch_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 12/27] target/m68k: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/m68k/cpu.h | 18 ------------------
 target/m68k/cpu.c | 17 +++++++++++++++++
 2 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 2790d61115..2f5f973bd4 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -604,24 +604,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
 #define TB_FLAGS_TRACE          16
 #define TB_FLAGS_TRACE_BIT      (1 << TB_FLAGS_TRACE)
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->pc;
-    *cs_base = 0;
-    *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
-    if (env->sr & SR_S) {
-        *flags |= TB_FLAGS_MSR_S;
-        *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
-        *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
-    }
-    if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
-        *flags |= TB_FLAGS_TRACE;
-    }
-}
-
 void dump_mmu(CPUM68KState *env);
 
 #endif
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 7c8efbb42c..3bb9f58651 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -51,6 +51,22 @@ static void m68k_restore_state_to_opc(CPUState *cs,
     }
 }
 
+static void m68k_get_cpu_state(CPUM68KState *env, vaddr *pc,
+                               uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->pc;
+    *cs_base = 0;
+    *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
+    if (env->sr & SR_S) {
+        *flags |= TB_FLAGS_MSR_S;
+        *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
+        *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
+    }
+    if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
+        *flags |= TB_FLAGS_TRACE;
+    }
+}
+
 static bool m68k_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -524,6 +540,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
 static const TCGCPUOps m68k_tcg_ops = {
     .initialize = m68k_tcg_init,
     .restore_state_to_opc = m68k_restore_state_to_opc,
+    .get_cpu_state = m68k_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = m68k_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 13/27] target/microblaze: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/microblaze/cpu.h | 10 ----------
 target/microblaze/cpu.c |  9 +++++++++
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 8058dcac7f..956269250c 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -415,16 +415,6 @@ void mb_tcg_init(void);
 /* Ensure there is no overlap between the two masks. */
 QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->pc;
-    *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
-    *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
-}
-
 #if !defined(CONFIG_USER_ONLY)
 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                      MMUAccessType access_type, int mmu_idx,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 96c2b71f7f..ded4c7a0de 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -113,6 +113,14 @@ static void mb_restore_state_to_opc(CPUState *cs,
     cpu->env.iflags = data[1];
 }
 
+static void mb_get_cpu_state(CPUMBState *env, vaddr *pc,
+                             uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->pc;
+    *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
+    *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
+}
+
 static bool mb_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -408,6 +416,7 @@ static const TCGCPUOps mb_tcg_ops = {
     .initialize = mb_tcg_init,
     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
     .restore_state_to_opc = mb_restore_state_to_opc,
+    .get_cpu_state = mb_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = mb_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 14/27] target/mips: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/cpu.h              | 11 -----------
 target/mips/tcg/tcg-internal.h |  2 ++
 target/mips/cpu.c              |  1 +
 target/mips/tcg/translate.c    |  9 +++++++++
 4 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index caa12a2dd3..9d2f7e0194 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1362,17 +1362,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu);
 /* helper.c */
 target_ulong exception_resume_pc(CPUMIPSState *env);
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->active_tc.PC;
-    *cs_base = 0;
-    *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
-                            MIPS_HFLAG_HWRENA_ULR);
-}
-
 /**
  * mips_cpu_create_with_clock:
  * @typename: a MIPS CPU type.
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index aef032c48d..c54d5c64b2 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -24,6 +24,8 @@ G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 void mips_restore_state_to_opc(CPUState *cs,
                                const TranslationBlock *tb,
                                const uint64_t *data);
+void mips_get_cpu_state(CPUMIPSState *env, vaddr *pc,
+                        uint64_t *cs_base, uint32_t *flags);
 
 const char *mips_exception_name(int32_t exception);
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 8d8f690a53..6cc64b7628 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -551,6 +551,7 @@ static const TCGCPUOps mips_tcg_ops = {
     .initialize = mips_tcg_init,
     .synchronize_from_tb = mips_cpu_synchronize_from_tb,
     .restore_state_to_opc = mips_restore_state_to_opc,
+    .get_cpu_state = mips_get_cpu_state,
 
 #if !defined(CONFIG_USER_ONLY)
     .tlb_fill = mips_cpu_tlb_fill,
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 06c108cc9c..4ecac13a8f 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15581,3 +15581,12 @@ void mips_restore_state_to_opc(CPUState *cs,
         break;
     }
 }
+
+void mips_get_cpu_state(CPUMIPSState *env, vaddr *pc,
+                        uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->active_tc.PC;
+    *cs_base = 0;
+    *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
+                            MIPS_HFLAG_HWRENA_ULR);
+}
-- 
2.41.0

[PATCH-for-9.1 15/27] target/nios2: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/nios2/cpu.h | 14 --------------
 target/nios2/cpu.c | 13 +++++++++++++
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 32002b819a..d0616723fe 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -286,18 +286,4 @@ FIELD(TBFLAGS, CRS0, 0, 1)  /* Set if CRS == 0. */
 FIELD(TBFLAGS, U, 1, 1)     /* Overlaps CR_STATUS_U */
 FIELD(TBFLAGS, R0_0, 2, 1)  /* Set if R0 == 0. */
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS);
-
-    *pc = env->pc;
-    *cs_base = 0;
-    *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U)
-           | (crs ? 0 : R_TBFLAGS_CRS0_MASK)
-           | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK);
-}
-
 #endif /* NIOS2_CPU_H */
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 679aff5730..d1a98c47ad 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -43,6 +43,18 @@ static void nios2_restore_state_to_opc(CPUState *cs,
     cpu_env(cs)->pc = data[0];
 }
 
+static void nios2_get_cpu_state(CPUNios2State *env, vaddr *pc,
+                                uint64_t *cs_base, uint32_t *flags)
+{
+    unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS);
+
+    *pc = env->pc;
+    *cs_base = 0;
+    *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U)
+             | (crs ? 0 : R_TBFLAGS_CRS0_MASK)
+             | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK);
+}
+
 static bool nios2_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -354,6 +366,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
 static const TCGCPUOps nios2_tcg_ops = {
     .initialize = nios2_tcg_init,
     .restore_state_to_opc = nios2_restore_state_to_opc,
+    .get_cpu_state = nios2_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = nios2_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 16/27] target/openrisc: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/openrisc/cpu.h | 12 ------------
 target/openrisc/cpu.c | 11 +++++++++++
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index d42800242f..6997c7534e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -351,18 +351,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
     env->shadow_gpr[0][i] = val;
 }
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->pc;
-    *cs_base = 0;
-    *flags = (env->dflag ? TB_FLAGS_DFLAG : 0)
-           | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
-           | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
-}
-
 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
 {
     return (env->sr
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 33c45dbf04..ce44ac0316 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -62,6 +62,16 @@ static void openrisc_restore_state_to_opc(CPUState *cs,
     }
 }
 
+static void openrisc_get_cpu_state(CPUOpenRISCState *env, vaddr *pc,
+                                   uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->pc;
+    *cs_base = 0;
+    *flags = (env->dflag ? TB_FLAGS_DFLAG : 0)
+             | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
+             | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
+}
+
 static bool openrisc_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
@@ -229,6 +239,7 @@ static const TCGCPUOps openrisc_tcg_ops = {
     .initialize = openrisc_translate_init,
     .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
     .restore_state_to_opc = openrisc_restore_state_to_opc,
+    .get_cpu_state = openrisc_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = openrisc_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 17/27] target/ppc: Indent ppc_tcg_ops[] with 4 spaces

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu_init.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 7e65f08147..464e91faa2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7360,22 +7360,22 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
 #include "hw/core/tcg-cpu-ops.h"
 
 static const TCGCPUOps ppc_tcg_ops = {
-  .initialize = ppc_translate_init,
-  .restore_state_to_opc = ppc_restore_state_to_opc,
+    .initialize = ppc_translate_init,
+    .restore_state_to_opc = ppc_restore_state_to_opc,
 
 #ifdef CONFIG_USER_ONLY
-  .record_sigsegv = ppc_cpu_record_sigsegv,
+    .record_sigsegv = ppc_cpu_record_sigsegv,
 #else
-  .tlb_fill = ppc_cpu_tlb_fill,
-  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
-  .do_interrupt = ppc_cpu_do_interrupt,
-  .cpu_exec_enter = ppc_cpu_exec_enter,
-  .cpu_exec_exit = ppc_cpu_exec_exit,
-  .do_unaligned_access = ppc_cpu_do_unaligned_access,
-  .do_transaction_failed = ppc_cpu_do_transaction_failed,
-  .debug_excp_handler = ppc_cpu_debug_excp_handler,
-  .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
-  .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
+    .tlb_fill = ppc_cpu_tlb_fill,
+    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+    .do_interrupt = ppc_cpu_do_interrupt,
+    .cpu_exec_enter = ppc_cpu_exec_enter,
+    .cpu_exec_exit = ppc_cpu_exec_exit,
+    .do_unaligned_access = ppc_cpu_do_unaligned_access,
+    .do_transaction_failed = ppc_cpu_do_transaction_failed,
+    .debug_excp_handler = ppc_cpu_debug_excp_handler,
+    .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
+    .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
 #endif /* !CONFIG_USER_ONLY */
 };
 #endif /* CONFIG_TCG */
-- 
2.41.0

[PATCH-for-9.1 18/27] target/ppc: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state(),
unifying with the method declared in target/ppc/helper_regs.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu.h         | 16 +++-------------
 target/ppc/cpu_init.c    |  1 +
 target/ppc/helper_regs.c | 13 +++++++------
 3 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index ced4e53024..6aa18db335 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2716,19 +2716,9 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer);
  */
 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-#ifdef CONFIG_DEBUG_TCG
-void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
-                          uint64_t *cs_base, uint32_t *flags);
-#else
-static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->nip;
-    *cs_base = 0;
-    *flags = env->hflags;
-}
+#ifdef CONFIG_TCG
+void ppc_get_cpu_state(CPUPPCState *env, vaddr *pc,
+                       uint64_t *cs_base, uint32_t *flags);
 #endif
 
 G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 464e91faa2..673559b444 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7362,6 +7362,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
 static const TCGCPUOps ppc_tcg_ops = {
     .initialize = ppc_translate_init,
     .restore_state_to_opc = ppc_restore_state_to_opc,
+    .get_cpu_state = ppc_get_cpu_state,
 
 #ifdef CONFIG_USER_ONLY
     .record_sigsegv = ppc_cpu_record_sigsegv,
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 25258986e3..e62591067c 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -217,25 +217,26 @@ void hreg_update_pmu_hflags(CPUPPCState *env)
     env->hflags |= hreg_compute_pmu_hflags_value(env);
 }
 
-#ifdef CONFIG_DEBUG_TCG
-void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
-                          uint64_t *cs_base, uint32_t *flags)
+#ifdef CONFIG_TCG
+void ppc_get_cpu_state(CPUPPCState *env, vaddr *pc,
+                       uint64_t *cs_base, uint32_t *flags)
 {
     uint32_t hflags_current = env->hflags;
-    uint32_t hflags_rebuilt;
 
     *pc = env->nip;
     *cs_base = 0;
     *flags = hflags_current;
 
-    hflags_rebuilt = hreg_compute_hflags_value(env);
+#ifdef CONFIG_DEBUG_TCG
+    uint32_t hflags_rebuilt = hreg_compute_hflags_value(env);
     if (unlikely(hflags_current != hflags_rebuilt)) {
         cpu_abort(env_cpu(env),
                   "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
                   hflags_current, hflags_rebuilt);
     }
-}
 #endif
+}
+#endif /* CONFIG_TCG */
 
 void cpu_interrupt_exittb(CPUState *cs)
 {
-- 
2.41.0

[PATCH-for-9.1 19/27] target/riscv: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Note, now riscv_get_cpu_state() is restricted to TCG, and
is declared with static scope.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/cpu.h                      |  3 -
 target/riscv/cpu.c                      |  2 +-
 target/riscv/cpu_helper.c               | 87 ------------------------
 target/riscv/tcg/tcg-cpu.c              | 88 +++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvv.c.inc |  2 +-
 5 files changed, 90 insertions(+), 92 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3b1a02b944..d00d1be235 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -704,9 +704,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew,
     return vlen >> (vsew + 3 - lmul);
 }
 
-void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-                          uint64_t *cs_base, uint32_t *pflags);
-
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c160b9216b..ca537d0e0a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -889,7 +889,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
 
-    /* Match cpu_get_tb_cpu_state. */
+    /* Match riscv_get_cpu_state. */
     if (env->xl == MXL_RV32) {
         return env->pc & UINT32_MAX;
     }
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ce7322011d..e18a269358 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -25,7 +25,6 @@
 #include "pmu.h"
 #include "exec/exec-all.h"
 #include "instmap.h"
-#include "tcg/tcg-op.h"
 #include "trace.h"
 #include "semihosting/common-semi.h"
 #include "sysemu/cpu-timers.h"
@@ -62,92 +61,6 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
 #endif
 }
 
-void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-                          uint64_t *cs_base, uint32_t *pflags)
-{
-    RISCVCPU *cpu = env_archcpu(env);
-    RISCVExtStatus fs, vs;
-    uint32_t flags = 0;
-
-    *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
-    *cs_base = 0;
-
-    if (cpu->cfg.ext_zve32f) {
-        /*
-         * If env->vl equals to VLMAX, we can use generic vector operation
-         * expanders (GVEC) to accerlate the vector operations.
-         * However, as LMUL could be a fractional number. The maximum
-         * vector size can be operated might be less than 8 bytes,
-         * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
-         * only when maxsz >= 8 bytes.
-         */
-
-        /* lmul encoded as in DisasContext::lmul */
-        int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
-        uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
-        uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
-        uint32_t maxsz = vlmax << vsew;
-        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
-                           (maxsz >= 8);
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
-        flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew);
-        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
-                           FIELD_EX64(env->vtype, VTYPE, VLMUL));
-        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
-        flags = FIELD_DP32(flags, TB_FLAGS, VTA,
-                           FIELD_EX64(env->vtype, VTYPE, VTA));
-        flags = FIELD_DP32(flags, TB_FLAGS, VMA,
-                           FIELD_EX64(env->vtype, VTYPE, VMA));
-        flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
-    } else {
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
-    }
-
-#ifdef CONFIG_USER_ONLY
-    fs = EXT_STATUS_DIRTY;
-    vs = EXT_STATUS_DIRTY;
-#else
-    flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
-
-    flags |= riscv_env_mmu_index(env, 0);
-    fs = get_field(env->mstatus, MSTATUS_FS);
-    vs = get_field(env->mstatus, MSTATUS_VS);
-
-    if (env->virt_enabled) {
-        flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
-        /*
-         * Merge DISABLED and !DIRTY states using MIN.
-         * We will set both fields when dirtying.
-         */
-        fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
-        vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
-    }
-
-    /* With Zfinx, floating point is enabled/disabled by Smstateen. */
-    if (!riscv_has_ext(env, RVF)) {
-        fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE)
-             ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
-    }
-
-    if (cpu->cfg.debug && !icount_enabled()) {
-        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
-    }
-#endif
-
-    flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
-    flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
-    flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
-    flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
-    if (env->cur_pmmask != 0) {
-        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
-    }
-    if (env->cur_pmbase != 0) {
-        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
-    }
-
-    *pflags = flags;
-}
-
 void riscv_cpu_update_mask(CPURISCVState *env)
 {
     target_ulong mask = 0, base = 0;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ab6db817db..934007673e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -31,6 +31,7 @@
 #include "hw/core/accel-cpu.h"
 #include "hw/core/tcg-cpu-ops.h"
 #include "tcg/tcg.h"
+#include "sysemu/cpu-timers.h"
 
 /* Hash that stores user set extensions */
 static GHashTable *multi_ext_user_opts;
@@ -129,10 +130,97 @@ static void riscv_restore_state_to_opc(CPUState *cs,
     env->bins = data[1];
 }
 
+static void riscv_get_cpu_state(CPURISCVState *env, vaddr *pc,
+                                uint64_t *cs_base, uint32_t *pflags)
+{
+    RISCVCPU *cpu = env_archcpu(env);
+    RISCVExtStatus fs, vs;
+    uint32_t flags = 0;
+
+    *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
+    *cs_base = 0;
+
+    if (cpu->cfg.ext_zve32f) {
+        /*
+         * If env->vl equals to VLMAX, we can use generic vector operation
+         * expanders (GVEC) to accerlate the vector operations.
+         * However, as LMUL could be a fractional number. The maximum
+         * vector size can be operated might be less than 8 bytes,
+         * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
+         * only when maxsz >= 8 bytes.
+         */
+
+        /* lmul encoded as in DisasContext::lmul */
+        int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
+        uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+        uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
+        uint32_t maxsz = vlmax << vsew;
+        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
+                           (maxsz >= 8);
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
+        flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew);
+        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
+                           FIELD_EX64(env->vtype, VTYPE, VLMUL));
+        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
+        flags = FIELD_DP32(flags, TB_FLAGS, VTA,
+                           FIELD_EX64(env->vtype, VTYPE, VTA));
+        flags = FIELD_DP32(flags, TB_FLAGS, VMA,
+                           FIELD_EX64(env->vtype, VTYPE, VMA));
+        flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
+    } else {
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
+    }
+
+#ifdef CONFIG_USER_ONLY
+    fs = EXT_STATUS_DIRTY;
+    vs = EXT_STATUS_DIRTY;
+#else
+    flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
+
+    flags |= riscv_env_mmu_index(env, 0);
+    fs = get_field(env->mstatus, MSTATUS_FS);
+    vs = get_field(env->mstatus, MSTATUS_VS);
+
+    if (env->virt_enabled) {
+        flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
+        /*
+         * Merge DISABLED and !DIRTY states using MIN.
+         * We will set both fields when dirtying.
+         */
+        fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
+        vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
+    }
+
+    /* With Zfinx, floating point is enabled/disabled by Smstateen. */
+    if (!riscv_has_ext(env, RVF)) {
+        fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE)
+             ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
+    }
+
+    if (cpu->cfg.debug && !icount_enabled()) {
+        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
+    }
+#endif
+
+    flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
+    flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
+    flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
+    flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
+    if (env->cur_pmmask != 0) {
+        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
+    }
+    if (env->cur_pmbase != 0) {
+        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
+    }
+
+    *pflags = flags;
+}
+
 static const TCGCPUOps riscv_tcg_ops = {
     .initialize = riscv_translate_init,
     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
     .restore_state_to_opc = riscv_restore_state_to_opc,
+    .get_cpu_state = riscv_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = riscv_cpu_tlb_fill,
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index e42728990e..3c16c4852b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -578,7 +578,7 @@ static bool vext_check_slide(DisasContext *s, int vd, int vs2,
 }
 
 /*
- * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
+ * In riscv_get_cpu_state(), set VILL if RVV was not present.
  * So RVV is also be checked in this function.
  */
 static bool vext_check_isa_ill(DisasContext *s)
-- 
2.41.0

[PATCH-for-9.1 20/27] target/rx: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/rx/cpu.h | 11 -----------
 target/rx/cpu.c | 10 ++++++++++
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 996f121bcd..dcda762212 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -149,17 +149,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
 #define RX_CPU_IRQ 0
 #define RX_CPU_FIR 1
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->pc;
-    *cs_base = 0;
-    *flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
-    *flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
-}
-
 static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
 {
     uint32_t psw = 0;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index da673a595d..3b55b09e64 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -58,6 +58,15 @@ static void rx_restore_state_to_opc(CPUState *cs,
     cpu->env.pc = data[0];
 }
 
+static void rx_get_cpu_state(CPURXState *env, vaddr *pc,
+                             uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->pc;
+    *cs_base = 0;
+    *flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
+    *flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
+}
+
 static bool rx_cpu_has_work(CPUState *cs)
 {
     return cs->interrupt_request &
@@ -187,6 +196,7 @@ static const TCGCPUOps rx_tcg_ops = {
     .initialize = rx_translate_init,
     .synchronize_from_tb = rx_cpu_synchronize_from_tb,
     .restore_state_to_opc = rx_restore_state_to_opc,
+    .get_cpu_state = rx_get_cpu_state,
     .tlb_fill = rx_cpu_tlb_fill,
 
 #ifndef CONFIG_USER_ONLY
-- 
2.41.0

[PATCH-for-9.1 21/27] target/s390x: Restrict TCG-specific declarations

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/s390x/s390x-internal.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index 825252d728..559c9f561d 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -398,10 +398,12 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3,
 
 
 /* translate.c */
+#ifdef CONFIG_TCG
 void s390x_translate_init(void);
 void s390x_restore_state_to_opc(CPUState *cs,
                                 const TranslationBlock *tb,
                                 const uint64_t *data);
+#endif /* CONFIG_TCG */
 
 /* sigp.c */
 int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3);
-- 
2.41.0

[PATCH-for-9.1 22/27] target/s390x: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Note, now s390x_get_cpu_state() is restricted to TCG.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/s390x/cpu.h            | 30 ------------------------------
 target/s390x/s390x-internal.h |  2 ++
 target/s390x/cpu.c            |  1 +
 target/s390x/tcg/mem_helper.c |  2 +-
 target/s390x/tcg/translate.c  | 23 +++++++++++++++++++++++
 5 files changed, 27 insertions(+), 31 deletions(-)

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 2e184aabf5..c84ab43928 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -412,36 +412,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch)
 #endif
 }
 
-#ifdef CONFIG_TCG
-
-#include "tcg/tcg_s390x.h"
-
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    if (env->psw.addr & 1) {
-        /*
-         * Instructions must be at even addresses.
-         * This needs to be checked before address translation.
-         */
-        env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */
-        tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
-    }
-    *pc = env->psw.addr;
-    *cs_base = env->ex_value;
-    *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
-    if (env->cregs[0] & CR0_AFP) {
-        *flags |= FLAG_MASK_AFP;
-    }
-    if (env->cregs[0] & CR0_VECTOR) {
-        *flags |= FLAG_MASK_VECTOR;
-    }
-}
-
-#endif /* CONFIG_TCG */
-
 /* PER bits from control register 9 */
 #define PER_CR9_EVENT_BRANCH           0x80000000
 #define PER_CR9_EVENT_IFETCH           0x40000000
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index 559c9f561d..f9796c2742 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -403,6 +403,8 @@ void s390x_translate_init(void);
 void s390x_restore_state_to_opc(CPUState *cs,
                                 const TranslationBlock *tb,
                                 const uint64_t *data);
+void s390x_get_cpu_state(CPUS390XState *env, vaddr *pc,
+                         uint64_t *cs_base, uint32_t *flags);
 #endif /* CONFIG_TCG */
 
 /* sigp.c */
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index f7194534ae..afade52b76 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -327,6 +327,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
 static const TCGCPUOps s390_tcg_ops = {
     .initialize = s390x_translate_init,
     .restore_state_to_opc = s390x_restore_state_to_opc,
+    .get_cpu_state = s390x_get_cpu_state,
 
 #ifdef CONFIG_USER_ONLY
     .record_sigsegv = s390_cpu_record_sigsegv,
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 557831def4..e1d0133439 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -2391,7 +2391,7 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t r1, uint64_t addr)
    it does not change the program counter.
 
    Perform this by recording the modified instruction in env->ex_value.
-   This will be noticed by cpu_get_tb_cpu_state and thus tb translation.
+   This will be noticed by s390x_get_cpu_state and thus tb translation.
 */
 void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr)
 {
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 0d0c672c95..bf8d00ecef 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -44,6 +44,7 @@
 #include "exec/translator.h"
 #include "exec/log.h"
 #include "qemu/atomic128.h"
+#include "tcg_s390x.h"
 
 #define HELPER_H "helper.h"
 #include "exec/helper-info.c.inc"
@@ -6569,3 +6570,25 @@ void s390x_restore_state_to_opc(CPUState *cs,
     /* Record ILEN.  */
     env->int_pgm_ilen = data[2];
 }
+
+void s390x_get_cpu_state(CPUS390XState *env, vaddr *pc,
+                         uint64_t *cs_base, uint32_t *flags)
+{
+    if (env->psw.addr & 1) {
+        /*
+         * Instructions must be at even addresses.
+         * This needs to be checked before address translation.
+         */
+        env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */
+        tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
+    }
+    *pc = env->psw.addr;
+    *cs_base = env->ex_value;
+    *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+    if (env->cregs[0] & CR0_AFP) {
+        *flags |= FLAG_MASK_AFP;
+    }
+    if (env->cregs[0] & CR0_VECTOR) {
+        *flags |= FLAG_MASK_VECTOR;
+    }
+}
-- 
2.41.0

[PATCH-for-9.1 23/27] target/sh4: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sh4/cpu.h | 15 ---------------
 target/sh4/cpu.c | 16 ++++++++++++++++
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 9211da6bde..36aff035cf 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -370,19 +370,4 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
     env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
 }
 
-static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->pc;
-    /* For a gUSA region, notice the end of the region.  */
-    *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
-    *flags = env->flags
-            | (env->fpscr & TB_FLAG_FPSCR_MASK)
-            | (env->sr & TB_FLAG_SR_MASK)
-            | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
-#ifdef CONFIG_USER_ONLY
-    *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#endif
-}
-
 #endif /* SH4_CPU_H */
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 4f5a4a3d98..9b2b377e29 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -67,6 +67,21 @@ static void superh_restore_state_to_opc(CPUState *cs,
      */
 }
 
+static void sh4_get_cpu_state(CPUSH4State *env, vaddr *pc,
+                              uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->pc;
+    /* For a gUSA region, notice the end of the region.  */
+    *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
+    *flags = env->flags
+             | (env->fpscr & TB_FLAG_FPSCR_MASK)
+             | (env->sr & TB_FLAG_SR_MASK)
+             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
+#ifdef CONFIG_USER_ONLY
+    *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
+}
+
 #ifndef CONFIG_USER_ONLY
 static bool superh_io_recompile_replay_branch(CPUState *cs,
                                               const TranslationBlock *tb)
@@ -250,6 +265,7 @@ static const TCGCPUOps superh_tcg_ops = {
     .initialize = sh4_translate_init,
     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
     .restore_state_to_opc = superh_restore_state_to_opc,
+    .get_cpu_state = sh4_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = superh_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 24/27] target/sparc: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sparc/cpu.h       | 37 ++-----------------------------------
 target/sparc/cpu.c       |  1 +
 target/sparc/translate.c | 33 +++++++++++++++++++++++++++++++++
 3 files changed, 36 insertions(+), 35 deletions(-)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index ae55cd15a4..283c235222 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -614,6 +614,8 @@ void sparc_tcg_init(void);
 void sparc_restore_state_to_opc(CPUState *cs,
                                 const TranslationBlock *tb,
                                 const uint64_t *data);
+void sparc_get_cpu_state(CPUSPARCState *env, vaddr *pc,
+                         uint64_t *cs_base, uint32_t *pflags);
 
 /* fop_helper.c */
 target_ulong cpu_get_fsr(CPUSPARCState *);
@@ -747,41 +749,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
 #define TB_FLAG_HYPER        (1 << 7)
 #define TB_FLAG_ASI_SHIFT    24
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *pflags)
-{
-    uint32_t flags;
-    *pc = env->pc;
-    *cs_base = env->npc;
-    flags = cpu_mmu_index(env_cpu(env), false);
-#ifndef CONFIG_USER_ONLY
-    if (cpu_supervisor_mode(env)) {
-        flags |= TB_FLAG_SUPER;
-    }
-#endif
-#ifdef TARGET_SPARC64
-#ifndef CONFIG_USER_ONLY
-    if (cpu_hypervisor_mode(env)) {
-        flags |= TB_FLAG_HYPER;
-    }
-#endif
-    if (env->pstate & PS_AM) {
-        flags |= TB_FLAG_AM_ENABLED;
-    }
-    if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
-        flags |= TB_FLAG_FPU_ENABLED;
-    }
-    flags |= env->asi << TB_FLAG_ASI_SHIFT;
-#else
-    if (env->psref) {
-        flags |= TB_FLAG_FPU_ENABLED;
-    }
-#endif
-    *pflags = flags;
-}
-
 static inline bool tb_fpu_enabled(int tb_flags)
 {
 #if defined(CONFIG_USER_ONLY)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index dc9ead21fc..b74a3f00b7 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -899,6 +899,7 @@ static const TCGCPUOps sparc_tcg_ops = {
     .initialize = sparc_tcg_init,
     .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
     .restore_state_to_opc = sparc_restore_state_to_opc,
+    .get_cpu_state = sparc_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = sparc_cpu_tlb_fill,
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 319934d9bd..49958837b8 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5122,3 +5122,36 @@ void sparc_restore_state_to_opc(CPUState *cs,
         env->npc = npc;
     }
 }
+
+void sparc_get_cpu_state(CPUSPARCState *env, vaddr *pc,
+                         uint64_t *cs_base, uint32_t *pflags)
+{
+    uint32_t flags;
+    *pc = env->pc;
+    *cs_base = env->npc;
+    flags = cpu_mmu_index(env_cpu(env), false);
+#ifndef CONFIG_USER_ONLY
+    if (cpu_supervisor_mode(env)) {
+        flags |= TB_FLAG_SUPER;
+    }
+#endif
+#ifdef TARGET_SPARC64
+#ifndef CONFIG_USER_ONLY
+    if (cpu_hypervisor_mode(env)) {
+        flags |= TB_FLAG_HYPER;
+    }
+#endif
+    if (env->pstate & PS_AM) {
+        flags |= TB_FLAG_AM_ENABLED;
+    }
+    if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
+        flags |= TB_FLAG_FPU_ENABLED;
+    }
+    flags |= env->asi << TB_FLAG_ASI_SHIFT;
+#else
+    if (env->psref) {
+        flags |= TB_FLAG_FPU_ENABLED;
+    }
+#endif
+    *pflags = flags;
+}
-- 
2.41.0

[PATCH-for-9.1 25/27] target/tricore: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/tricore/cpu.h | 12 ------------
 target/tricore/cpu.c | 13 +++++++++++++
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 220af69fc2..9537fef2b9 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -253,18 +253,6 @@ FIELD(TB_FLAGS, PRIV, 0, 2)
 void cpu_state_reset(CPUTriCoreState *s);
 void tricore_tcg_init(void);
 
-static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    uint32_t new_flags = 0;
-    *pc = env->PC;
-    *cs_base = 0;
-
-    new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
-            extract32(env->PSW, 10, 2));
-    *flags = new_flags;
-}
-
 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
 
 /* helpers.c */
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index a9af73aeb5..d6ac07a488 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -58,6 +58,18 @@ static void tricore_restore_state_to_opc(CPUState *cs,
     cpu_env(cs)->PC = data[0];
 }
 
+static void tricore_get_cpu_state(CPUTriCoreState *env, vaddr *pc,
+                                  uint64_t *cs_base, uint32_t *flags)
+{
+    uint32_t new_flags = 0;
+    *pc = env->PC;
+    *cs_base = 0;
+
+    new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
+                            extract32(env->PSW, 10, 2));
+    *flags = new_flags;
+}
+
 static void tricore_cpu_reset_hold(Object *obj)
 {
     CPUState *cs = CPU(obj);
@@ -168,6 +180,7 @@ static const TCGCPUOps tricore_tcg_ops = {
     .initialize = tricore_tcg_init,
     .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
     .restore_state_to_opc = tricore_restore_state_to_opc,
+    .get_cpu_state = tricore_get_cpu_state,
     .tlb_fill = tricore_cpu_tlb_fill,
 };
 
-- 
2.41.0

[PATCH-for-9.1 26/27] target/xtensa: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/xtensa/cpu.h | 70 ---------------------------------------------
 target/xtensa/cpu.c | 69 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+), 70 deletions(-)

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3826b779e4..2b6f2bdea7 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -734,76 +734,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
 
 #include "exec/cpu-all.h"
 
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
-                                        uint64_t *cs_base, uint32_t *flags)
-{
-    *pc = env->pc;
-    *cs_base = 0;
-    *flags = 0;
-    *flags |= xtensa_get_ring(env);
-    if (env->sregs[PS] & PS_EXCM) {
-        *flags |= XTENSA_TBFLAG_EXCM;
-    } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
-        target_ulong lend_dist =
-            env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
-
-        /*
-         * 0 in the csbase_lend field means that there may not be a loopback
-         * for any instruction that starts inside this page. Any other value
-         * means that an instruction that ends at this offset from the page
-         * start may loop back and will need loopback code to be generated.
-         *
-         * lend_dist is 0 when LEND points to the start of the page, but
-         * no instruction that starts inside this page may end at offset 0,
-         * so it's still correct.
-         *
-         * When an instruction ends at a page boundary it may only start in
-         * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
-         * for the TB that contains this instruction.
-         */
-        if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
-            target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
-
-            *cs_base = lend_dist;
-            if (lbeg_off < 256) {
-                *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
-            }
-        }
-    }
-    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
-            (env->sregs[LITBASE] & 1)) {
-        *flags |= XTENSA_TBFLAG_LITBASE;
-    }
-    if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
-        if (xtensa_get_cintlevel(env) < env->config->debug_level) {
-            *flags |= XTENSA_TBFLAG_DEBUG;
-        }
-        if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
-            *flags |= XTENSA_TBFLAG_ICOUNT;
-        }
-    }
-    if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
-        *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
-    }
-    if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
-        (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
-        uint32_t windowstart = xtensa_replicate_windowstart(env) >>
-            (env->sregs[WINDOW_BASE] + 1);
-        uint32_t w = ctz32(windowstart | 0x8);
-
-        *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
-        *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
-                            PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
-    } else {
-        *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
-    }
-    if (env->yield_needed) {
-        *flags |= XTENSA_TBFLAG_YIELD;
-    }
-}
-
 XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
                                         Clock *cpu_refclk);
 
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 875cf843c9..35c66432a1 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -63,6 +63,74 @@ static void xtensa_restore_state_to_opc(CPUState *cs,
     cpu->env.pc = data[0];
 }
 
+static void xtensa_get_cpu_state(CPUXtensaState *env, vaddr *pc,
+                                 uint64_t *cs_base, uint32_t *flags)
+{
+    *pc = env->pc;
+    *cs_base = 0;
+    *flags = 0;
+    *flags |= xtensa_get_ring(env);
+    if (env->sregs[PS] & PS_EXCM) {
+        *flags |= XTENSA_TBFLAG_EXCM;
+    } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
+        target_ulong lend_dist =
+            env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
+
+        /*
+         * 0 in the csbase_lend field means that there may not be a loopback
+         * for any instruction that starts inside this page. Any other value
+         * means that an instruction that ends at this offset from the page
+         * start may loop back and will need loopback code to be generated.
+         *
+         * lend_dist is 0 when LEND points to the start of the page, but
+         * no instruction that starts inside this page may end at offset 0,
+         * so it's still correct.
+         *
+         * When an instruction ends at a page boundary it may only start in
+         * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
+         * for the TB that contains this instruction.
+         */
+        if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
+            target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
+
+            *cs_base = lend_dist;
+            if (lbeg_off < 256) {
+                *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
+            }
+        }
+    }
+    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
+            (env->sregs[LITBASE] & 1)) {
+        *flags |= XTENSA_TBFLAG_LITBASE;
+    }
+    if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
+        if (xtensa_get_cintlevel(env) < env->config->debug_level) {
+            *flags |= XTENSA_TBFLAG_DEBUG;
+        }
+        if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
+            *flags |= XTENSA_TBFLAG_ICOUNT;
+        }
+    }
+    if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
+        *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
+    }
+    if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
+        (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
+        uint32_t windowstart = xtensa_replicate_windowstart(env) >>
+            (env->sregs[WINDOW_BASE] + 1);
+        uint32_t w = ctz32(windowstart | 0x8);
+
+        *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
+        *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
+                            PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
+    } else {
+        *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
+    }
+    if (env->yield_needed) {
+        *flags |= XTENSA_TBFLAG_YIELD;
+    }
+}
+
 static bool xtensa_cpu_has_work(CPUState *cs)
 {
 #ifndef CONFIG_USER_ONLY
@@ -230,6 +298,7 @@ static const TCGCPUOps xtensa_tcg_ops = {
     .initialize = xtensa_translate_init,
     .debug_excp_handler = xtensa_breakpoint_handler,
     .restore_state_to_opc = xtensa_restore_state_to_opc,
+    .get_cpu_state = xtensa_get_cpu_state,
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = xtensa_cpu_tlb_fill,
-- 
2.41.0

[PATCH-for-9.1 27/27] accel/tcg: Remove check on TARGET_HAS_CPU_GET_TB_CPU_STATE

[Philippe Mathieu-Daudé]

All targets have been converted to TCGCPUOps::get_cpu_state(),
there is no more use of TARGET_HAS_CPU_GET_TB_CPU_STATE in the
tree. Remove the check on TARGET_HAS_CPU_GET_TB_CPU_STATE, but
add an assertion in tcg_exec_realizefn() so new target won't
miss to implement this handler.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 accel/tcg/cpu-exec.c      | 1 +
 accel/tcg/translate-all.c | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 987e6164f7..6167bd3159 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -1072,6 +1072,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp)
         const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
 
         assert(tcg_ops->restore_state_to_opc);
+        assert(tcg_ops->get_cpu_state);
         tcg_ops->initialize();
         tcg_target_initialized = true;
     }
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 7b538d2b9c..3c9fafba69 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -221,7 +221,6 @@ void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
     cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data);
 }
 
-#ifndef TARGET_HAS_CPU_GET_TB_CPU_STATE
 void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc,
                           uint64_t *cs_base, uint32_t *flags)
 {
@@ -229,7 +228,6 @@ void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc,
 
     cpu->cc->tcg_ops->get_cpu_state(env, pc, cs_base, flags);
 }
-#endif
 
 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc)
 {
-- 
2.41.0

Re: [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler

[Philippe Mathieu-Daudé]

(Forgot to Cc Claudio to keep him updated)

On 19/3/24 16:42, Philippe Mathieu-Daudé wrote:
> Hi,
> 
> This series introduce a generic get_cpu_state() handler in
> TCGCPUOps and convert each target to it.
> 
> This is required to get a single cpu_get_tb_cpu_state()
> for heterogeneous emulation (since this method is called
> by accel/tcg/).
> 
> Regards,
> 
> Phil.
> 
> Philippe Mathieu-Daudé (27):
>    accel/tcg: Ensure frontends define restore_state_to_opc handler
>    accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler
>    target/alpha: Convert to TCGCPUOps::get_cpu_state()
>    target/arm: Restrict TCG-specific declarations
>    target/arm: Convert to TCGCPUOps::get_cpu_state()
>    target/avr: Convert to TCGCPUOps::get_cpu_state()
>    target/cris: Convert to TCGCPUOps::get_cpu_state()
>    target/hexagon: Convert to TCGCPUOps::get_cpu_state()
>    target/hppa: Convert to TCGCPUOps::get_cpu_state()
>    target/i386: Convert to TCGCPUOps::get_cpu_state()
>    target/loongarch: Convert to TCGCPUOps::get_cpu_state()
>    target/m68k: Convert to TCGCPUOps::get_cpu_state()
>    target/microblaze: Convert to TCGCPUOps::get_cpu_state()
>    target/mips: Convert to TCGCPUOps::get_cpu_state()
>    target/nios2: Convert to TCGCPUOps::get_cpu_state()
>    target/openrisc: Convert to TCGCPUOps::get_cpu_state()
>    target/ppc: Indent ppc_tcg_ops[] with 4 spaces
>    target/ppc: Convert to TCGCPUOps::get_cpu_state()
>    target/riscv: Convert to TCGCPUOps::get_cpu_state()
>    target/rx: Convert to TCGCPUOps::get_cpu_state()
>    target/s390x: Restrict TCG-specific declarations
>    target/s390x: Convert to TCGCPUOps::get_cpu_state()
>    target/sh4: Convert to TCGCPUOps::get_cpu_state()
>    target/sparc: Convert to TCGCPUOps::get_cpu_state()
>    target/tricore: Convert to TCGCPUOps::get_cpu_state()
>    target/xtensa: Convert to TCGCPUOps::get_cpu_state()
>    accel/tcg: Remove check on TARGET_HAS_CPU_GET_TB_CPU_STATE

Re: [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler

[Claudio Fontana]

Thanks Philippe, I fear I am unable to really be uptodate,
but it's great to see all the cleanup you and others have done!

Ciao,

Claudio

On 3/19/24 16:48, Philippe Mathieu-Daudé wrote:
> (Forgot to Cc Claudio to keep him updated)
> 
> On 19/3/24 16:42, Philippe Mathieu-Daudé wrote:
>> Hi,
>>
>> This series introduce a generic get_cpu_state() handler in
>> TCGCPUOps and convert each target to it.
>>
>> This is required to get a single cpu_get_tb_cpu_state()
>> for heterogeneous emulation (since this method is called
>> by accel/tcg/).
>>
>> Regards,
>>
>> Phil.
>>
>> Philippe Mathieu-Daudé (27):
>>    accel/tcg: Ensure frontends define restore_state_to_opc handler
>>    accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler
>>    target/alpha: Convert to TCGCPUOps::get_cpu_state()
>>    target/arm: Restrict TCG-specific declarations
>>    target/arm: Convert to TCGCPUOps::get_cpu_state()
>>    target/avr: Convert to TCGCPUOps::get_cpu_state()
>>    target/cris: Convert to TCGCPUOps::get_cpu_state()
>>    target/hexagon: Convert to TCGCPUOps::get_cpu_state()
>>    target/hppa: Convert to TCGCPUOps::get_cpu_state()
>>    target/i386: Convert to TCGCPUOps::get_cpu_state()
>>    target/loongarch: Convert to TCGCPUOps::get_cpu_state()
>>    target/m68k: Convert to TCGCPUOps::get_cpu_state()
>>    target/microblaze: Convert to TCGCPUOps::get_cpu_state()
>>    target/mips: Convert to TCGCPUOps::get_cpu_state()
>>    target/nios2: Convert to TCGCPUOps::get_cpu_state()
>>    target/openrisc: Convert to TCGCPUOps::get_cpu_state()
>>    target/ppc: Indent ppc_tcg_ops[] with 4 spaces
>>    target/ppc: Convert to TCGCPUOps::get_cpu_state()
>>    target/riscv: Convert to TCGCPUOps::get_cpu_state()
>>    target/rx: Convert to TCGCPUOps::get_cpu_state()
>>    target/s390x: Restrict TCG-specific declarations
>>    target/s390x: Convert to TCGCPUOps::get_cpu_state()
>>    target/sh4: Convert to TCGCPUOps::get_cpu_state()
>>    target/sparc: Convert to TCGCPUOps::get_cpu_state()
>>    target/tricore: Convert to TCGCPUOps::get_cpu_state()
>>    target/xtensa: Convert to TCGCPUOps::get_cpu_state()
>>    accel/tcg: Remove check on TARGET_HAS_CPU_GET_TB_CPU_STATE
> 

Re: [PATCH-for-9.1 10/27] target/i386: Convert to TCGCPUOps::get_cpu_state()

[Richard Henderson]

On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
> +static inline void x86_get_cpu_state(CPUX86State *env, vaddr *pc,

Remove inline.


r~

Re: [PATCH-for-9.1 22/27] target/s390x: Convert to TCGCPUOps::get_cpu_state()

[Richard Henderson]

On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
> 
> Note, now s390x_get_cpu_state() is restricted to TCG.
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   target/s390x/cpu.h            | 30 ------------------------------
>   target/s390x/s390x-internal.h |  2 ++
>   target/s390x/cpu.c            |  1 +
>   target/s390x/tcg/mem_helper.c |  2 +-
>   target/s390x/tcg/translate.c  | 23 +++++++++++++++++++++++
>   5 files changed, 27 insertions(+), 31 deletions(-)

Why is the function in translate.c, not cpu.c (with or without ifdefs)?


r~

Re: [PATCH-for-9.1 24/27] target/sparc: Convert to TCGCPUOps::get_cpu_state()

[Richard Henderson]

On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   target/sparc/cpu.h       | 37 ++-----------------------------------
>   target/sparc/cpu.c       |  1 +
>   target/sparc/translate.c | 33 +++++++++++++++++++++++++++++++++
>   3 files changed, 36 insertions(+), 35 deletions(-)

Again, why translate.c?

r~

Re: [PATCH-for-9.1 00/27] accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler

[Richard Henderson]

On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (27):
>    accel/tcg: Ensure frontends define restore_state_to_opc handler
>    accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler
>    target/alpha: Convert to TCGCPUOps::get_cpu_state()
>    target/arm: Restrict TCG-specific declarations
>    target/arm: Convert to TCGCPUOps::get_cpu_state()
>    target/avr: Convert to TCGCPUOps::get_cpu_state()
>    target/cris: Convert to TCGCPUOps::get_cpu_state()
>    target/hexagon: Convert to TCGCPUOps::get_cpu_state()
>    target/hppa: Convert to TCGCPUOps::get_cpu_state()
>    target/i386: Convert to TCGCPUOps::get_cpu_state()
>    target/loongarch: Convert to TCGCPUOps::get_cpu_state()
>    target/m68k: Convert to TCGCPUOps::get_cpu_state()
>    target/microblaze: Convert to TCGCPUOps::get_cpu_state()
>    target/mips: Convert to TCGCPUOps::get_cpu_state()
>    target/nios2: Convert to TCGCPUOps::get_cpu_state()
>    target/openrisc: Convert to TCGCPUOps::get_cpu_state()
>    target/ppc: Indent ppc_tcg_ops[] with 4 spaces
>    target/ppc: Convert to TCGCPUOps::get_cpu_state()
>    target/riscv: Convert to TCGCPUOps::get_cpu_state()
>    target/rx: Convert to TCGCPUOps::get_cpu_state()
>    target/s390x: Restrict TCG-specific declarations
>    target/s390x: Convert to TCGCPUOps::get_cpu_state()
>    target/sh4: Convert to TCGCPUOps::get_cpu_state()
>    target/sparc: Convert to TCGCPUOps::get_cpu_state()
>    target/tricore: Convert to TCGCPUOps::get_cpu_state()
>    target/xtensa: Convert to TCGCPUOps::get_cpu_state()
>    accel/tcg: Remove check on TARGET_HAS_CPU_GET_TB_CPU_STATE

Modulo 3 notes,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH-for-9.1 19/27] target/riscv: Convert to TCGCPUOps::get_cpu_state()

[Daniel Henrique Barboza]

On 3/19/24 12:42, Philippe Mathieu-Daudé wrote:
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
> 
> Note, now riscv_get_cpu_state() is restricted to TCG, and
> is declared with static scope.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>


>   target/riscv/cpu.h                      |  3 -
>   target/riscv/cpu.c                      |  2 +-
>   target/riscv/cpu_helper.c               | 87 ------------------------
>   target/riscv/tcg/tcg-cpu.c              | 88 +++++++++++++++++++++++++
>   target/riscv/insn_trans/trans_rvv.c.inc |  2 +-
>   5 files changed, 90 insertions(+), 92 deletions(-)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3b1a02b944..d00d1be235 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -704,9 +704,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew,
>       return vlen >> (vsew + 3 - lmul);
>   }
>   
> -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> -                          uint64_t *cs_base, uint32_t *pflags);
> -
>   void riscv_cpu_update_mask(CPURISCVState *env);
>   bool riscv_cpu_is_32bit(RISCVCPU *cpu);
>   
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c160b9216b..ca537d0e0a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -889,7 +889,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
>       RISCVCPU *cpu = RISCV_CPU(cs);
>       CPURISCVState *env = &cpu->env;
>   
> -    /* Match cpu_get_tb_cpu_state. */
> +    /* Match riscv_get_cpu_state. */
>       if (env->xl == MXL_RV32) {
>           return env->pc & UINT32_MAX;
>       }
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index ce7322011d..e18a269358 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -25,7 +25,6 @@
>   #include "pmu.h"
>   #include "exec/exec-all.h"
>   #include "instmap.h"
> -#include "tcg/tcg-op.h"
>   #include "trace.h"
>   #include "semihosting/common-semi.h"
>   #include "sysemu/cpu-timers.h"
> @@ -62,92 +61,6 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
>   #endif
>   }
>   
> -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> -                          uint64_t *cs_base, uint32_t *pflags)
> -{
> -    RISCVCPU *cpu = env_archcpu(env);
> -    RISCVExtStatus fs, vs;
> -    uint32_t flags = 0;
> -
> -    *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
> -    *cs_base = 0;
> -
> -    if (cpu->cfg.ext_zve32f) {
> -        /*
> -         * If env->vl equals to VLMAX, we can use generic vector operation
> -         * expanders (GVEC) to accerlate the vector operations.
> -         * However, as LMUL could be a fractional number. The maximum
> -         * vector size can be operated might be less than 8 bytes,
> -         * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
> -         * only when maxsz >= 8 bytes.
> -         */
> -
> -        /* lmul encoded as in DisasContext::lmul */
> -        int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
> -        uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
> -        uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
> -        uint32_t maxsz = vlmax << vsew;
> -        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
> -                           (maxsz >= 8);
> -        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
> -        flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew);
> -        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
> -                           FIELD_EX64(env->vtype, VTYPE, VLMUL));
> -        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
> -        flags = FIELD_DP32(flags, TB_FLAGS, VTA,
> -                           FIELD_EX64(env->vtype, VTYPE, VTA));
> -        flags = FIELD_DP32(flags, TB_FLAGS, VMA,
> -                           FIELD_EX64(env->vtype, VTYPE, VMA));
> -        flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
> -    } else {
> -        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
> -    }
> -
> -#ifdef CONFIG_USER_ONLY
> -    fs = EXT_STATUS_DIRTY;
> -    vs = EXT_STATUS_DIRTY;
> -#else
> -    flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
> -
> -    flags |= riscv_env_mmu_index(env, 0);
> -    fs = get_field(env->mstatus, MSTATUS_FS);
> -    vs = get_field(env->mstatus, MSTATUS_VS);
> -
> -    if (env->virt_enabled) {
> -        flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
> -        /*
> -         * Merge DISABLED and !DIRTY states using MIN.
> -         * We will set both fields when dirtying.
> -         */
> -        fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
> -        vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
> -    }
> -
> -    /* With Zfinx, floating point is enabled/disabled by Smstateen. */
> -    if (!riscv_has_ext(env, RVF)) {
> -        fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE)
> -             ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
> -    }
> -
> -    if (cpu->cfg.debug && !icount_enabled()) {
> -        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
> -    }
> -#endif
> -
> -    flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
> -    flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
> -    flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
> -    flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
> -    if (env->cur_pmmask != 0) {
> -        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
> -    }
> -    if (env->cur_pmbase != 0) {
> -        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
> -    }
> -
> -    *pflags = flags;
> -}
> -
>   void riscv_cpu_update_mask(CPURISCVState *env)
>   {
>       target_ulong mask = 0, base = 0;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index ab6db817db..934007673e 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -31,6 +31,7 @@
>   #include "hw/core/accel-cpu.h"
>   #include "hw/core/tcg-cpu-ops.h"
>   #include "tcg/tcg.h"
> +#include "sysemu/cpu-timers.h"
>   
>   /* Hash that stores user set extensions */
>   static GHashTable *multi_ext_user_opts;
> @@ -129,10 +130,97 @@ static void riscv_restore_state_to_opc(CPUState *cs,
>       env->bins = data[1];
>   }
>   
> +static void riscv_get_cpu_state(CPURISCVState *env, vaddr *pc,
> +                                uint64_t *cs_base, uint32_t *pflags)
> +{
> +    RISCVCPU *cpu = env_archcpu(env);
> +    RISCVExtStatus fs, vs;
> +    uint32_t flags = 0;
> +
> +    *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
> +    *cs_base = 0;
> +
> +    if (cpu->cfg.ext_zve32f) {
> +        /*
> +         * If env->vl equals to VLMAX, we can use generic vector operation
> +         * expanders (GVEC) to accerlate the vector operations.
> +         * However, as LMUL could be a fractional number. The maximum
> +         * vector size can be operated might be less than 8 bytes,
> +         * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
> +         * only when maxsz >= 8 bytes.
> +         */
> +
> +        /* lmul encoded as in DisasContext::lmul */
> +        int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);
> +        uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);
> +        uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
> +        uint32_t maxsz = vlmax << vsew;
> +        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
> +                           (maxsz >= 8);
> +        flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
> +        flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew);
> +        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
> +                           FIELD_EX64(env->vtype, VTYPE, VLMUL));
> +        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
> +        flags = FIELD_DP32(flags, TB_FLAGS, VTA,
> +                           FIELD_EX64(env->vtype, VTYPE, VTA));
> +        flags = FIELD_DP32(flags, TB_FLAGS, VMA,
> +                           FIELD_EX64(env->vtype, VTYPE, VMA));
> +        flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);
> +    } else {
> +        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
> +    }
> +
> +#ifdef CONFIG_USER_ONLY
> +    fs = EXT_STATUS_DIRTY;
> +    vs = EXT_STATUS_DIRTY;
> +#else
> +    flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
> +
> +    flags |= riscv_env_mmu_index(env, 0);
> +    fs = get_field(env->mstatus, MSTATUS_FS);
> +    vs = get_field(env->mstatus, MSTATUS_VS);
> +
> +    if (env->virt_enabled) {
> +        flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
> +        /*
> +         * Merge DISABLED and !DIRTY states using MIN.
> +         * We will set both fields when dirtying.
> +         */
> +        fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
> +        vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
> +    }
> +
> +    /* With Zfinx, floating point is enabled/disabled by Smstateen. */
> +    if (!riscv_has_ext(env, RVF)) {
> +        fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE)
> +             ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
> +    }
> +
> +    if (cpu->cfg.debug && !icount_enabled()) {
> +        flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
> +    }
> +#endif
> +
> +    flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
> +    flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
> +    flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
> +    flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
> +    if (env->cur_pmmask != 0) {
> +        flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
> +    }
> +    if (env->cur_pmbase != 0) {
> +        flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
> +    }
> +
> +    *pflags = flags;
> +}
> +
>   static const TCGCPUOps riscv_tcg_ops = {
>       .initialize = riscv_translate_init,
>       .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
>       .restore_state_to_opc = riscv_restore_state_to_opc,
> +    .get_cpu_state = riscv_get_cpu_state,
>   
>   #ifndef CONFIG_USER_ONLY
>       .tlb_fill = riscv_cpu_tlb_fill,
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index e42728990e..3c16c4852b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -578,7 +578,7 @@ static bool vext_check_slide(DisasContext *s, int vd, int vs2,
>   }
>   
>   /*
> - * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
> + * In riscv_get_cpu_state(), set VILL if RVV was not present.
>    * So RVV is also be checked in this function.
>    */
>   static bool vext_check_isa_ill(DisasContext *s)

Re: [PATCH-for-9.1 17/27] target/ppc: Indent ppc_tcg_ops[] with 4 spaces

[Nicholas Piggin]

Acked-by: Nicholas Piggin <npiggin@gmail.com>

On Wed Mar 20, 2024 at 1:42 AM AEST, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu_init.c | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 7e65f08147..464e91faa2 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -7360,22 +7360,22 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
>  #include "hw/core/tcg-cpu-ops.h"
>  
>  static const TCGCPUOps ppc_tcg_ops = {
> -  .initialize = ppc_translate_init,
> -  .restore_state_to_opc = ppc_restore_state_to_opc,
> +    .initialize = ppc_translate_init,
> +    .restore_state_to_opc = ppc_restore_state_to_opc,
>  
>  #ifdef CONFIG_USER_ONLY
> -  .record_sigsegv = ppc_cpu_record_sigsegv,
> +    .record_sigsegv = ppc_cpu_record_sigsegv,
>  #else
> -  .tlb_fill = ppc_cpu_tlb_fill,
> -  .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> -  .do_interrupt = ppc_cpu_do_interrupt,
> -  .cpu_exec_enter = ppc_cpu_exec_enter,
> -  .cpu_exec_exit = ppc_cpu_exec_exit,
> -  .do_unaligned_access = ppc_cpu_do_unaligned_access,
> -  .do_transaction_failed = ppc_cpu_do_transaction_failed,
> -  .debug_excp_handler = ppc_cpu_debug_excp_handler,
> -  .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
> -  .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
> +    .tlb_fill = ppc_cpu_tlb_fill,
> +    .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> +    .do_interrupt = ppc_cpu_do_interrupt,
> +    .cpu_exec_enter = ppc_cpu_exec_enter,
> +    .cpu_exec_exit = ppc_cpu_exec_exit,
> +    .do_unaligned_access = ppc_cpu_do_unaligned_access,
> +    .do_transaction_failed = ppc_cpu_do_transaction_failed,
> +    .debug_excp_handler = ppc_cpu_debug_excp_handler,
> +    .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
> +    .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
>  #endif /* !CONFIG_USER_ONLY */
>  };
>  #endif /* CONFIG_TCG */

Re: [PATCH-for-9.1 18/27] target/ppc: Convert to TCGCPUOps::get_cpu_state()

[Nicholas Piggin]

On Wed Mar 20, 2024 at 1:42 AM AEST, Philippe Mathieu-Daudé wrote:
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state(),
> unifying with the method declared in target/ppc/helper_regs.c.

Looks okay AFAIKS.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>

>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/ppc/cpu.h         | 16 +++-------------
>  target/ppc/cpu_init.c    |  1 +
>  target/ppc/helper_regs.c | 13 +++++++------
>  3 files changed, 11 insertions(+), 19 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index ced4e53024..6aa18db335 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2716,19 +2716,9 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer);
>   */
>  #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
>  
> -#define TARGET_HAS_CPU_GET_TB_CPU_STATE
> -
> -#ifdef CONFIG_DEBUG_TCG
> -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
> -                          uint64_t *cs_base, uint32_t *flags);
> -#else
> -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
> -                                        uint64_t *cs_base, uint32_t *flags)
> -{
> -    *pc = env->nip;
> -    *cs_base = 0;
> -    *flags = env->hflags;
> -}
> +#ifdef CONFIG_TCG
> +void ppc_get_cpu_state(CPUPPCState *env, vaddr *pc,
> +                       uint64_t *cs_base, uint32_t *flags);
>  #endif
>  
>  G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 464e91faa2..673559b444 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -7362,6 +7362,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
>  static const TCGCPUOps ppc_tcg_ops = {
>      .initialize = ppc_translate_init,
>      .restore_state_to_opc = ppc_restore_state_to_opc,
> +    .get_cpu_state = ppc_get_cpu_state,
>  
>  #ifdef CONFIG_USER_ONLY
>      .record_sigsegv = ppc_cpu_record_sigsegv,
> diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
> index 25258986e3..e62591067c 100644
> --- a/target/ppc/helper_regs.c
> +++ b/target/ppc/helper_regs.c
> @@ -217,25 +217,26 @@ void hreg_update_pmu_hflags(CPUPPCState *env)
>      env->hflags |= hreg_compute_pmu_hflags_value(env);
>  }
>  
> -#ifdef CONFIG_DEBUG_TCG
> -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
> -                          uint64_t *cs_base, uint32_t *flags)
> +#ifdef CONFIG_TCG
> +void ppc_get_cpu_state(CPUPPCState *env, vaddr *pc,
> +                       uint64_t *cs_base, uint32_t *flags)
>  {
>      uint32_t hflags_current = env->hflags;
> -    uint32_t hflags_rebuilt;
>  
>      *pc = env->nip;
>      *cs_base = 0;
>      *flags = hflags_current;
>  
> -    hflags_rebuilt = hreg_compute_hflags_value(env);
> +#ifdef CONFIG_DEBUG_TCG
> +    uint32_t hflags_rebuilt = hreg_compute_hflags_value(env);
>      if (unlikely(hflags_current != hflags_rebuilt)) {
>          cpu_abort(env_cpu(env),
>                    "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
>                    hflags_current, hflags_rebuilt);
>      }
> -}
>  #endif
> +}
> +#endif /* CONFIG_TCG */
>  
>  void cpu_interrupt_exittb(CPUState *cs)
>  {

Re: [PATCH-for-9.1 21/27] target/s390x: Restrict TCG-specific declarations

[Thomas Huth]

On 19/03/2024 16.42, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/s390x/s390x-internal.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
> index 825252d728..559c9f561d 100644
> --- a/target/s390x/s390x-internal.h
> +++ b/target/s390x/s390x-internal.h
> @@ -398,10 +398,12 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3,
>   
>   
>   /* translate.c */
> +#ifdef CONFIG_TCG
>   void s390x_translate_init(void);
>   void s390x_restore_state_to_opc(CPUState *cs,
>                                   const TranslationBlock *tb,
>                                   const uint64_t *data);
> +#endif /* CONFIG_TCG */
>   
>   /* sigp.c */
>   int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3);

Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [PATCH-for-9.1 22/27] target/s390x: Convert to TCGCPUOps::get_cpu_state()

[Philippe Mathieu-Daudé]

On 19/3/24 22:05, Richard Henderson wrote:
> On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
>> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
>>
>> Note, now s390x_get_cpu_state() is restricted to TCG.
>>
>> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
>> ---
>>   target/s390x/cpu.h            | 30 ------------------------------
>>   target/s390x/s390x-internal.h |  2 ++
>>   target/s390x/cpu.c            |  1 +
>>   target/s390x/tcg/mem_helper.c |  2 +-
>>   target/s390x/tcg/translate.c  | 23 +++++++++++++++++++++++
>>   5 files changed, 27 insertions(+), 31 deletions(-)
> 
> Why is the function in translate.c, not cpu.c (with or without ifdefs)?

My understanding is target/foo/tcg/ is better for TCG-specific handlers,
less #ifdef'ry and stubs. Then bar_helper.c are meant for TCG helpers
(including "exec/helper-proto.h").

Can you think of a better file (new name?) in tcg/ or do you rather
keep it in the main cpu.c?

Thanks,

Phil.

Re: [PATCH-for-9.1 22/27] target/s390x: Convert to TCGCPUOps::get_cpu_state()

[Richard Henderson]

On 3/19/24 21:09, Philippe Mathieu-Daudé wrote:
> On 19/3/24 22:05, Richard Henderson wrote:
>> On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
>>> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
>>>
>>> Note, now s390x_get_cpu_state() is restricted to TCG.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
>>> ---
>>>   target/s390x/cpu.h            | 30 ------------------------------
>>>   target/s390x/s390x-internal.h |  2 ++
>>>   target/s390x/cpu.c            |  1 +
>>>   target/s390x/tcg/mem_helper.c |  2 +-
>>>   target/s390x/tcg/translate.c  | 23 +++++++++++++++++++++++
>>>   5 files changed, 27 insertions(+), 31 deletions(-)
>>
>> Why is the function in translate.c, not cpu.c (with or without ifdefs)?
> 
> My understanding is target/foo/tcg/ is better for TCG-specific handlers,
> less #ifdef'ry and stubs. Then bar_helper.c are meant for TCG helpers
> (including "exec/helper-proto.h").
> 
> Can you think of a better file (new name?) in tcg/ or do you rather
> keep it in the main cpu.c?

Given that all other targets to this point used cpu.c, I would prefer s390x and sparc to 
not be the only exceptions.


r~

RE: [PATCH-for-9.1 08/27] target/hexagon: Convert to TCGCPUOps::get_cpu_state()

[Brian Cain]

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Sent: Tuesday, March 19, 2024 10:43 AM
> To: qemu-devel@nongnu.org
> Cc: qemu-s390x@nongnu.org; Richard Henderson
> <richard.henderson@linaro.org>; qemu-ppc@nongnu.org; qemu-
> arm@nongnu.org; qemu-riscv@nongnu.org; Anton Johansson <anjo@rev.ng>;
> Philippe Mathieu-Daudé <philmd@linaro.org>; Brian Cain
> <bcain@quicinc.com>
> Subject: [PATCH-for-9.1 08/27] target/hexagon: Convert to
> TCGCPUOps::get_cpu_state()
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
> 
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Brian Cain <bcain@quicinc.com>

> ---
>  target/hexagon/cpu.h | 14 --------------
>  target/hexagon/cpu.c | 13 +++++++++++++
>  2 files changed, 13 insertions(+), 14 deletions(-)
> 
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 935a9c3276..1d42c33827 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -134,20 +134,6 @@ struct ArchCPU {
> 
>  FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
> 
> -#define TARGET_HAS_CPU_GET_TB_CPU_STATE
> -
> -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
> -                                        uint64_t *cs_base, uint32_t *flags)
> -{
> -    uint32_t hex_flags = 0;
> -    *pc = env->gpr[HEX_REG_PC];
> -    *cs_base = 0;
> -    if (*pc == env->gpr[HEX_REG_SA0]) {
> -        hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
> -    }
> -    *flags = hex_flags;
> -}
> -
>  typedef HexagonCPU ArchCPU;
> 
>  void hexagon_translate_init(void);
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index 3a716b9be3..5e0a9441f2 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -273,6 +273,18 @@ static void hexagon_restore_state_to_opc(CPUState
> *cs,
>      cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
>  }
> 
> +static void hexagon_get_cpu_state(CPUHexagonState *env, vaddr *pc,
> +                                  uint64_t *cs_base, uint32_t *flags)
> +{
> +    uint32_t hex_flags = 0;
> +    *pc = env->gpr[HEX_REG_PC];
> +    *cs_base = 0;
> +    if (*pc == env->gpr[HEX_REG_SA0]) {
> +        hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
> +    }
> +    *flags = hex_flags;
> +}
> +
>  static void hexagon_cpu_reset_hold(Object *obj)
>  {
>      CPUState *cs = CPU(obj);
> @@ -327,6 +339,7 @@ static const TCGCPUOps hexagon_tcg_ops = {
>      .initialize = hexagon_translate_init,
>      .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
>      .restore_state_to_opc = hexagon_restore_state_to_opc,
> +    .get_cpu_state = hexagon_get_cpu_state,
>  };
> 
>  static void hexagon_cpu_class_init(ObjectClass *c, void *data)
> --
> 2.41.0

Re: [PATCH-for-9.1 25/27] target/tricore: Convert to TCGCPUOps::get_cpu_state()

[Bastian Koppelmann]

On Tue, Mar 19, 2024 at 04:42:54PM +0100, Philippe Mathieu-Daudé wrote:
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/tricore/cpu.h | 12 ------------
>  target/tricore/cpu.c | 13 +++++++++++++
>  2 files changed, 13 insertions(+), 12 deletions(-)

Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Cheers,
Bastian