* [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC
@ 2017-09-07 19:24 Subbaraya Sundeep
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
` (5 more replies)
0 siblings, 6 replies; 28+ messages in thread
From: Subbaraya Sundeep @ 2017-09-07 19:24 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Hi Qemu-devel,
I am trying to add Smartfusion2 SoC.
SoC is from Microsemi and System on Module(SOM)
board is from Emcraft systems. Smartfusion2 has hardened
Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
At the moment only system timer, sysreg and SPI
controller are modelled.
Testing:
./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial mon:stdio \
-kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw
Binaries u-boot.bin and spi.bin are at:
https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
U-boot is from Emcraft with modified
- SPI driver not to use PDMA.
- ugly hack to pass dtb to kernel in r1.
@
https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
driver added by myself @
https://github.com/Subbaraya-Sundeep/linux.git
v8:
memory_region_init_ram to memory_region_init_rom in soc
%s/emcraft_sf2_init/emcraft_sf2_s2s010_init/g in som
Added mc->ignore_memory_transaction_failures = true in som
as per latest commit.
Code simplifications as suggested by Alistair in sysreg and ssi.
v7:
Removed vmstate_register_ram_global as per latest commit
Moved header files to C which are local to C source files
Removed abort() from msf2-sysreg.c
Added VMStateDescription in mss-timer.c
v6:
Moved some defines from header files to source files
Added properties m3clk, apb0div, apb0div1 properties
to soc.
Added properties apb0divisor, apb1divisor to sysreg
Update system_clock_source in msf2-soc.c
Changed machine name smartfusion2-som->emcraft-sf2
v5
As per Philippe comments:
Added abort in Sysreg if guest tries to remap memory
other than default mapping.
Use of CONFIG_MSF2 in Makefile for soc.c
Fixed incorrect logic in timer model.
Renamed msf2-timer.c -> mss-timer.c
msf2-spi.c -> mss-spi.c also type names
Renamed function msf2_init->emcraft_sf2_init in msf2-som.c
Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
properties to soc.
Pass soc part-name,memory size and clock rate properties from som.
v4:
Fixed build failure by using PRIx macros.
v3:
Added SoC file and board file as per Alistair comments.
v2:
Added SPI controller so that u-boot loads kernel from spi flash.
v1:
Initial patch set with timer and sysreg
Thanks,
Sundeep
Subbaraya Sundeep (5):
msf2: Add Smartfusion2 System timer
msf2: Microsemi Smartfusion2 System Register block
msf2: Add Smartfusion2 SPI controller
msf2: Add Smartfusion2 SoC
msf2: Add Emcraft's Smartfusion2 SOM kit
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs | 1 +
hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++
hw/arm/msf2-som.c | 95 ++++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/msf2-sysreg.c | 195 +++++++++++++++++++
hw/ssi/Makefile.objs | 1 +
hw/ssi/mss-spi.c | 404 ++++++++++++++++++++++++++++++++++++++++
hw/timer/Makefile.objs | 1 +
hw/timer/mss-timer.c | 289 ++++++++++++++++++++++++++++
include/hw/arm/msf2-soc.h | 66 +++++++
include/hw/misc/msf2-sysreg.h | 78 ++++++++
include/hw/ssi/mss-spi.h | 58 ++++++
include/hw/timer/mss-timer.h | 64 +++++++
14 files changed, 1472 insertions(+)
create mode 100644 hw/arm/msf2-soc.c
create mode 100644 hw/arm/msf2-som.c
create mode 100644 hw/misc/msf2-sysreg.c
create mode 100644 hw/ssi/mss-spi.c
create mode 100644 hw/timer/mss-timer.c
create mode 100644 include/hw/arm/msf2-soc.h
create mode 100644 include/hw/misc/msf2-sysreg.h
create mode 100644 include/hw/ssi/mss-spi.h
create mode 100644 include/hw/timer/mss-timer.h
--
2.5.0
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Qemu-devel] [Qemu devel v8 PATCH 1/5] msf2: Add Smartfusion2 System timer
2017-09-07 19:24 [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
@ 2017-09-07 19:24 ` Subbaraya Sundeep
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
` (4 subsequent siblings)
5 siblings, 0 replies; 28+ messages in thread
From: Subbaraya Sundeep @ 2017-09-07 19:24 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Modelled System Timer in Microsemi's Smartfusion2 Soc.
Timer has two 32bit down counters and two interrupts.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/timer/Makefile.objs | 1 +
hw/timer/mss-timer.c | 289 +++++++++++++++++++++++++++++++++++++++++++
include/hw/timer/mss-timer.h | 64 ++++++++++
3 files changed, 354 insertions(+)
create mode 100644 hw/timer/mss-timer.c
create mode 100644 include/hw/timer/mss-timer.h
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 15cce1c..8c19eac 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -42,3 +42,4 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
+common-obj-$(CONFIG_MSF2) += mss-timer.o
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
new file mode 100644
index 0000000..60f1213
--- /dev/null
+++ b/hw/timer/mss-timer.c
@@ -0,0 +1,289 @@
+/*
+ * Block model of System timer present in
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "qemu/log.h"
+#include "hw/timer/mss-timer.h"
+
+#ifndef MSS_TIMER_ERR_DEBUG
+#define MSS_TIMER_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSS_TIMER_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+#define R_TIM_VAL 0
+#define R_TIM_LOADVAL 1
+#define R_TIM_BGLOADVAL 2
+#define R_TIM_CTRL 3
+#define R_TIM_RIS 4
+#define R_TIM_MIS 5
+
+#define TIMER_CTRL_ENBL (1 << 0)
+#define TIMER_CTRL_ONESHOT (1 << 1)
+#define TIMER_CTRL_INTR (1 << 2)
+#define TIMER_RIS_ACK (1 << 0)
+#define TIMER_RST_CLR (1 << 6)
+#define TIMER_MODE (1 << 0)
+
+static void timer_update_irq(struct Msf2Timer *st)
+{
+ bool isr, ier;
+
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+ qemu_set_irq(st->irq, (ier && isr));
+}
+
+static void timer_update(struct Msf2Timer *st)
+{
+ uint64_t count;
+
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
+ ptimer_stop(st->ptimer);
+ return;
+ }
+
+ count = st->regs[R_TIM_LOADVAL];
+ ptimer_set_limit(st->ptimer, count, 1);
+ ptimer_run(st->ptimer, 1);
+}
+
+static uint64_t
+timer_read(void *opaque, hwaddr offset, unsigned int size)
+{
+ MSSTimerState *t = opaque;
+ hwaddr addr;
+ struct Msf2Timer *st;
+ uint32_t ret = 0;
+ int timer = 0;
+ int isr;
+ int ier;
+
+ addr = offset >> 2;
+ /*
+ * Two independent timers has same base address.
+ * Based on address passed figure out which timer is being used.
+ */
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
+ timer = 1;
+ addr -= R_TIM1_MAX;
+ }
+
+ st = &t->timers[timer];
+
+ switch (addr) {
+ case R_TIM_VAL:
+ ret = ptimer_get_count(st->ptimer);
+ break;
+
+ case R_TIM_MIS:
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+ ret = ier & isr;
+ break;
+
+ default:
+ if (addr < R_TIM1_MAX) {
+ ret = st->regs[addr];
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
+ return ret;
+ }
+ break;
+ }
+
+ DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset,
+ ret);
+ return ret;
+}
+
+static void
+timer_write(void *opaque, hwaddr offset,
+ uint64_t val64, unsigned int size)
+{
+ MSSTimerState *t = opaque;
+ hwaddr addr;
+ struct Msf2Timer *st;
+ int timer = 0;
+ uint32_t value = val64;
+
+ addr = offset >> 2;
+ /*
+ * Two independent timers has same base address.
+ * Based on addr passed figure out which timer is being used.
+ */
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
+ timer = 1;
+ addr -= R_TIM1_MAX;
+ }
+
+ st = &t->timers[timer];
+
+ DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
+ value, timer);
+
+ switch (addr) {
+ case R_TIM_CTRL:
+ st->regs[R_TIM_CTRL] = value;
+ timer_update(st);
+ break;
+
+ case R_TIM_RIS:
+ if (value & TIMER_RIS_ACK) {
+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
+ }
+ break;
+
+ case R_TIM_LOADVAL:
+ st->regs[R_TIM_LOADVAL] = value;
+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
+ timer_update(st);
+ }
+ break;
+
+ case R_TIM_BGLOADVAL:
+ st->regs[R_TIM_BGLOADVAL] = value;
+ st->regs[R_TIM_LOADVAL] = value;
+ break;
+
+ case R_TIM_VAL:
+ case R_TIM_MIS:
+ break;
+
+ default:
+ if (addr < R_TIM1_MAX) {
+ st->regs[addr] = value;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
+ return;
+ }
+ break;
+ }
+ timer_update_irq(st);
+}
+
+static const MemoryRegionOps timer_ops = {
+ .read = timer_read,
+ .write = timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4
+ }
+};
+
+static void timer_hit(void *opaque)
+{
+ struct Msf2Timer *st = opaque;
+
+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
+
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
+ timer_update(st);
+ }
+ timer_update_irq(st);
+}
+
+static void mss_timer_init(Object *obj)
+{
+ MSSTimerState *t = MSS_TIMER(obj);
+ int i;
+
+ /* Init all the ptimers. */
+ for (i = 0; i < NUM_TIMERS; i++) {
+ struct Msf2Timer *st = &t->timers[i];
+
+ st->bh = qemu_bh_new(timer_hit, st);
+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
+ ptimer_set_freq(st->ptimer, t->freq_hz);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
+ }
+
+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
+ NUM_TIMERS * R_TIM1_MAX * 4);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
+}
+
+static const VMStateDescription vmstate_timers = {
+ .name = "mss-timer-block",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_PTIMER(ptimer, struct Msf2Timer),
+ VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_mss_timer = {
+ .name = TYPE_MSS_TIMER,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(freq_hz, MSSTimerState),
+ VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
+ vmstate_timers, struct Msf2Timer),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property mss_timer_properties[] = {
+ /* Libero GUI shows 100Mhz as default for clocks */
+ DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
+ 100 * 1000000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void mss_timer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->props = mss_timer_properties;
+ dc->vmsd = &vmstate_mss_timer;
+}
+
+static const TypeInfo mss_timer_info = {
+ .name = TYPE_MSS_TIMER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSSTimerState),
+ .instance_init = mss_timer_init,
+ .class_init = mss_timer_class_init,
+};
+
+static void mss_timer_register_types(void)
+{
+ type_register_static(&mss_timer_info);
+}
+
+type_init(mss_timer_register_types)
diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
new file mode 100644
index 0000000..d15d173
--- /dev/null
+++ b/include/hw/timer/mss-timer.h
@@ -0,0 +1,64 @@
+/*
+ * Microsemi SmartFusion2 Timer.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSS_TIMER_H
+#define HW_MSS_TIMER_H
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+
+#define TYPE_MSS_TIMER "mss-timer"
+#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \
+ (obj), TYPE_MSS_TIMER)
+
+/*
+ * There are two 32-bit down counting timers.
+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer
+ * that operates either in Periodic mode or in One-shot mode.
+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
+ * In 64-bit mode, writing to the 32-bit registers has no effect.
+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers
+ * has no effect. Only two 32-bit timers are supported currently.
+ */
+#define NUM_TIMERS 2
+
+#define R_TIM1_MAX 6
+
+struct Msf2Timer {
+ QEMUBH *bh;
+ ptimer_state *ptimer;
+
+ uint32_t regs[R_TIM1_MAX];
+ qemu_irq irq;
+};
+
+typedef struct MSSTimerState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+ uint32_t freq_hz;
+ struct Msf2Timer timers[NUM_TIMERS];
+} MSSTimerState;
+
+#endif /* HW_MSS_TIMER_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block
2017-09-07 19:24 [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
@ 2017-09-07 19:24 ` Subbaraya Sundeep
2017-09-14 4:36 ` Philippe Mathieu-Daudé
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
` (3 subsequent siblings)
5 siblings, 1 reply; 28+ messages in thread
From: Subbaraya Sundeep @ 2017-09-07 19:24 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Added Sytem register block of Smartfusion2.
This block has PLL registers which are accessed by guest.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/msf2-sysreg.c | 195 ++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/msf2-sysreg.h | 78 +++++++++++++++++
3 files changed, 274 insertions(+)
create mode 100644 hw/misc/msf2-sysreg.c
create mode 100644 include/hw/misc/msf2-sysreg.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 29fb922..e8f0a02 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
obj-y += mmio_interface.o
+obj-$(CONFIG_MSF2) += msf2-sysreg.o
diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
new file mode 100644
index 0000000..40d603d
--- /dev/null
+++ b/hw/misc/msf2-sysreg.c
@@ -0,0 +1,195 @@
+/*
+ * System Register block model of Microsemi SmartFusion2.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/misc/msf2-sysreg.h"
+
+#ifndef MSF2_SYSREG_ERR_DEBUG
+#define MSF2_SYSREG_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static inline int msf2_divbits(uint32_t div)
+{
+ int ret = 0;
+
+ switch (div) {
+ case 1:
+ ret = 0;
+ break;
+ case 2:
+ ret = 1;
+ break;
+ case 4:
+ ret = 2;
+ break;
+ case 8:
+ ret = 4;
+ break;
+ case 16:
+ ret = 5;
+ break;
+ case 32:
+ ret = 6;
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static void msf2_sysreg_reset(DeviceState *d)
+{
+ MSF2SysregState *s = MSF2_SYSREG(d);
+
+ DB_PRINT("RESET");
+
+ s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
+ s->regs[MSSDDR_PLL_STATUS] = 0x3;
+ s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
+ msf2_divbits(s->apb1div) << 2;
+}
+
+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ MSF2SysregState *s = opaque;
+ uint32_t ret = 0;
+
+ offset >>= 2;
+ if (offset < ARRAY_SIZE(s->regs)) {
+ ret = s->regs[offset];
+ DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32,
+ offset << 2, ret);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
+ offset << 2);
+ }
+
+ return ret;
+}
+
+static void msf2_sysreg_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ MSF2SysregState *s = opaque;
+ uint32_t newval = val;
+
+ DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64,
+ offset, val);
+
+ offset >>= 2;
+
+ switch (offset) {
+ case MSSDDR_PLL_STATUS:
+ break;
+
+ case ESRAM_CR:
+ if (newval != s->regs[ESRAM_CR]) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSF2_SYSREG": eSRAM remapping not supported\n");
+ }
+ break;
+
+ case DDR_CR:
+ if (newval != s->regs[DDR_CR]) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSF2_SYSREG": DDR remapping not supported\n");
+ }
+ break;
+
+ case ENVM_REMAP_BASE_CR:
+ if (newval != s->regs[ENVM_REMAP_BASE_CR]) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSF2_SYSREG": eNVM remapping not supported\n");
+ }
+ break;
+
+ default:
+ if (offset < ARRAY_SIZE(s->regs)) {
+ s->regs[offset] = newval;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
+ offset << 2);
+ }
+ break;
+ }
+}
+
+static const MemoryRegionOps sysreg_ops = {
+ .read = msf2_sysreg_read,
+ .write = msf2_sysreg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void msf2_sysreg_init(Object *obj)
+{
+ MSF2SysregState *s = MSF2_SYSREG(obj);
+
+ memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
+ MSF2_SYSREG_MMIO_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
+
+static const VMStateDescription vmstate_msf2_sysreg = {
+ .name = TYPE_MSF2_SYSREG,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property msf2_sysreg_properties[] = {
+ /* default divisors in Libero GUI */
+ DEFINE_PROP_UINT32("apb0divisor", MSF2SysregState, apb0div, 2),
+ DEFINE_PROP_UINT32("apb1divisor", MSF2SysregState, apb1div, 2),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_msf2_sysreg;
+ dc->reset = msf2_sysreg_reset;
+ dc->props = msf2_sysreg_properties;
+}
+
+static const TypeInfo msf2_sysreg_info = {
+ .name = TYPE_MSF2_SYSREG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .class_init = msf2_sysreg_class_init,
+ .instance_size = sizeof(MSF2SysregState),
+ .instance_init = msf2_sysreg_init,
+};
+
+static void msf2_sysreg_register_types(void)
+{
+ type_register_static(&msf2_sysreg_info);
+}
+
+type_init(msf2_sysreg_register_types)
diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
new file mode 100644
index 0000000..f39cc41
--- /dev/null
+++ b/include/hw/misc/msf2-sysreg.h
@@ -0,0 +1,78 @@
+/*
+ * Microsemi SmartFusion2 SYSREG
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSF2_SYSREG_H
+#define HW_MSF2_SYSREG_H
+
+#include "hw/sysbus.h"
+
+enum {
+ ESRAM_CR = 0x00 / 4,
+ ESRAM_MAX_LAT,
+ DDR_CR,
+ ENVM_CR,
+ ENVM_REMAP_BASE_CR,
+ ENVM_REMAP_FAB_CR,
+ CC_CR,
+ CC_REGION_CR,
+ CC_LOCK_BASE_ADDR_CR,
+ CC_FLUSH_INDX_CR,
+ DDRB_BUF_TIMER_CR,
+ DDRB_NB_ADDR_CR,
+ DDRB_NB_SIZE_CR,
+ DDRB_CR,
+
+ SOFT_RESET_CR = 0x48 / 4,
+ M3_CR,
+
+ GPIO_SYSRESET_SEL_CR = 0x58 / 4,
+
+ MDDR_CR = 0x60 / 4,
+
+ MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
+ MSSDDR_PLL_STATUS_HIGH_CR,
+ MSSDDR_FACC1_CR,
+ MSSDDR_FACC2_CR,
+
+ MSSDDR_PLL_STATUS = 0x150 / 4,
+
+};
+
+#define MSF2_SYSREG_MMIO_SIZE 0x300
+
+#define TYPE_MSF2_SYSREG "msf2-sysreg"
+#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
+
+typedef struct MSF2SysregState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ uint32_t apb0div;
+ uint32_t apb1div;
+
+ uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];
+} MSF2SysregState;
+
+#endif /* HW_MSF2_SYSREG_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
2017-09-07 19:24 [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
@ 2017-09-07 19:24 ` Subbaraya Sundeep
2017-09-12 23:50 ` Alistair Francis
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
` (2 subsequent siblings)
5 siblings, 1 reply; 28+ messages in thread
From: Subbaraya Sundeep @ 2017-09-07 19:24 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Modelled Microsemi's Smartfusion2 SPI controller.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
hw/ssi/Makefile.objs | 1 +
hw/ssi/mss-spi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++
include/hw/ssi/mss-spi.h | 58 +++++++
3 files changed, 463 insertions(+)
create mode 100644 hw/ssi/mss-spi.c
create mode 100644 include/hw/ssi/mss-spi.h
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index 487add2..f5bcc65 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
+common-obj-$(CONFIG_MSF2) += mss-spi.o
obj-$(CONFIG_OMAP) += omap_spi.o
obj-$(CONFIG_IMX) += imx_spi.o
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
new file mode 100644
index 0000000..5a8e308
--- /dev/null
+++ b/hw/ssi/mss-spi.c
@@ -0,0 +1,404 @@
+/*
+ * Block model of SPI controller present in
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
+ *
+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/ssi/mss-spi.h"
+#include "qemu/log.h"
+
+#ifndef MSS_SPI_ERR_DEBUG
+#define MSS_SPI_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSS_SPI_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt "\n", __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+#define FIFO_CAPACITY 32
+
+#define R_SPI_CONTROL 0
+#define R_SPI_DFSIZE 1
+#define R_SPI_STATUS 2
+#define R_SPI_INTCLR 3
+#define R_SPI_RX 4
+#define R_SPI_TX 5
+#define R_SPI_CLKGEN 6
+#define R_SPI_SS 7
+#define R_SPI_MIS 8
+#define R_SPI_RIS 9
+
+#define S_TXDONE (1 << 0)
+#define S_RXRDY (1 << 1)
+#define S_RXCHOVRF (1 << 2)
+#define S_RXFIFOFUL (1 << 4)
+#define S_RXFIFOFULNXT (1 << 5)
+#define S_RXFIFOEMP (1 << 6)
+#define S_RXFIFOEMPNXT (1 << 7)
+#define S_TXFIFOFUL (1 << 8)
+#define S_TXFIFOFULNXT (1 << 9)
+#define S_TXFIFOEMP (1 << 10)
+#define S_TXFIFOEMPNXT (1 << 11)
+#define S_FRAMESTART (1 << 12)
+#define S_SSEL (1 << 13)
+#define S_ACTIVE (1 << 14)
+
+#define C_ENABLE (1 << 0)
+#define C_MODE (1 << 1)
+#define C_INTRXDATA (1 << 4)
+#define C_INTTXDATA (1 << 5)
+#define C_INTRXOVRFLO (1 << 6)
+#define C_SPS (1 << 26)
+#define C_BIGFIFO (1 << 29)
+#define C_RESET (1 << 31)
+
+#define FRAMESZ_MASK 0x1F
+#define FMCOUNT_MASK 0x00FFFF00
+#define FMCOUNT_SHIFT 8
+
+static void txfifo_reset(MSSSpiState *s)
+{
+ fifo32_reset(&s->tx_fifo);
+
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
+}
+
+static void rxfifo_reset(MSSSpiState *s)
+{
+ fifo32_reset(&s->rx_fifo);
+
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+}
+
+static void set_fifodepth(MSSSpiState *s)
+{
+ unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
+
+ if (size <= 8) {
+ s->fifo_depth = 32;
+ } else if (size <= 16) {
+ s->fifo_depth = 16;
+ } else if (size <= 32) {
+ s->fifo_depth = 8;
+ } else {
+ s->fifo_depth = 4;
+ }
+}
+
+static void update_mis(MSSSpiState *s)
+{
+ uint32_t reg = s->regs[R_SPI_CONTROL];
+ uint32_t tmp;
+
+ /*
+ * form the Control register interrupt enable bits
+ * same as RIS, MIS and Interrupt clear registers for simplicity
+ */
+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
+ ((reg & C_INTTXDATA) >> 5);
+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
+}
+
+static void spi_update_irq(MSSSpiState *s)
+{
+ int irq;
+
+ update_mis(s);
+ irq = !!(s->regs[R_SPI_MIS]);
+
+ qemu_set_irq(s->irq, irq);
+}
+
+static void mss_spi_reset(DeviceState *d)
+{
+ MSSSpiState *s = MSS_SPI(d);
+
+ memset(s->regs, 0, sizeof s->regs);
+ s->regs[R_SPI_CONTROL] = 0x80000102;
+ s->regs[R_SPI_DFSIZE] = 0x4;
+ s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
+ s->regs[R_SPI_CLKGEN] = 0x7;
+ s->regs[R_SPI_RIS] = 0x0;
+
+ s->fifo_depth = 4;
+ s->frame_count = 1;
+ s->enabled = false;
+
+ rxfifo_reset(s);
+ txfifo_reset(s);
+}
+
+static uint64_t
+spi_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ MSSSpiState *s = opaque;
+ uint32_t ret = 0;
+
+ addr >>= 2;
+ switch (addr) {
+ case R_SPI_RX:
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+ s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
+ ret = fifo32_pop(&s->rx_fifo);
+ if (fifo32_is_empty(&s->rx_fifo)) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+ }
+ break;
+
+ case R_SPI_MIS:
+ update_mis(s);
+ ret = s->regs[R_SPI_MIS];
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(s->regs)) {
+ ret = s->regs[addr];
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
+ addr * 4);
+ return ret;
+ }
+ break;
+ }
+
+ DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
+ spi_update_irq(s);
+ return ret;
+}
+
+static void assert_cs(MSSSpiState *s)
+{
+ qemu_set_irq(s->cs_line, 0);
+}
+
+static void deassert_cs(MSSSpiState *s)
+{
+ qemu_set_irq(s->cs_line, 1);
+}
+
+static void spi_flush_txfifo(MSSSpiState *s)
+{
+ uint32_t tx;
+ uint32_t rx;
+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
+
+ /*
+ * Chip Select(CS) is automatically controlled by this controller.
+ * If SPS bit is set in Control register then CS is asserted
+ * until all the frames set in frame count of Control register are
+ * transferred. If SPS is not set then CS pulses between frames.
+ * Note that Slave Select register specifies which of the CS line
+ * has to be controlled automatically by controller. Bits SS[7:1] are for
+ * masters in FPGA fabric since we model only Microcontroller subsystem
+ * of Smartfusion2 we control only one CS(SS[0]) line.
+ */
+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
+ assert_cs(s);
+
+ s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
+
+ tx = fifo32_pop(&s->tx_fifo);
+ DB_PRINT("data tx:0x%" PRIx32, tx);
+ rx = ssi_transfer(s->spi, tx);
+ DB_PRINT("data rx:0x%" PRIx32, rx);
+
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
+ s->regs[R_SPI_RIS] |= S_RXCHOVRF;
+ } else {
+ fifo32_push(&s->rx_fifo, rx);
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
+ } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
+ }
+ }
+ s->frame_count--;
+ if (!sps) {
+ deassert_cs(s);
+ }
+ }
+
+ if (!s->frame_count) {
+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
+ FMCOUNT_SHIFT;
+ deassert_cs(s);
+ s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
+ s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
+ }
+}
+
+static void spi_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ MSSSpiState *s = opaque;
+ uint32_t value = val64;
+
+ DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
+ addr >>= 2;
+
+ switch (addr) {
+ case R_SPI_TX:
+ /* adding to already full FIFO */
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
+ break;
+ }
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
+ fifo32_push(&s->tx_fifo, value);
+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
+ } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
+ }
+ if (s->enabled) {
+ spi_flush_txfifo(s);
+ }
+ break;
+
+ case R_SPI_CONTROL:
+ s->regs[R_SPI_CONTROL] = value;
+ if (value & C_BIGFIFO) {
+ set_fifodepth(s);
+ } else {
+ s->fifo_depth = 4;
+ }
+ s->enabled = value & C_ENABLE;
+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
+ if (value & C_RESET) {
+ mss_spi_reset(DEVICE(s));
+ }
+ break;
+
+ case R_SPI_DFSIZE:
+ if (s->enabled) {
+ break;
+ }
+ s->regs[R_SPI_DFSIZE] = value;
+ break;
+
+ case R_SPI_INTCLR:
+ s->regs[R_SPI_INTCLR] = value;
+ if (value & S_TXDONE) {
+ s->regs[R_SPI_RIS] &= ~S_TXDONE;
+ }
+ if (value & S_RXRDY) {
+ s->regs[R_SPI_RIS] &= ~S_RXRDY;
+ }
+ if (value & S_RXCHOVRF) {
+ s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
+ }
+ break;
+
+ case R_SPI_MIS:
+ case R_SPI_STATUS:
+ case R_SPI_RIS:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
+ __func__, addr * 4);
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(s->regs)) {
+ s->regs[addr] = value;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
+ addr * 4);
+ }
+ break;
+ }
+
+ spi_update_irq(s);
+}
+
+static const MemoryRegionOps spi_ops = {
+ .read = spi_read,
+ .write = spi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4
+ }
+};
+
+static void mss_spi_realize(DeviceState *dev, Error **errp)
+{
+ MSSSpiState *s = MSS_SPI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ s->spi = ssi_create_bus(dev, "spi");
+
+ sysbus_init_irq(sbd, &s->irq);
+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
+ sysbus_init_irq(sbd, &s->cs_line);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
+ TYPE_MSS_SPI, R_SPI_MAX * 4);
+ sysbus_init_mmio(sbd, &s->mmio);
+
+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
+}
+
+static const VMStateDescription vmstate_mss_spi = {
+ .name = TYPE_MSS_SPI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_FIFO32(tx_fifo, MSSSpiState),
+ VMSTATE_FIFO32(rx_fifo, MSSSpiState),
+ VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void mss_spi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = mss_spi_realize;
+ dc->reset = mss_spi_reset;
+ dc->vmsd = &vmstate_mss_spi;
+}
+
+static const TypeInfo mss_spi_info = {
+ .name = TYPE_MSS_SPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSSSpiState),
+ .class_init = mss_spi_class_init,
+};
+
+static void mss_spi_register_types(void)
+{
+ type_register_static(&mss_spi_info);
+}
+
+type_init(mss_spi_register_types)
diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
new file mode 100644
index 0000000..f0cf324
--- /dev/null
+++ b/include/hw/ssi/mss-spi.h
@@ -0,0 +1,58 @@
+/*
+ * Microsemi SmartFusion2 SPI
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSS_SPI_H
+#define HW_MSS_SPI_H
+
+#include "hw/sysbus.h"
+#include "hw/ssi/ssi.h"
+#include "qemu/fifo32.h"
+
+#define TYPE_MSS_SPI "mss-spi"
+#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
+
+#define R_SPI_MAX 16
+
+typedef struct MSSSpiState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ qemu_irq irq;
+
+ qemu_irq cs_line;
+
+ SSIBus *spi;
+
+ Fifo32 rx_fifo;
+ Fifo32 tx_fifo;
+
+ int fifo_depth;
+ uint32_t frame_count;
+ bool enabled;
+
+ uint32_t regs[R_SPI_MAX];
+} MSSSpiState;
+
+#endif /* HW_MSS_SPI_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC
2017-09-07 19:24 [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (2 preceding siblings ...)
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
@ 2017-09-07 19:24 ` Subbaraya Sundeep
2017-09-07 21:38 ` Philippe Mathieu-Daudé
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
2017-09-07 21:44 ` [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Philippe Mathieu-Daudé
5 siblings, 1 reply; 28+ messages in thread
From: Subbaraya Sundeep @ 2017-09-07 19:24 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Smartfusion2 SoC has hardened Microcontroller subsystem
and flash based FPGA fabric. This patch adds support for
Microcontroller subsystem in the SoC.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs | 1 +
hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++++++++++++++++++++
include/hw/arm/msf2-soc.h | 66 ++++++++++++
4 files changed, 286 insertions(+)
create mode 100644 hw/arm/msf2-soc.c
create mode 100644 include/hw/arm/msf2-soc.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index bbdd3c1..5059d13 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -129,3 +129,4 @@ CONFIG_ACPI=y
CONFIG_SMBIOS=y
CONFIG_ASPEED_SOC=y
CONFIG_GPIO_KEY=y
+CONFIG_MSF2=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index a2e56ec..df36a03 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
obj-$(CONFIG_MPS2) += mps2.o
+obj-$(CONFIG_MSF2) += msf2-soc.o
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
new file mode 100644
index 0000000..47fffa4
--- /dev/null
+++ b/hw/arm/msf2-soc.c
@@ -0,0 +1,218 @@
+/*
+ * SmartFusion2 SoC emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "hw/char/serial.h"
+#include "hw/boards.h"
+#include "sysemu/block-backend.h"
+#include "qemu/cutils.h"
+#include "hw/arm/msf2-soc.h"
+
+#define MSF2_TIMER_BASE 0x40004000
+#define MSF2_SYSREG_BASE 0x40038000
+
+#define ENVM_BASE_ADDRESS 0x60000000
+
+#define SRAM_BASE_ADDRESS 0x20000000
+
+#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
+
+/*
+ * eSRAM max size is 80k without SECDED(Single error correction and
+ * dual error detection) feature and 64k with SECDED.
+ * We do not support SECDED now.
+ */
+#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
+
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
+
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
+
+static void m2sxxx_soc_initfn(Object *obj)
+{
+ MSF2State *s = MSF2_SOC(obj);
+ int i;
+
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
+
+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
+
+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
+
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
+ TYPE_MSS_SPI);
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+ }
+}
+
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+ MSF2State *s = MSF2_SOC(dev_soc);
+ DeviceState *dev, *armv7m;
+ SysBusDevice *busdev;
+ Error *err = NULL;
+ int i;
+
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *nvm = g_new(MemoryRegion, 1);
+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
+
+ memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
+ &error_fatal);
+ /*
+ * On power-on, the eNVM region 0x60000000 is automatically
+ * remapped to the Cortex-M3 processor executable region
+ * start address (0x0). We do not support remapping other eNVM,
+ * eSRAM and DDR regions by guest(via Sysreg) currently.
+ */
+ memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
+ nvm, 0, s->envm_size);
+
+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
+ memory_region_add_subregion(system_memory, 0, nvm_alias);
+
+ memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
+ &error_fatal);
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+ armv7m = DEVICE(&s->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 81);
+ qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
+ "memory", &error_abort);
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
+
+ for (i = 0; i < MSF2_NUM_UARTS; i++) {
+ if (serial_hds[i]) {
+ serial_mm_init(get_system_memory(), uart_addr[i], 2,
+ qdev_get_gpio_in(armv7m, uart_irq[i]),
+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
+ }
+ }
+
+ dev = DEVICE(&s->timer);
+ /* APB0 clock is the timer input clock */
+ qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
+ object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(armv7m, timer_irq[0]));
+ sysbus_connect_irq(busdev, 1,
+ qdev_get_gpio_in(armv7m, timer_irq[1]));
+
+ dev = DEVICE(&s->sysreg);
+ qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
+ qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
+ object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
+
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
+ gchar *bus_name;
+
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ qdev_get_gpio_in(armv7m, spi_irq[i]));
+
+ /* Alias controller SPI bus to the SoC itself */
+ bus_name = g_strdup_printf("spi%d", i);
+ object_property_add_alias(OBJECT(s), bus_name,
+ OBJECT(&s->spi[i]), "spi",
+ &error_abort);
+ g_free(bus_name);
+ }
+}
+
+static Property m2sxxx_soc_properties[] = {
+ /*
+ * part name specifies the type of SmartFusion2 device variant(this
+ * property is for information purpose only.
+ */
+ DEFINE_PROP_STRING("part-name", MSF2State, part_name),
+ DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
+ DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
+ MSF2_ESRAM_MAX_SIZE),
+ /* Libero GUI shows 100Mhz as default for clocks */
+ DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
+ /* default divisors in Libero GUI */
+ DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2),
+ DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = m2sxxx_soc_realize;
+ dc->props = m2sxxx_soc_properties;
+}
+
+static const TypeInfo m2sxxx_soc_info = {
+ .name = TYPE_MSF2_SOC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSF2State),
+ .instance_init = m2sxxx_soc_initfn,
+ .class_init = m2sxxx_soc_class_init,
+};
+
+static void m2sxxx_soc_types(void)
+{
+ type_register_static(&m2sxxx_soc_info);
+}
+
+type_init(m2sxxx_soc_types)
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
new file mode 100644
index 0000000..eb239fa
--- /dev/null
+++ b/include/hw/arm/msf2-soc.h
@@ -0,0 +1,66 @@
+/*
+ * Microsemi Smartfusion2 SoC
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_MSF2_SOC_H
+#define HW_ARM_MSF2_SOC_H
+
+#include "hw/arm/armv7m.h"
+#include "hw/timer/mss-timer.h"
+#include "hw/misc/msf2-sysreg.h"
+#include "hw/ssi/mss-spi.h"
+
+#define TYPE_MSF2_SOC "msf2-soc"
+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
+
+#define MSF2_NUM_SPIS 2
+#define MSF2_NUM_UARTS 2
+
+/*
+ * System timer consists of two programmable 32-bit
+ * decrementing counters that generate individual interrupts to
+ * the Cortex-M3 processor
+ */
+#define MSF2_NUM_TIMERS 2
+
+typedef struct MSF2State {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ ARMv7MState armv7m;
+
+ char *part_name;
+ uint64_t envm_size;
+ uint64_t esram_size;
+
+ uint32_t m3clk;
+ uint32_t apb0div;
+ uint32_t apb1div;
+
+ MSF2SysregState sysreg;
+ MSSTimerState timer;
+ MSSSpiState spi[MSF2_NUM_SPIS];
+} MSF2State;
+
+#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [Qemu devel v8 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit
2017-09-07 19:24 [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (3 preceding siblings ...)
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
@ 2017-09-07 19:24 ` Subbaraya Sundeep
2017-09-14 17:14 ` Peter Maydell
2017-09-07 21:44 ` [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Philippe Mathieu-Daudé
5 siblings, 1 reply; 28+ messages in thread
From: Subbaraya Sundeep @ 2017-09-07 19:24 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Emulated Emcraft's Smartfusion2 System On Module starter
kit.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/Makefile.objs | 2 +-
hw/arm/msf2-som.c | 95 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 96 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/msf2-som.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index df36a03..e81a7dc 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -19,4 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
obj-$(CONFIG_MPS2) += mps2.o
-obj-$(CONFIG_MSF2) += msf2-soc.o
+obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
new file mode 100644
index 0000000..bc917db
--- /dev/null
+++ b/hw/arm/msf2-som.c
@@ -0,0 +1,95 @@
+/*
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "qemu/cutils.h"
+#include "hw/arm/msf2-soc.h"
+
+#define DDR_BASE_ADDRESS 0xA0000000
+#define DDR_SIZE (64 * M_BYTE)
+
+#define M2S010_ENVM_SIZE (256 * K_BYTE)
+#define M2S010_ESRAM_SIZE (64 * K_BYTE)
+
+static void emcraft_sf2_s2s010_init(MachineState *machine)
+{
+ DeviceState *dev;
+ DeviceState *spi_flash;
+ MSF2State *soc;
+ DriveInfo *dinfo = drive_get_next(IF_MTD);
+ qemu_irq cs_line;
+ SSIBus *spi_bus;
+ MemoryRegion *sysmem = get_system_memory();
+ MemoryRegion *ddr = g_new(MemoryRegion, 1);
+
+ memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
+ &error_fatal);
+ memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
+
+ dev = qdev_create(NULL, TYPE_MSF2_SOC);
+ qdev_prop_set_string(dev, "part-name", "M2S010");
+ qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
+ qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
+
+ /*
+ * CPU clock and peripheral clocks(APB0, APB1)are configurable
+ * in Libero. CPU clock is divided by APB0 and APB1 divisors for
+ * peripherals. Emcraft's SoM kit comes with these settings by default.
+ */
+ qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
+ qdev_prop_set_uint32(dev, "apb0div", 2);
+ qdev_prop_set_uint32(dev, "apb1div", 2);
+
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
+
+ soc = MSF2_SOC(dev);
+
+ /* Attach SPI flash to SPI0 controller */
+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
+ if (dinfo) {
+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
+ &error_fatal);
+ }
+ qdev_init_nofail(spi_flash);
+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
+
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ soc->envm_size);
+}
+
+static void emcraft_sf2_machine_init(MachineClass *mc)
+{
+ mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
+ mc->init = emcraft_sf2_s2s010_init;
+ mc->ignore_memory_transaction_failures = true;
+}
+
+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
--
2.5.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
@ 2017-09-07 21:38 ` Philippe Mathieu-Daudé
2017-09-08 7:26 ` sundeep subbaraya
0 siblings, 1 reply; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-07 21:38 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23
On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
> Smartfusion2 SoC has hardened Microcontroller subsystem
> and flash based FPGA fabric. This patch adds support for
> Microcontroller subsystem in the SoC.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/Makefile.objs | 1 +
> hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++++++++++++++++++++
> include/hw/arm/msf2-soc.h | 66 ++++++++++++
> 4 files changed, 286 insertions(+)
> create mode 100644 hw/arm/msf2-soc.c
> create mode 100644 include/hw/arm/msf2-soc.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index bbdd3c1..5059d13 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -129,3 +129,4 @@ CONFIG_ACPI=y
> CONFIG_SMBIOS=y
> CONFIG_ASPEED_SOC=y
> CONFIG_GPIO_KEY=y
> +CONFIG_MSF2=y
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index a2e56ec..df36a03 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
> obj-$(CONFIG_MPS2) += mps2.o
> +obj-$(CONFIG_MSF2) += msf2-soc.o
> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
> new file mode 100644
> index 0000000..47fffa4
> --- /dev/null
> +++ b/hw/arm/msf2-soc.c
> @@ -0,0 +1,218 @@
> +/*
> + * SmartFusion2 SoC emulation.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "hw/arm/arm.h"
> +#include "exec/address-spaces.h"
> +#include "hw/char/serial.h"
> +#include "hw/boards.h"
> +#include "sysemu/block-backend.h"
> +#include "qemu/cutils.h"
> +#include "hw/arm/msf2-soc.h"
> +
> +#define MSF2_TIMER_BASE 0x40004000
> +#define MSF2_SYSREG_BASE 0x40038000
> +
> +#define ENVM_BASE_ADDRESS 0x60000000
> +
> +#define SRAM_BASE_ADDRESS 0x20000000
> +
> +#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
> +
> +/*
> + * eSRAM max size is 80k without SECDED(Single error correction and
> + * dual error detection) feature and 64k with SECDED.
> + * We do not support SECDED now.
> + */
> +#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
> +
> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
> +
> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
> +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
> +
> +static void m2sxxx_soc_initfn(Object *obj)
> +{
> + MSF2State *s = MSF2_SOC(obj);
> + int i;
> +
> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
> +
> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
> +
> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
> +
> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
> + TYPE_MSS_SPI);
> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
> + }
> +}
> +
> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> +{
> + MSF2State *s = MSF2_SOC(dev_soc);
> + DeviceState *dev, *armv7m;
> + SysBusDevice *busdev;
> + Error *err = NULL;
> + int i;
> +
> + MemoryRegion *system_memory = get_system_memory();
> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
> + MemoryRegion *sram = g_new(MemoryRegion, 1);
> +
> + memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
> + &error_fatal);
> + /*
> + * On power-on, the eNVM region 0x60000000 is automatically
> + * remapped to the Cortex-M3 processor executable region
> + * start address (0x0). We do not support remapping other eNVM,
> + * eSRAM and DDR regions by guest(via Sysreg) currently.
> + */
> + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
you can drop the ".alias", this function already prepends "alias "
> + nvm, 0, s->envm_size);
> +
> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
> + memory_region_add_subregion(system_memory, 0, nvm_alias);
> +
> + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
> + &error_fatal);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> +
> + armv7m = DEVICE(&s->armv7m);
> + qdev_prop_set_uint32(armv7m, "num-irq", 81);
> + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
> + "memory", &error_abort);
> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
> +
> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
> + if (serial_hds[i]) {
> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
> + qdev_get_gpio_in(armv7m, uart_irq[i]),
> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
> + }
> + }
> +
> + dev = DEVICE(&s->timer);
> + /* APB0 clock is the timer input clock */
> + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
> + sysbus_connect_irq(busdev, 0,
> + qdev_get_gpio_in(armv7m, timer_irq[0]));
> + sysbus_connect_irq(busdev, 1,
> + qdev_get_gpio_in(armv7m, timer_irq[1]));
> +
> + dev = DEVICE(&s->sysreg);
> + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
> + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
> +
> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> + gchar *bus_name;
> +
> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
> + qdev_get_gpio_in(armv7m, spi_irq[i]));
> +
> + /* Alias controller SPI bus to the SoC itself */
> + bus_name = g_strdup_printf("spi%d", i);
> + object_property_add_alias(OBJECT(s), bus_name,
> + OBJECT(&s->spi[i]), "spi",
> + &error_abort);
> + g_free(bus_name);
> + }
> +}
> +
> +static Property m2sxxx_soc_properties[] = {
> + /*
> + * part name specifies the type of SmartFusion2 device variant(this
> + * property is for information purpose only.
> + */
> + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
> + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
> + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
> + MSF2_ESRAM_MAX_SIZE),
> + /* Libero GUI shows 100Mhz as default for clocks */
> + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
> + /* default divisors in Libero GUI */
> + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2),
> + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = m2sxxx_soc_realize;
> + dc->props = m2sxxx_soc_properties;
> +}
> +
> +static const TypeInfo m2sxxx_soc_info = {
> + .name = TYPE_MSF2_SOC,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSF2State),
> + .instance_init = m2sxxx_soc_initfn,
> + .class_init = m2sxxx_soc_class_init,
> +};
> +
> +static void m2sxxx_soc_types(void)
> +{
> + type_register_static(&m2sxxx_soc_info);
> +}
> +
> +type_init(m2sxxx_soc_types)
> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
> new file mode 100644
> index 0000000..eb239fa
> --- /dev/null
> +++ b/include/hw/arm/msf2-soc.h
> @@ -0,0 +1,66 @@
> +/*
> + * Microsemi Smartfusion2 SoC
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_ARM_MSF2_SOC_H
> +#define HW_ARM_MSF2_SOC_H
> +
> +#include "hw/arm/armv7m.h"
> +#include "hw/timer/mss-timer.h"
> +#include "hw/misc/msf2-sysreg.h"
> +#include "hw/ssi/mss-spi.h"
> +
> +#define TYPE_MSF2_SOC "msf2-soc"
> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
> +
> +#define MSF2_NUM_SPIS 2
> +#define MSF2_NUM_UARTS 2
> +
> +/*
> + * System timer consists of two programmable 32-bit
> + * decrementing counters that generate individual interrupts to
> + * the Cortex-M3 processor
> + */
> +#define MSF2_NUM_TIMERS 2
> +
> +typedef struct MSF2State {
> + /*< private >*/
> + SysBusDevice parent_obj;
> + /*< public >*/
> +
> + ARMv7MState armv7m;
> +
> + char *part_name;
> + uint64_t envm_size;
> + uint64_t esram_size;
> +
> + uint32_t m3clk;
> + uint32_t apb0div;
> + uint32_t apb1div;
> +
> + MSF2SysregState sysreg;
> + MSSTimerState timer;
> + MSSSpiState spi[MSF2_NUM_SPIS];
> +} MSF2State;
> +
> +#endif
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC
2017-09-07 19:24 [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (4 preceding siblings ...)
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
@ 2017-09-07 21:44 ` Philippe Mathieu-Daudé
2017-09-08 7:24 ` sundeep subbaraya
5 siblings, 1 reply; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-07 21:44 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23
Hi Subbaraya,
very good work!
On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
> Hi Qemu-devel,
>
> I am trying to add Smartfusion2 SoC.
> SoC is from Microsemi and System on Module(SOM)
> board is from Emcraft systems. Smartfusion2 has hardened
> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
> At the moment only system timer, sysreg and SPI
> controller are modelled.
>
> Testing:
> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial mon:stdio \
> -kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw
"-M emcraft-sf2" ;)
U-Boot 2010.03-00147-g7da5092 (Jul 03 2017 - 09:04:50)
CPU : SmartFusion2 SoC (Cortex-M3 Hard IP)
Freqs: CORTEX-M3=142MHz,PCLK0=71MHz,PCLK1=71MHz
Board: M2S-FG484-SOM Rev 1A, www.emcraft.com
DRAM: 64 MB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: M2S_MAC
Hit any key to stop autoboot: 0
16384 KiB S25FL128P_64K at 0:0 is now current device
## Booting kernel from Legacy Image at a0007fc0 ...
Image Name: dtskernel
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2664224 Bytes = 2.5 MB
Load Address: a0008000
Entry Point: a0008001
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
NVIC: Bad read offset 0xd74
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.5.0-00001-g3aa90e8-dirty
(sundeep@sundeep-Vostro-3458) (gcc version 5.4.0 (GCC) ) #102 PREEMPT
Tue May 16 19:43:40 IST 2017
[ 0.000000] CPU: ARMv7-M [410fc231] revision 1 (ARMv7M), cr=00000000
[ 0.000000] CPU: unknown data cache, unknown instruction cache
[ 0.000000] Machine model: Microsemi SmartFusion 2 development board
[ 0.000000] Kernel command line: console=ttyS0,115200n8 panic=10
mem=64M@0xa0000000 earlyprintk
[ 0.000000] Memory: 62204K/65536K available (1472K kernel code, 73K
rwdata, 652K rodata, 400K init, 120K bss, 3332K reserved, 0K cma-reserved)
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.001178] sched_clock: 32 bits at 83MHz, resolution 12ns, wraps
every 25873297401ns
[ 0.003085] clocksource: msf2_clocksource: mask: 0xffffffff
max_cycles: 0xffffffff, max_idle_ns: 23027234290 ns
[ 0.009732] timer at 40004000, irq=16
[ 0.014475] Calibrating delay loop... 442.36 BogoMIPS (lpj=2211840)
[ 0.653685] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
[ 0.690789] console [ttyS0] disabled
[ 0.696659] 40000000.serial: ttyS0 at MMIO 0x40000000 (irq = 17,
base_baud = 5187500) is a 16550
[ 0.702725] console [ttyS0] enabled
[ 0.826251] Freeing unused kernel memory: 400K (a021c000 - a0280000)
init started: BusyBox v1.24.1 (2017-05-15 09:57:00 IST)
~ #
(qemu) info mtree
address-space: cpu-memory
0000000000000000-ffffffffffffffff (prio 0, i/o): armv7m-container
0000000000000000-ffffffffffffffff (prio -1, i/o): system
0000000000000000-000000000003ffff (prio 0, i/o): alias
MSF2.eNVM.alias @MSF2.eNVM 0000000000000000-000000000003ffff
0000000020000000-000000002000ffff (prio 0, ram): MSF2.eSRAM
0000000040000000-000000004000001f (prio 0, i/o): serial
0000000040001000-000000004000103f (prio 0, i/o): mss-spi
0000000040004000-000000004000402f (prio 0, i/o): mss-timer
0000000040011000-000000004001103f (prio 0, i/o): mss-spi
0000000040038000-00000000400382ff (prio 0, i/o): msf2-sysreg
0000000060000000-000000006003ffff (prio 0, rom): MSF2.eNVM
00000000a0000000-00000000a3ffffff (prio 0, ram): ddr-ram
0000000022000000-0000000023ffffff (prio 0, i/o): bitband
0000000042000000-0000000043ffffff (prio 0, i/o): bitband
00000000e000e000-00000000e000efff (prio 0, i/o): nvic
00000000e000e000-00000000e000efff (prio 0, i/o): nvic_sysregs
00000000e000e010-00000000e000e0ef (prio 1, i/o): systick
(qemu) info qtree
bus: main-system-bus
type System
dev: msf2-soc, id ""
part-name = "M2S010"
eNVM-size = 262144 (0x40000)
eSRAM-size = 65536 (0x10000)
m3clk = 142000000 (0x876bf80)
apb0div = 2 (0x2)
apb1div = 2 (0x2)
dev: mss-spi, id ""
gpio-out "sysbus-irq" 2
mmio 0000000040011000/0000000000000040
bus: spi
type SSI
dev: mss-spi, id ""
gpio-out "sysbus-irq" 2
mmio 0000000040001000/0000000000000040
bus: spi
type SSI
dev: s25sl12801, id ""
gpio-in "ssi-gpio-cs" 1
nonvolatile-cfg = 36863 (0x8fff)
spansion-cr1nv = 0 (0x0)
spansion-cr2nv = 1 (0x1)
spansion-cr3nv = 2 (0x2)
spansion-cr4nv = 16 (0x10)
drive = "mtd0"
dev: mss-timer, id ""
gpio-out "sysbus-irq" 2
clock-frequency = 71000000 (0x43b5fc0)
mmio 0000000040004000/0000000000000030
dev: msf2-sysreg, id ""
apb0divisor = 2 (0x2)
apb1divisor = 2 (0x2)
mmio 0000000040038000/0000000000000300
So far:
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Just some comments (no need to fix):
M2S-FG484-SOM> reset
resetting ...
M2S-FG484-SOM>
Hmm no reset, I was expecting some unimp/guest-error warning.
M2S-FG484-SOM> tftpboot
m2s_eth_init: FIFO initialization timeout
*** m2s_mac_dump_regs FIFO init:
DMA TX CTRL=00000000;DESC=00000000;STAT=00000000
DMA RX CTRL=00000000;DESC=00000000;STAT=00000000
DMA IRQ 00000000/00000000
CFG1=00000000;CFG2=00000000;IFG=00000000;HD=00000000;MFL=00000000
IFCTRL=00000000;IFSTAT=00000000;ADR1=00000000;ADR2=00000000
FIFO CFG 00000000/00000000/00000000/00000000/00000000/00000000/
FIFO ACC
00000000/00000000/00000000/00000000/00000000/00000000/00000000/00000000/
(same unimp/guest-error warning)
M2S-FG484-SOM> sf erase 0 0x1000
UNHANDLED EXCEPTION: HARD FAULT
R0 = 00000072 R1 = 00000072
R2 = 09fa3af0 R3 = 004c8000
R12 = 00000004 LR = 00000a27
PC = 0000ec98 PSR = 01000000
[hang]
IN:
0x0000029e: e7fe b.n 0x29e
>
> Binaries u-boot.bin and spi.bin are at:
> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>
> U-boot is from Emcraft with modified
> - SPI driver not to use PDMA.
> - ugly hack to pass dtb to kernel in r1.
> @
> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>
> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
> driver added by myself @
> https://github.com/Subbaraya-Sundeep/linux.git
>
> v8:
> memory_region_init_ram to memory_region_init_rom in soc
> %s/emcraft_sf2_init/emcraft_sf2_s2s010_init/g in som
> Added mc->ignore_memory_transaction_failures = true in som
> as per latest commit.
> Code simplifications as suggested by Alistair in sysreg and ssi.
>
> v7:
> Removed vmstate_register_ram_global as per latest commit
> Moved header files to C which are local to C source files
> Removed abort() from msf2-sysreg.c
> Added VMStateDescription in mss-timer.c
>
> v6:
> Moved some defines from header files to source files
> Added properties m3clk, apb0div, apb0div1 properties
> to soc.
> Added properties apb0divisor, apb1divisor to sysreg
> Update system_clock_source in msf2-soc.c
> Changed machine name smartfusion2-som->emcraft-sf2
>
> v5
> As per Philippe comments:
> Added abort in Sysreg if guest tries to remap memory
> other than default mapping.
> Use of CONFIG_MSF2 in Makefile for soc.c
> Fixed incorrect logic in timer model.
> Renamed msf2-timer.c -> mss-timer.c
> msf2-spi.c -> mss-spi.c also type names
> Renamed function msf2_init->emcraft_sf2_init in msf2-som.c
> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
> properties to soc.
> Pass soc part-name,memory size and clock rate properties from som.
> v4:
> Fixed build failure by using PRIx macros.
> v3:
> Added SoC file and board file as per Alistair comments.
> v2:
> Added SPI controller so that u-boot loads kernel from spi flash.
> v1:
> Initial patch set with timer and sysreg
>
> Thanks,
> Sundeep
>
>
> Subbaraya Sundeep (5):
> msf2: Add Smartfusion2 System timer
> msf2: Microsemi Smartfusion2 System Register block
> msf2: Add Smartfusion2 SPI controller
> msf2: Add Smartfusion2 SoC
> msf2: Add Emcraft's Smartfusion2 SOM kit
>
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/Makefile.objs | 1 +
> hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++
> hw/arm/msf2-som.c | 95 ++++++++++
> hw/misc/Makefile.objs | 1 +
> hw/misc/msf2-sysreg.c | 195 +++++++++++++++++++
> hw/ssi/Makefile.objs | 1 +
> hw/ssi/mss-spi.c | 404 ++++++++++++++++++++++++++++++++++++++++
> hw/timer/Makefile.objs | 1 +
> hw/timer/mss-timer.c | 289 ++++++++++++++++++++++++++++
> include/hw/arm/msf2-soc.h | 66 +++++++
> include/hw/misc/msf2-sysreg.h | 78 ++++++++
> include/hw/ssi/mss-spi.h | 58 ++++++
> include/hw/timer/mss-timer.h | 64 +++++++
> 14 files changed, 1472 insertions(+)
> create mode 100644 hw/arm/msf2-soc.c
> create mode 100644 hw/arm/msf2-som.c
> create mode 100644 hw/misc/msf2-sysreg.c
> create mode 100644 hw/ssi/mss-spi.c
> create mode 100644 hw/timer/mss-timer.c
> create mode 100644 include/hw/arm/msf2-soc.h
> create mode 100644 include/hw/misc/msf2-sysreg.h
> create mode 100644 include/hw/ssi/mss-spi.h
> create mode 100644 include/hw/timer/mss-timer.h
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC
2017-09-07 21:44 ` [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Philippe Mathieu-Daudé
@ 2017-09-08 7:24 ` sundeep subbaraya
2017-09-14 4:10 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-08 7:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Phillipe,
On Fri, Sep 8, 2017 at 3:14 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Subbaraya,
>
> very good work!
>
> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>
>> Hi Qemu-devel,
>>
>> I am trying to add Smartfusion2 SoC.
>> SoC is from Microsemi and System on Module(SOM)
>> board is from Emcraft systems. Smartfusion2 has hardened
>> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
>> At the moment only system timer, sysreg and SPI
>> controller are modelled.
>>
>> Testing:
>> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial mon:stdio \
>> -kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw
>>
>
> "-M emcraft-sf2" ;)
>
copy/paste error :)
>
> U-Boot 2010.03-00147-g7da5092 (Jul 03 2017 - 09:04:50)
>
> CPU : SmartFusion2 SoC (Cortex-M3 Hard IP)
> Freqs: CORTEX-M3=142MHz,PCLK0=71MHz,PCLK1=71MHz
> Board: M2S-FG484-SOM Rev 1A, www.emcraft.com
> DRAM: 64 MB
> *** Warning - bad CRC, using default environment
>
> In: serial
> Out: serial
> Err: serial
> Net: M2S_MAC
> Hit any key to stop autoboot: 0
> 16384 KiB S25FL128P_64K at 0:0 is now current device
> ## Booting kernel from Legacy Image at a0007fc0 ...
> Image Name: dtskernel
> Image Type: ARM Linux Kernel Image (uncompressed)
> Data Size: 2664224 Bytes = 2.5 MB
> Load Address: a0008000
> Entry Point: a0008001
> Verifying Checksum ... OK
> Loading Kernel Image ... OK
> OK
>
> Starting kernel ...
>
> NVIC: Bad read offset 0xd74
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.5.0-00001-g3aa90e8-dirty
> (sundeep@sundeep-Vostro-3458) (gcc version 5.4.0 (GCC) ) #102 PREEMPT Tue
> May 16 19:43:40 IST 2017
> [ 0.000000] CPU: ARMv7-M [410fc231] revision 1 (ARMv7M), cr=00000000
> [ 0.000000] CPU: unknown data cache, unknown instruction cache
> [ 0.000000] Machine model: Microsemi SmartFusion 2 development board
> [ 0.000000] Kernel command line: console=ttyS0,115200n8 panic=10
> mem=64M@0xa0000000 earlyprintk
> [ 0.000000] Memory: 62204K/65536K available (1472K kernel code, 73K
> rwdata, 652K rodata, 400K init, 120K bss, 3332K reserved, 0K cma-reserved)
> [ 0.000000] NR_IRQS:16 nr_irqs:16 16
> [ 0.001178] sched_clock: 32 bits at 83MHz, resolution 12ns, wraps every
> 25873297401ns
> [ 0.003085] clocksource: msf2_clocksource: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 23027234290 ns
> [ 0.009732] timer at 40004000, irq=16
> [ 0.014475] Calibrating delay loop... 442.36 BogoMIPS (lpj=2211840)
> [ 0.653685] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
> [ 0.690789] console [ttyS0] disabled
> [ 0.696659] 40000000.serial: ttyS0 at MMIO 0x40000000 (irq = 17,
> base_baud = 5187500) is a 16550
> [ 0.702725] console [ttyS0] enabled
> [ 0.826251] Freeing unused kernel memory: 400K (a021c000 - a0280000)
> init started: BusyBox v1.24.1 (2017-05-15 09:57:00 IST)
> ~ #
>
> (qemu) info mtree
> address-space: cpu-memory
> 0000000000000000-ffffffffffffffff (prio 0, i/o): armv7m-container
> 0000000000000000-ffffffffffffffff (prio -1, i/o): system
> 0000000000000000-000000000003ffff (prio 0, i/o): alias
> MSF2.eNVM.alias @MSF2.eNVM 0000000000000000-000000000003ffff
> 0000000020000000-000000002000ffff (prio 0, ram): MSF2.eSRAM
> 0000000040000000-000000004000001f (prio 0, i/o): serial
> 0000000040001000-000000004000103f (prio 0, i/o): mss-spi
> 0000000040004000-000000004000402f (prio 0, i/o): mss-timer
> 0000000040011000-000000004001103f (prio 0, i/o): mss-spi
> 0000000040038000-00000000400382ff (prio 0, i/o): msf2-sysreg
> 0000000060000000-000000006003ffff (prio 0, rom): MSF2.eNVM
> 00000000a0000000-00000000a3ffffff (prio 0, ram): ddr-ram
> 0000000022000000-0000000023ffffff (prio 0, i/o): bitband
> 0000000042000000-0000000043ffffff (prio 0, i/o): bitband
> 00000000e000e000-00000000e000efff (prio 0, i/o): nvic
> 00000000e000e000-00000000e000efff (prio 0, i/o): nvic_sysregs
> 00000000e000e010-00000000e000e0ef (prio 1, i/o): systick
>
> (qemu) info qtree
> bus: main-system-bus
> type System
> dev: msf2-soc, id ""
> part-name = "M2S010"
> eNVM-size = 262144 (0x40000)
> eSRAM-size = 65536 (0x10000)
> m3clk = 142000000 (0x876bf80)
> apb0div = 2 (0x2)
> apb1div = 2 (0x2)
> dev: mss-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 0000000040011000/0000000000000040
> bus: spi
> type SSI
> dev: mss-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 0000000040001000/0000000000000040
> bus: spi
> type SSI
> dev: s25sl12801, id ""
> gpio-in "ssi-gpio-cs" 1
> nonvolatile-cfg = 36863 (0x8fff)
> spansion-cr1nv = 0 (0x0)
> spansion-cr2nv = 1 (0x1)
> spansion-cr3nv = 2 (0x2)
> spansion-cr4nv = 16 (0x10)
> drive = "mtd0"
> dev: mss-timer, id ""
> gpio-out "sysbus-irq" 2
> clock-frequency = 71000000 (0x43b5fc0)
> mmio 0000000040004000/0000000000000030
> dev: msf2-sysreg, id ""
> apb0divisor = 2 (0x2)
> apb1divisor = 2 (0x2)
> mmio 0000000040038000/0000000000000300
>
> So far:
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
Thanks for testing.
> Just some comments (no need to fix):
>
Thank you, I will look into these errors once the patchset gets into the
tree.
>
> M2S-FG484-SOM> reset
> resetting ...
> M2S-FG484-SOM>
>
> Hmm no reset, I was expecting some unimp/guest-error warning.
>
> M2S-FG484-SOM> tftpboot
> m2s_eth_init: FIFO initialization timeout
> *** m2s_mac_dump_regs FIFO init:
> DMA TX CTRL=00000000;DESC=00000000;STAT=00000000
> DMA RX CTRL=00000000;DESC=00000000;STAT=00000000
> DMA IRQ 00000000/00000000
> CFG1=00000000;CFG2=00000000;IFG=00000000;HD=00000000;MFL=00000000
> IFCTRL=00000000;IFSTAT=00000000;ADR1=00000000;ADR2=00000000
> FIFO CFG 00000000/00000000/00000000/00000000/00000000/00000000/
> FIFO ACC 00000000/00000000/00000000/00000000/00000000/00000000/000000
> 00/00000000/
>
> (same unimp/guest-error warning)
>
If device is not implemented how do I print warning when guest access that
device?
Thanks,
Sundeep
>
> M2S-FG484-SOM> sf erase 0 0x1000
> UNHANDLED EXCEPTION: HARD FAULT
> R0 = 00000072 R1 = 00000072
> R2 = 09fa3af0 R3 = 004c8000
> R12 = 00000004 LR = 00000a27
> PC = 0000ec98 PSR = 01000000
> [hang]
> IN:
> 0x0000029e: e7fe b.n 0x29e
>
>
>
>> Binaries u-boot.bin and spi.bin are at:
>> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>>
>> U-boot is from Emcraft with modified
>> - SPI driver not to use PDMA.
>> - ugly hack to pass dtb to kernel in r1.
>> @
>> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>>
>> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
>> driver added by myself @
>> https://github.com/Subbaraya-Sundeep/linux.git
>>
>> v8:
>> memory_region_init_ram to memory_region_init_rom in soc
>> %s/emcraft_sf2_init/emcraft_sf2_s2s010_init/g in som
>> Added mc->ignore_memory_transaction_failures = true in som
>> as per latest commit.
>> Code simplifications as suggested by Alistair in sysreg and ssi.
>>
>> v7:
>> Removed vmstate_register_ram_global as per latest commit
>> Moved header files to C which are local to C source files
>> Removed abort() from msf2-sysreg.c
>> Added VMStateDescription in mss-timer.c
>>
>> v6:
>> Moved some defines from header files to source files
>> Added properties m3clk, apb0div, apb0div1 properties
>> to soc.
>> Added properties apb0divisor, apb1divisor to sysreg
>> Update system_clock_source in msf2-soc.c
>> Changed machine name smartfusion2-som->emcraft-sf2
>>
>> v5
>> As per Philippe comments:
>> Added abort in Sysreg if guest tries to remap memory
>> other than default mapping.
>> Use of CONFIG_MSF2 in Makefile for soc.c
>> Fixed incorrect logic in timer model.
>> Renamed msf2-timer.c -> mss-timer.c
>> msf2-spi.c -> mss-spi.c also type names
>> Renamed function msf2_init->emcraft_sf2_init in msf2-som.c
>> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
>> properties to soc.
>> Pass soc part-name,memory size and clock rate properties from
>> som.
>> v4:
>> Fixed build failure by using PRIx macros.
>> v3:
>> Added SoC file and board file as per Alistair comments.
>> v2:
>> Added SPI controller so that u-boot loads kernel from spi flash.
>> v1:
>> Initial patch set with timer and sysreg
>>
>> Thanks,
>> Sundeep
>>
>>
>> Subbaraya Sundeep (5):
>> msf2: Add Smartfusion2 System timer
>> msf2: Microsemi Smartfusion2 System Register block
>> msf2: Add Smartfusion2 SPI controller
>> msf2: Add Smartfusion2 SoC
>> msf2: Add Emcraft's Smartfusion2 SOM kit
>>
>> default-configs/arm-softmmu.mak | 1 +
>> hw/arm/Makefile.objs | 1 +
>> hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++
>> hw/arm/msf2-som.c | 95 ++++++++++
>> hw/misc/Makefile.objs | 1 +
>> hw/misc/msf2-sysreg.c | 195 +++++++++++++++++++
>> hw/ssi/Makefile.objs | 1 +
>> hw/ssi/mss-spi.c | 404 ++++++++++++++++++++++++++++++
>> ++++++++++
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/mss-timer.c | 289 ++++++++++++++++++++++++++++
>> include/hw/arm/msf2-soc.h | 66 +++++++
>> include/hw/misc/msf2-sysreg.h | 78 ++++++++
>> include/hw/ssi/mss-spi.h | 58 ++++++
>> include/hw/timer/mss-timer.h | 64 +++++++
>> 14 files changed, 1472 insertions(+)
>> create mode 100644 hw/arm/msf2-soc.c
>> create mode 100644 hw/arm/msf2-som.c
>> create mode 100644 hw/misc/msf2-sysreg.c
>> create mode 100644 hw/ssi/mss-spi.c
>> create mode 100644 hw/timer/mss-timer.c
>> create mode 100644 include/hw/arm/msf2-soc.h
>> create mode 100644 include/hw/misc/msf2-sysreg.h
>> create mode 100644 include/hw/ssi/mss-spi.h
>> create mode 100644 include/hw/timer/mss-timer.h
>>
>>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC
2017-09-07 21:38 ` Philippe Mathieu-Daudé
@ 2017-09-08 7:26 ` sundeep subbaraya
2017-09-13 9:21 ` sundeep subbaraya
0 siblings, 1 reply; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-08 7:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Fri, Sep 8, 2017 at 3:08 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>
>> Smartfusion2 SoC has hardened Microcontroller subsystem
>> and flash based FPGA fabric. This patch adds support for
>> Microcontroller subsystem in the SoC.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> default-configs/arm-softmmu.mak | 1 +
>> hw/arm/Makefile.objs | 1 +
>> hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++++++++++
>> ++++++++++
>> include/hw/arm/msf2-soc.h | 66 ++++++++++++
>> 4 files changed, 286 insertions(+)
>> create mode 100644 hw/arm/msf2-soc.c
>> create mode 100644 include/hw/arm/msf2-soc.h
>>
>> diff --git a/default-configs/arm-softmmu.mak
>> b/default-configs/arm-softmmu.mak
>> index bbdd3c1..5059d13 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -129,3 +129,4 @@ CONFIG_ACPI=y
>> CONFIG_SMBIOS=y
>> CONFIG_ASPEED_SOC=y
>> CONFIG_GPIO_KEY=y
>> +CONFIG_MSF2=y
>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> index a2e56ec..df36a03 100644
>> --- a/hw/arm/Makefile.objs
>> +++ b/hw/arm/Makefile.objs
>> @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
>> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
>> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
>> obj-$(CONFIG_MPS2) += mps2.o
>> +obj-$(CONFIG_MSF2) += msf2-soc.o
>> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
>> new file mode 100644
>> index 0000000..47fffa4
>> --- /dev/null
>> +++ b/hw/arm/msf2-soc.c
>> @@ -0,0 +1,218 @@
>> +/*
>> + * SmartFusion2 SoC emulation.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "qemu-common.h"
>> +#include "hw/arm/arm.h"
>> +#include "exec/address-spaces.h"
>> +#include "hw/char/serial.h"
>> +#include "hw/boards.h"
>> +#include "sysemu/block-backend.h"
>> +#include "qemu/cutils.h"
>> +#include "hw/arm/msf2-soc.h"
>> +
>> +#define MSF2_TIMER_BASE 0x40004000
>> +#define MSF2_SYSREG_BASE 0x40038000
>> +
>> +#define ENVM_BASE_ADDRESS 0x60000000
>> +
>> +#define SRAM_BASE_ADDRESS 0x20000000
>> +
>> +#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
>> +
>> +/*
>> + * eSRAM max size is 80k without SECDED(Single error correction and
>> + * dual error detection) feature and 64k with SECDED.
>> + * We do not support SECDED now.
>> + */
>> +#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
>> +
>> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 ,
>> 0x40011000 };
>> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 ,
>> 0x40010000 };
>> +
>> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
>> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
>> +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
>> +
>> +static void m2sxxx_soc_initfn(Object *obj)
>> +{
>> + MSF2State *s = MSF2_SOC(obj);
>> + int i;
>> +
>> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
>> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
>> +
>> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
>> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
>> +
>> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
>> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
>> +
>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
>> + TYPE_MSS_SPI);
>> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>> + }
>> +}
>> +
>> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
>> +{
>> + MSF2State *s = MSF2_SOC(dev_soc);
>> + DeviceState *dev, *armv7m;
>> + SysBusDevice *busdev;
>> + Error *err = NULL;
>> + int i;
>> +
>> + MemoryRegion *system_memory = get_system_memory();
>> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
>> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
>> + MemoryRegion *sram = g_new(MemoryRegion, 1);
>> +
>> + memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
>> + &error_fatal);
>> + /*
>> + * On power-on, the eNVM region 0x60000000 is automatically
>> + * remapped to the Cortex-M3 processor executable region
>> + * start address (0x0). We do not support remapping other eNVM,
>> + * eSRAM and DDR regions by guest(via Sysreg) currently.
>> + */
>> + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
>>
>
> you can drop the ".alias", this function already prepends "alias "
.remap sounds good?
Thanks,
Sundeep
>
>
> + nvm, 0, s->envm_size);
>> +
>> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
>> + memory_region_add_subregion(system_memory, 0, nvm_alias);
>> +
>> + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
>> + &error_fatal);
>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
>> +
>> + armv7m = DEVICE(&s->armv7m);
>> + qdev_prop_set_uint32(armv7m, "num-irq", 81);
>> + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
>> + object_property_set_link(OBJECT(&s->armv7m),
>> OBJECT(get_system_memory()),
>> + "memory", &error_abort);
>> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized",
>> &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> +
>> + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
>> +
>> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
>> + if (serial_hds[i]) {
>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
>> + qdev_get_gpio_in(armv7m, uart_irq[i]),
>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
>> + }
>> + }
>> +
>> + dev = DEVICE(&s->timer);
>> + /* APB0 clock is the timer input clock */
>> + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
>> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> + busdev = SYS_BUS_DEVICE(dev);
>> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
>> + sysbus_connect_irq(busdev, 0,
>> + qdev_get_gpio_in(armv7m, timer_irq[0]));
>> + sysbus_connect_irq(busdev, 1,
>> + qdev_get_gpio_in(armv7m, timer_irq[1]));
>> +
>> + dev = DEVICE(&s->sysreg);
>> + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
>> + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
>> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized",
>> &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> + busdev = SYS_BUS_DEVICE(dev);
>> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
>> +
>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>> + gchar *bus_name;
>> +
>> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>> &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> +
>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>> + qdev_get_gpio_in(armv7m, spi_irq[i]));
>> +
>> + /* Alias controller SPI bus to the SoC itself */
>> + bus_name = g_strdup_printf("spi%d", i);
>> + object_property_add_alias(OBJECT(s), bus_name,
>> + OBJECT(&s->spi[i]), "spi",
>> + &error_abort);
>> + g_free(bus_name);
>> + }
>> +}
>> +
>> +static Property m2sxxx_soc_properties[] = {
>> + /*
>> + * part name specifies the type of SmartFusion2 device variant(this
>> + * property is for information purpose only.
>> + */
>> + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
>> + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size,
>> MSF2_ENVM_MAX_SIZE),
>> + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
>> + MSF2_ESRAM_MAX_SIZE),
>> + /* Libero GUI shows 100Mhz as default for clocks */
>> + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
>> + /* default divisors in Libero GUI */
>> + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2),
>> + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->realize = m2sxxx_soc_realize;
>> + dc->props = m2sxxx_soc_properties;
>> +}
>> +
>> +static const TypeInfo m2sxxx_soc_info = {
>> + .name = TYPE_MSF2_SOC,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(MSF2State),
>> + .instance_init = m2sxxx_soc_initfn,
>> + .class_init = m2sxxx_soc_class_init,
>> +};
>> +
>> +static void m2sxxx_soc_types(void)
>> +{
>> + type_register_static(&m2sxxx_soc_info);
>> +}
>> +
>> +type_init(m2sxxx_soc_types)
>> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
>> new file mode 100644
>> index 0000000..eb239fa
>> --- /dev/null
>> +++ b/include/hw/arm/msf2-soc.h
>> @@ -0,0 +1,66 @@
>> +/*
>> + * Microsemi Smartfusion2 SoC
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef HW_ARM_MSF2_SOC_H
>> +#define HW_ARM_MSF2_SOC_H
>> +
>> +#include "hw/arm/armv7m.h"
>> +#include "hw/timer/mss-timer.h"
>> +#include "hw/misc/msf2-sysreg.h"
>> +#include "hw/ssi/mss-spi.h"
>> +
>> +#define TYPE_MSF2_SOC "msf2-soc"
>> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
>> +
>> +#define MSF2_NUM_SPIS 2
>> +#define MSF2_NUM_UARTS 2
>> +
>> +/*
>> + * System timer consists of two programmable 32-bit
>> + * decrementing counters that generate individual interrupts to
>> + * the Cortex-M3 processor
>> + */
>> +#define MSF2_NUM_TIMERS 2
>> +
>> +typedef struct MSF2State {
>> + /*< private >*/
>> + SysBusDevice parent_obj;
>> + /*< public >*/
>> +
>> + ARMv7MState armv7m;
>> +
>> + char *part_name;
>> + uint64_t envm_size;
>> + uint64_t esram_size;
>> +
>> + uint32_t m3clk;
>> + uint32_t apb0div;
>> + uint32_t apb1div;
>> +
>> + MSF2SysregState sysreg;
>> + MSSTimerState timer;
>> + MSSSpiState spi[MSF2_NUM_SPIS];
>> +} MSF2State;
>> +
>> +#endif
>>
>>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
@ 2017-09-12 23:50 ` Alistair Francis
2017-09-13 2:21 ` sundeep subbaraya
0 siblings, 1 reply; 28+ messages in thread
From: Alistair Francis @ 2017-09-12 23:50 UTC (permalink / raw)
To: Subbaraya Sundeep
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
On Thu, Sep 7, 2017 at 12:24 PM, Subbaraya Sundeep
<sundeep.lkml@gmail.com> wrote:
> Modelled Microsemi's Smartfusion2 SPI controller.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Thanks,
Alistair
> ---
> hw/ssi/Makefile.objs | 1 +
> hw/ssi/mss-spi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ssi/mss-spi.h | 58 +++++++
> 3 files changed, 463 insertions(+)
> create mode 100644 hw/ssi/mss-spi.c
> create mode 100644 include/hw/ssi/mss-spi.h
>
> diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
> index 487add2..f5bcc65 100644
> --- a/hw/ssi/Makefile.objs
> +++ b/hw/ssi/Makefile.objs
> @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
> common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
> +common-obj-$(CONFIG_MSF2) += mss-spi.o
>
> obj-$(CONFIG_OMAP) += omap_spi.o
> obj-$(CONFIG_IMX) += imx_spi.o
> diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
> new file mode 100644
> index 0000000..5a8e308
> --- /dev/null
> +++ b/hw/ssi/mss-spi.c
> @@ -0,0 +1,404 @@
> +/*
> + * Block model of SPI controller present in
> + * Microsemi's SmartFusion2 and SmartFusion SoCs.
> + *
> + * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/ssi/mss-spi.h"
> +#include "qemu/log.h"
> +
> +#ifndef MSS_SPI_ERR_DEBUG
> +#define MSS_SPI_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (MSS_SPI_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt "\n", __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +#define FIFO_CAPACITY 32
> +
> +#define R_SPI_CONTROL 0
> +#define R_SPI_DFSIZE 1
> +#define R_SPI_STATUS 2
> +#define R_SPI_INTCLR 3
> +#define R_SPI_RX 4
> +#define R_SPI_TX 5
> +#define R_SPI_CLKGEN 6
> +#define R_SPI_SS 7
> +#define R_SPI_MIS 8
> +#define R_SPI_RIS 9
> +
> +#define S_TXDONE (1 << 0)
> +#define S_RXRDY (1 << 1)
> +#define S_RXCHOVRF (1 << 2)
> +#define S_RXFIFOFUL (1 << 4)
> +#define S_RXFIFOFULNXT (1 << 5)
> +#define S_RXFIFOEMP (1 << 6)
> +#define S_RXFIFOEMPNXT (1 << 7)
> +#define S_TXFIFOFUL (1 << 8)
> +#define S_TXFIFOFULNXT (1 << 9)
> +#define S_TXFIFOEMP (1 << 10)
> +#define S_TXFIFOEMPNXT (1 << 11)
> +#define S_FRAMESTART (1 << 12)
> +#define S_SSEL (1 << 13)
> +#define S_ACTIVE (1 << 14)
> +
> +#define C_ENABLE (1 << 0)
> +#define C_MODE (1 << 1)
> +#define C_INTRXDATA (1 << 4)
> +#define C_INTTXDATA (1 << 5)
> +#define C_INTRXOVRFLO (1 << 6)
> +#define C_SPS (1 << 26)
> +#define C_BIGFIFO (1 << 29)
> +#define C_RESET (1 << 31)
> +
> +#define FRAMESZ_MASK 0x1F
> +#define FMCOUNT_MASK 0x00FFFF00
> +#define FMCOUNT_SHIFT 8
> +
> +static void txfifo_reset(MSSSpiState *s)
> +{
> + fifo32_reset(&s->tx_fifo);
> +
> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
> + s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
> +}
> +
> +static void rxfifo_reset(MSSSpiState *s)
> +{
> + fifo32_reset(&s->rx_fifo);
> +
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> +}
> +
> +static void set_fifodepth(MSSSpiState *s)
> +{
> + unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
> +
> + if (size <= 8) {
> + s->fifo_depth = 32;
> + } else if (size <= 16) {
> + s->fifo_depth = 16;
> + } else if (size <= 32) {
> + s->fifo_depth = 8;
> + } else {
> + s->fifo_depth = 4;
> + }
> +}
> +
> +static void update_mis(MSSSpiState *s)
> +{
> + uint32_t reg = s->regs[R_SPI_CONTROL];
> + uint32_t tmp;
> +
> + /*
> + * form the Control register interrupt enable bits
> + * same as RIS, MIS and Interrupt clear registers for simplicity
> + */
> + tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
> + ((reg & C_INTTXDATA) >> 5);
> + s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
> +}
> +
> +static void spi_update_irq(MSSSpiState *s)
> +{
> + int irq;
> +
> + update_mis(s);
> + irq = !!(s->regs[R_SPI_MIS]);
> +
> + qemu_set_irq(s->irq, irq);
> +}
> +
> +static void mss_spi_reset(DeviceState *d)
> +{
> + MSSSpiState *s = MSS_SPI(d);
> +
> + memset(s->regs, 0, sizeof s->regs);
> + s->regs[R_SPI_CONTROL] = 0x80000102;
> + s->regs[R_SPI_DFSIZE] = 0x4;
> + s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
> + s->regs[R_SPI_CLKGEN] = 0x7;
> + s->regs[R_SPI_RIS] = 0x0;
> +
> + s->fifo_depth = 4;
> + s->frame_count = 1;
> + s->enabled = false;
> +
> + rxfifo_reset(s);
> + txfifo_reset(s);
> +}
> +
> +static uint64_t
> +spi_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + MSSSpiState *s = opaque;
> + uint32_t ret = 0;
> +
> + addr >>= 2;
> + switch (addr) {
> + case R_SPI_RX:
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> + s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
> + ret = fifo32_pop(&s->rx_fifo);
> + if (fifo32_is_empty(&s->rx_fifo)) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> + }
> + break;
> +
> + case R_SPI_MIS:
> + update_mis(s);
> + ret = s->regs[R_SPI_MIS];
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(s->regs)) {
> + ret = s->regs[addr];
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
> + addr * 4);
> + return ret;
> + }
> + break;
> + }
> +
> + DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
> + spi_update_irq(s);
> + return ret;
> +}
> +
> +static void assert_cs(MSSSpiState *s)
> +{
> + qemu_set_irq(s->cs_line, 0);
> +}
> +
> +static void deassert_cs(MSSSpiState *s)
> +{
> + qemu_set_irq(s->cs_line, 1);
> +}
> +
> +static void spi_flush_txfifo(MSSSpiState *s)
> +{
> + uint32_t tx;
> + uint32_t rx;
> + bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
> +
> + /*
> + * Chip Select(CS) is automatically controlled by this controller.
> + * If SPS bit is set in Control register then CS is asserted
> + * until all the frames set in frame count of Control register are
> + * transferred. If SPS is not set then CS pulses between frames.
> + * Note that Slave Select register specifies which of the CS line
> + * has to be controlled automatically by controller. Bits SS[7:1] are for
> + * masters in FPGA fabric since we model only Microcontroller subsystem
> + * of Smartfusion2 we control only one CS(SS[0]) line.
> + */
> + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
> + assert_cs(s);
> +
> + s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
> +
> + tx = fifo32_pop(&s->tx_fifo);
> + DB_PRINT("data tx:0x%" PRIx32, tx);
> + rx = ssi_transfer(s->spi, tx);
> + DB_PRINT("data rx:0x%" PRIx32, rx);
> +
> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
> + s->regs[R_SPI_RIS] |= S_RXCHOVRF;
> + } else {
> + fifo32_push(&s->rx_fifo, rx);
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
> + if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
> + } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
> + }
> + }
> + s->frame_count--;
> + if (!sps) {
> + deassert_cs(s);
> + }
> + }
> +
> + if (!s->frame_count) {
> + s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
> + FMCOUNT_SHIFT;
> + deassert_cs(s);
> + s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
> + s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
> + }
> +}
> +
> +static void spi_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + MSSSpiState *s = opaque;
> + uint32_t value = val64;
> +
> + DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
> + addr >>= 2;
> +
> + switch (addr) {
> + case R_SPI_TX:
> + /* adding to already full FIFO */
> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> + break;
> + }
> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
> + fifo32_push(&s->tx_fifo, value);
> + if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
> + s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
> + } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
> + }
> + if (s->enabled) {
> + spi_flush_txfifo(s);
> + }
> + break;
> +
> + case R_SPI_CONTROL:
> + s->regs[R_SPI_CONTROL] = value;
> + if (value & C_BIGFIFO) {
> + set_fifodepth(s);
> + } else {
> + s->fifo_depth = 4;
> + }
> + s->enabled = value & C_ENABLE;
> + s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
> + if (value & C_RESET) {
> + mss_spi_reset(DEVICE(s));
> + }
> + break;
> +
> + case R_SPI_DFSIZE:
> + if (s->enabled) {
> + break;
> + }
> + s->regs[R_SPI_DFSIZE] = value;
> + break;
> +
> + case R_SPI_INTCLR:
> + s->regs[R_SPI_INTCLR] = value;
> + if (value & S_TXDONE) {
> + s->regs[R_SPI_RIS] &= ~S_TXDONE;
> + }
> + if (value & S_RXRDY) {
> + s->regs[R_SPI_RIS] &= ~S_RXRDY;
> + }
> + if (value & S_RXCHOVRF) {
> + s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
> + }
> + break;
> +
> + case R_SPI_MIS:
> + case R_SPI_STATUS:
> + case R_SPI_RIS:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Write to read only register 0x%" HWADDR_PRIx "\n",
> + __func__, addr * 4);
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(s->regs)) {
> + s->regs[addr] = value;
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
> + addr * 4);
> + }
> + break;
> + }
> +
> + spi_update_irq(s);
> +}
> +
> +static const MemoryRegionOps spi_ops = {
> + .read = spi_read,
> + .write = spi_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4
> + }
> +};
> +
> +static void mss_spi_realize(DeviceState *dev, Error **errp)
> +{
> + MSSSpiState *s = MSS_SPI(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + s->spi = ssi_create_bus(dev, "spi");
> +
> + sysbus_init_irq(sbd, &s->irq);
> + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
> + sysbus_init_irq(sbd, &s->cs_line);
> +
> + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
> + TYPE_MSS_SPI, R_SPI_MAX * 4);
> + sysbus_init_mmio(sbd, &s->mmio);
> +
> + fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
> + fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
> +}
> +
> +static const VMStateDescription vmstate_mss_spi = {
> + .name = TYPE_MSS_SPI,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_FIFO32(tx_fifo, MSSSpiState),
> + VMSTATE_FIFO32(rx_fifo, MSSSpiState),
> + VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void mss_spi_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = mss_spi_realize;
> + dc->reset = mss_spi_reset;
> + dc->vmsd = &vmstate_mss_spi;
> +}
> +
> +static const TypeInfo mss_spi_info = {
> + .name = TYPE_MSS_SPI,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSSSpiState),
> + .class_init = mss_spi_class_init,
> +};
> +
> +static void mss_spi_register_types(void)
> +{
> + type_register_static(&mss_spi_info);
> +}
> +
> +type_init(mss_spi_register_types)
> diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
> new file mode 100644
> index 0000000..f0cf324
> --- /dev/null
> +++ b/include/hw/ssi/mss-spi.h
> @@ -0,0 +1,58 @@
> +/*
> + * Microsemi SmartFusion2 SPI
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MSS_SPI_H
> +#define HW_MSS_SPI_H
> +
> +#include "hw/sysbus.h"
> +#include "hw/ssi/ssi.h"
> +#include "qemu/fifo32.h"
> +
> +#define TYPE_MSS_SPI "mss-spi"
> +#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
> +
> +#define R_SPI_MAX 16
> +
> +typedef struct MSSSpiState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion mmio;
> +
> + qemu_irq irq;
> +
> + qemu_irq cs_line;
> +
> + SSIBus *spi;
> +
> + Fifo32 rx_fifo;
> + Fifo32 tx_fifo;
> +
> + int fifo_depth;
> + uint32_t frame_count;
> + bool enabled;
> +
> + uint32_t regs[R_SPI_MAX];
> +} MSSSpiState;
> +
> +#endif /* HW_MSS_SPI_H */
> --
> 2.5.0
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
2017-09-12 23:50 ` Alistair Francis
@ 2017-09-13 2:21 ` sundeep subbaraya
0 siblings, 0 replies; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-13 2:21 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
Hi Alistair,
On Wed, Sep 13, 2017 at 5:20 AM, Alistair Francis <alistair23@gmail.com>
wrote:
> On Thu, Sep 7, 2017 at 12:24 PM, Subbaraya Sundeep
> <sundeep.lkml@gmail.com> wrote:
> > Modelled Microsemi's Smartfusion2 SPI controller.
> >
> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
>
> Thank you,
Sundeep
> Thanks,
> Alistair
>
> > ---
> > hw/ssi/Makefile.objs | 1 +
> > hw/ssi/mss-spi.c | 404 ++++++++++++++++++++++++++++++
> +++++++++++++++++
> > include/hw/ssi/mss-spi.h | 58 +++++++
> > 3 files changed, 463 insertions(+)
> > create mode 100644 hw/ssi/mss-spi.c
> > create mode 100644 include/hw/ssi/mss-spi.h
> >
> > diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
> > index 487add2..f5bcc65 100644
> > --- a/hw/ssi/Makefile.objs
> > +++ b/hw/ssi/Makefile.objs
> > @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> > common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
> > common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
> > common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
> > +common-obj-$(CONFIG_MSF2) += mss-spi.o
> >
> > obj-$(CONFIG_OMAP) += omap_spi.o
> > obj-$(CONFIG_IMX) += imx_spi.o
> > diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
> > new file mode 100644
> > index 0000000..5a8e308
> > --- /dev/null
> > +++ b/hw/ssi/mss-spi.c
> > @@ -0,0 +1,404 @@
> > +/*
> > + * Block model of SPI controller present in
> > + * Microsemi's SmartFusion2 and SmartFusion SoCs.
> > + *
> > + * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> > + * of this software and associated documentation files (the
> "Software"), to deal
> > + * in the Software without restriction, including without limitation
> the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> > + * copies of the Software, and to permit persons to whom the Software is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/ssi/mss-spi.h"
> > +#include "qemu/log.h"
> > +
> > +#ifndef MSS_SPI_ERR_DEBUG
> > +#define MSS_SPI_ERR_DEBUG 0
> > +#endif
> > +
> > +#define DB_PRINT_L(lvl, fmt, args...) do { \
> > + if (MSS_SPI_ERR_DEBUG >= lvl) { \
> > + qemu_log("%s: " fmt "\n", __func__, ## args); \
> > + } \
> > +} while (0);
> > +
> > +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> > +
> > +#define FIFO_CAPACITY 32
> > +
> > +#define R_SPI_CONTROL 0
> > +#define R_SPI_DFSIZE 1
> > +#define R_SPI_STATUS 2
> > +#define R_SPI_INTCLR 3
> > +#define R_SPI_RX 4
> > +#define R_SPI_TX 5
> > +#define R_SPI_CLKGEN 6
> > +#define R_SPI_SS 7
> > +#define R_SPI_MIS 8
> > +#define R_SPI_RIS 9
> > +
> > +#define S_TXDONE (1 << 0)
> > +#define S_RXRDY (1 << 1)
> > +#define S_RXCHOVRF (1 << 2)
> > +#define S_RXFIFOFUL (1 << 4)
> > +#define S_RXFIFOFULNXT (1 << 5)
> > +#define S_RXFIFOEMP (1 << 6)
> > +#define S_RXFIFOEMPNXT (1 << 7)
> > +#define S_TXFIFOFUL (1 << 8)
> > +#define S_TXFIFOFULNXT (1 << 9)
> > +#define S_TXFIFOEMP (1 << 10)
> > +#define S_TXFIFOEMPNXT (1 << 11)
> > +#define S_FRAMESTART (1 << 12)
> > +#define S_SSEL (1 << 13)
> > +#define S_ACTIVE (1 << 14)
> > +
> > +#define C_ENABLE (1 << 0)
> > +#define C_MODE (1 << 1)
> > +#define C_INTRXDATA (1 << 4)
> > +#define C_INTTXDATA (1 << 5)
> > +#define C_INTRXOVRFLO (1 << 6)
> > +#define C_SPS (1 << 26)
> > +#define C_BIGFIFO (1 << 29)
> > +#define C_RESET (1 << 31)
> > +
> > +#define FRAMESZ_MASK 0x1F
> > +#define FMCOUNT_MASK 0x00FFFF00
> > +#define FMCOUNT_SHIFT 8
> > +
> > +static void txfifo_reset(MSSSpiState *s)
> > +{
> > + fifo32_reset(&s->tx_fifo);
> > +
> > + s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
> > + s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
> > +}
> > +
> > +static void rxfifo_reset(MSSSpiState *s)
> > +{
> > + fifo32_reset(&s->rx_fifo);
> > +
> > + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> > + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> > +}
> > +
> > +static void set_fifodepth(MSSSpiState *s)
> > +{
> > + unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
> > +
> > + if (size <= 8) {
> > + s->fifo_depth = 32;
> > + } else if (size <= 16) {
> > + s->fifo_depth = 16;
> > + } else if (size <= 32) {
> > + s->fifo_depth = 8;
> > + } else {
> > + s->fifo_depth = 4;
> > + }
> > +}
> > +
> > +static void update_mis(MSSSpiState *s)
> > +{
> > + uint32_t reg = s->regs[R_SPI_CONTROL];
> > + uint32_t tmp;
> > +
> > + /*
> > + * form the Control register interrupt enable bits
> > + * same as RIS, MIS and Interrupt clear registers for simplicity
> > + */
> > + tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
> > + ((reg & C_INTTXDATA) >> 5);
> > + s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
> > +}
> > +
> > +static void spi_update_irq(MSSSpiState *s)
> > +{
> > + int irq;
> > +
> > + update_mis(s);
> > + irq = !!(s->regs[R_SPI_MIS]);
> > +
> > + qemu_set_irq(s->irq, irq);
> > +}
> > +
> > +static void mss_spi_reset(DeviceState *d)
> > +{
> > + MSSSpiState *s = MSS_SPI(d);
> > +
> > + memset(s->regs, 0, sizeof s->regs);
> > + s->regs[R_SPI_CONTROL] = 0x80000102;
> > + s->regs[R_SPI_DFSIZE] = 0x4;
> > + s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
> > + s->regs[R_SPI_CLKGEN] = 0x7;
> > + s->regs[R_SPI_RIS] = 0x0;
> > +
> > + s->fifo_depth = 4;
> > + s->frame_count = 1;
> > + s->enabled = false;
> > +
> > + rxfifo_reset(s);
> > + txfifo_reset(s);
> > +}
> > +
> > +static uint64_t
> > +spi_read(void *opaque, hwaddr addr, unsigned int size)
> > +{
> > + MSSSpiState *s = opaque;
> > + uint32_t ret = 0;
> > +
> > + addr >>= 2;
> > + switch (addr) {
> > + case R_SPI_RX:
> > + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> > + s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
> > + ret = fifo32_pop(&s->rx_fifo);
> > + if (fifo32_is_empty(&s->rx_fifo)) {
> > + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> > + }
> > + break;
> > +
> > + case R_SPI_MIS:
> > + update_mis(s);
> > + ret = s->regs[R_SPI_MIS];
> > + break;
> > +
> > + default:
> > + if (addr < ARRAY_SIZE(s->regs)) {
> > + ret = s->regs[addr];
> > + } else {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: Bad offset 0x%" HWADDR_PRIx "\n",
> __func__,
> > + addr * 4);
> > + return ret;
> > + }
> > + break;
> > + }
> > +
> > + DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
> > + spi_update_irq(s);
> > + return ret;
> > +}
> > +
> > +static void assert_cs(MSSSpiState *s)
> > +{
> > + qemu_set_irq(s->cs_line, 0);
> > +}
> > +
> > +static void deassert_cs(MSSSpiState *s)
> > +{
> > + qemu_set_irq(s->cs_line, 1);
> > +}
> > +
> > +static void spi_flush_txfifo(MSSSpiState *s)
> > +{
> > + uint32_t tx;
> > + uint32_t rx;
> > + bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
> > +
> > + /*
> > + * Chip Select(CS) is automatically controlled by this controller.
> > + * If SPS bit is set in Control register then CS is asserted
> > + * until all the frames set in frame count of Control register are
> > + * transferred. If SPS is not set then CS pulses between frames.
> > + * Note that Slave Select register specifies which of the CS line
> > + * has to be controlled automatically by controller. Bits SS[7:1]
> are for
> > + * masters in FPGA fabric since we model only Microcontroller
> subsystem
> > + * of Smartfusion2 we control only one CS(SS[0]) line.
> > + */
> > + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
> > + assert_cs(s);
> > +
> > + s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
> > +
> > + tx = fifo32_pop(&s->tx_fifo);
> > + DB_PRINT("data tx:0x%" PRIx32, tx);
> > + rx = ssi_transfer(s->spi, tx);
> > + DB_PRINT("data rx:0x%" PRIx32, rx);
> > +
> > + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> > + s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
> > + s->regs[R_SPI_RIS] |= S_RXCHOVRF;
> > + } else {
> > + fifo32_push(&s->rx_fifo, rx);
> > + s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
> > + if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
> > + s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
> > + } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> > + s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
> > + }
> > + }
> > + s->frame_count--;
> > + if (!sps) {
> > + deassert_cs(s);
> > + }
> > + }
> > +
> > + if (!s->frame_count) {
> > + s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
> > + FMCOUNT_SHIFT;
> > + deassert_cs(s);
> > + s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
> > + s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
> > + }
> > +}
> > +
> > +static void spi_write(void *opaque, hwaddr addr,
> > + uint64_t val64, unsigned int size)
> > +{
> > + MSSSpiState *s = opaque;
> > + uint32_t value = val64;
> > +
> > + DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
> > + addr >>= 2;
> > +
> > + switch (addr) {
> > + case R_SPI_TX:
> > + /* adding to already full FIFO */
> > + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> > + break;
> > + }
> > + s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
> > + fifo32_push(&s->tx_fifo, value);
> > + if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
> > + s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
> > + } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> > + s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
> > + }
> > + if (s->enabled) {
> > + spi_flush_txfifo(s);
> > + }
> > + break;
> > +
> > + case R_SPI_CONTROL:
> > + s->regs[R_SPI_CONTROL] = value;
> > + if (value & C_BIGFIFO) {
> > + set_fifodepth(s);
> > + } else {
> > + s->fifo_depth = 4;
> > + }
> > + s->enabled = value & C_ENABLE;
> > + s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
> > + if (value & C_RESET) {
> > + mss_spi_reset(DEVICE(s));
> > + }
> > + break;
> > +
> > + case R_SPI_DFSIZE:
> > + if (s->enabled) {
> > + break;
> > + }
> > + s->regs[R_SPI_DFSIZE] = value;
> > + break;
> > +
> > + case R_SPI_INTCLR:
> > + s->regs[R_SPI_INTCLR] = value;
> > + if (value & S_TXDONE) {
> > + s->regs[R_SPI_RIS] &= ~S_TXDONE;
> > + }
> > + if (value & S_RXRDY) {
> > + s->regs[R_SPI_RIS] &= ~S_RXRDY;
> > + }
> > + if (value & S_RXCHOVRF) {
> > + s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
> > + }
> > + break;
> > +
> > + case R_SPI_MIS:
> > + case R_SPI_STATUS:
> > + case R_SPI_RIS:
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: Write to read only register 0x%"
> HWADDR_PRIx "\n",
> > + __func__, addr * 4);
> > + break;
> > +
> > + default:
> > + if (addr < ARRAY_SIZE(s->regs)) {
> > + s->regs[addr] = value;
> > + } else {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: Bad offset 0x%" HWADDR_PRIx "\n",
> __func__,
> > + addr * 4);
> > + }
> > + break;
> > + }
> > +
> > + spi_update_irq(s);
> > +}
> > +
> > +static const MemoryRegionOps spi_ops = {
> > + .read = spi_read,
> > + .write = spi_write,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 1,
> > + .max_access_size = 4
> > + }
> > +};
> > +
> > +static void mss_spi_realize(DeviceState *dev, Error **errp)
> > +{
> > + MSSSpiState *s = MSS_SPI(dev);
> > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> > +
> > + s->spi = ssi_create_bus(dev, "spi");
> > +
> > + sysbus_init_irq(sbd, &s->irq);
> > + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
> > + sysbus_init_irq(sbd, &s->cs_line);
> > +
> > + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
> > + TYPE_MSS_SPI, R_SPI_MAX * 4);
> > + sysbus_init_mmio(sbd, &s->mmio);
> > +
> > + fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
> > + fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
> > +}
> > +
> > +static const VMStateDescription vmstate_mss_spi = {
> > + .name = TYPE_MSS_SPI,
> > + .version_id = 1,
> > + .minimum_version_id = 1,
> > + .fields = (VMStateField[]) {
> > + VMSTATE_FIFO32(tx_fifo, MSSSpiState),
> > + VMSTATE_FIFO32(rx_fifo, MSSSpiState),
> > + VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
> > + VMSTATE_END_OF_LIST()
> > + }
> > +};
> > +
> > +static void mss_spi_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
> > + dc->realize = mss_spi_realize;
> > + dc->reset = mss_spi_reset;
> > + dc->vmsd = &vmstate_mss_spi;
> > +}
> > +
> > +static const TypeInfo mss_spi_info = {
> > + .name = TYPE_MSS_SPI,
> > + .parent = TYPE_SYS_BUS_DEVICE,
> > + .instance_size = sizeof(MSSSpiState),
> > + .class_init = mss_spi_class_init,
> > +};
> > +
> > +static void mss_spi_register_types(void)
> > +{
> > + type_register_static(&mss_spi_info);
> > +}
> > +
> > +type_init(mss_spi_register_types)
> > diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
> > new file mode 100644
> > index 0000000..f0cf324
> > --- /dev/null
> > +++ b/include/hw/ssi/mss-spi.h
> > @@ -0,0 +1,58 @@
> > +/*
> > + * Microsemi SmartFusion2 SPI
> > + *
> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> > + * of this software and associated documentation files (the
> "Software"), to deal
> > + * in the Software without restriction, including without limitation
> the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> > + * copies of the Software, and to permit persons to whom the Software is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#ifndef HW_MSS_SPI_H
> > +#define HW_MSS_SPI_H
> > +
> > +#include "hw/sysbus.h"
> > +#include "hw/ssi/ssi.h"
> > +#include "qemu/fifo32.h"
> > +
> > +#define TYPE_MSS_SPI "mss-spi"
> > +#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
> > +
> > +#define R_SPI_MAX 16
> > +
> > +typedef struct MSSSpiState {
> > + SysBusDevice parent_obj;
> > +
> > + MemoryRegion mmio;
> > +
> > + qemu_irq irq;
> > +
> > + qemu_irq cs_line;
> > +
> > + SSIBus *spi;
> > +
> > + Fifo32 rx_fifo;
> > + Fifo32 tx_fifo;
> > +
> > + int fifo_depth;
> > + uint32_t frame_count;
> > + bool enabled;
> > +
> > + uint32_t regs[R_SPI_MAX];
> > +} MSSSpiState;
> > +
> > +#endif /* HW_MSS_SPI_H */
> > --
> > 2.5.0
> >
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC
2017-09-08 7:26 ` sundeep subbaraya
@ 2017-09-13 9:21 ` sundeep subbaraya
2017-09-13 17:07 ` sundeep subbaraya
2017-09-13 17:24 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-13 9:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
All patches got Reviewed-by. Do you want me to change alias to remap and
send
v9 or wait so that you get time to review?
Thanks,
Sundeep
On Fri, Sep 8, 2017 at 12:56 PM, sundeep subbaraya <sundeep.lkml@gmail.com>
wrote:
> Hi Philippe,
>
> On Fri, Sep 8, 2017 at 3:08 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
> wrote:
>
>> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>>
>>> Smartfusion2 SoC has hardened Microcontroller subsystem
>>> and flash based FPGA fabric. This patch adds support for
>>> Microcontroller subsystem in the SoC.
>>>
>>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
>>> ---
>>> default-configs/arm-softmmu.mak | 1 +
>>> hw/arm/Makefile.objs | 1 +
>>> hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++++++++++
>>> ++++++++++
>>> include/hw/arm/msf2-soc.h | 66 ++++++++++++
>>> 4 files changed, 286 insertions(+)
>>> create mode 100644 hw/arm/msf2-soc.c
>>> create mode 100644 include/hw/arm/msf2-soc.h
>>>
>>> diff --git a/default-configs/arm-softmmu.mak
>>> b/default-configs/arm-softmmu.mak
>>> index bbdd3c1..5059d13 100644
>>> --- a/default-configs/arm-softmmu.mak
>>> +++ b/default-configs/arm-softmmu.mak
>>> @@ -129,3 +129,4 @@ CONFIG_ACPI=y
>>> CONFIG_SMBIOS=y
>>> CONFIG_ASPEED_SOC=y
>>> CONFIG_GPIO_KEY=y
>>> +CONFIG_MSF2=y
>>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>>> index a2e56ec..df36a03 100644
>>> --- a/hw/arm/Makefile.objs
>>> +++ b/hw/arm/Makefile.objs
>>> @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
>>> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
>>> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
>>> obj-$(CONFIG_MPS2) += mps2.o
>>> +obj-$(CONFIG_MSF2) += msf2-soc.o
>>> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
>>> new file mode 100644
>>> index 0000000..47fffa4
>>> --- /dev/null
>>> +++ b/hw/arm/msf2-soc.c
>>> @@ -0,0 +1,218 @@
>>> +/*
>>> + * SmartFusion2 SoC emulation.
>>> + *
>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person
>>> obtaining a copy
>>> + * of this software and associated documentation files (the
>>> "Software"), to deal
>>> + * in the Software without restriction, including without limitation
>>> the rights
>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>>> sell
>>> + * copies of the Software, and to permit persons to whom the Software is
>>> + * furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>>> SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>> OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>> ARISING FROM,
>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>>> DEALINGS IN
>>> + * THE SOFTWARE.
>>> + */
>>> +
>>> +#include "qemu/osdep.h"
>>> +#include "qapi/error.h"
>>> +#include "qemu-common.h"
>>> +#include "hw/arm/arm.h"
>>> +#include "exec/address-spaces.h"
>>> +#include "hw/char/serial.h"
>>> +#include "hw/boards.h"
>>> +#include "sysemu/block-backend.h"
>>> +#include "qemu/cutils.h"
>>> +#include "hw/arm/msf2-soc.h"
>>> +
>>> +#define MSF2_TIMER_BASE 0x40004000
>>> +#define MSF2_SYSREG_BASE 0x40038000
>>> +
>>> +#define ENVM_BASE_ADDRESS 0x60000000
>>> +
>>> +#define SRAM_BASE_ADDRESS 0x20000000
>>> +
>>> +#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
>>> +
>>> +/*
>>> + * eSRAM max size is 80k without SECDED(Single error correction and
>>> + * dual error detection) feature and 64k with SECDED.
>>> + * We do not support SECDED now.
>>> + */
>>> +#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
>>> +
>>> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 ,
>>> 0x40011000 };
>>> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 ,
>>> 0x40010000 };
>>> +
>>> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
>>> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
>>> +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
>>> +
>>> +static void m2sxxx_soc_initfn(Object *obj)
>>> +{
>>> + MSF2State *s = MSF2_SOC(obj);
>>> + int i;
>>> +
>>> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
>>> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
>>> +
>>> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
>>> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
>>> +
>>> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
>>> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
>>> +
>>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>>> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>> + TYPE_MSS_SPI);
>>> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>> + }
>>> +}
>>> +
>>> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
>>> +{
>>> + MSF2State *s = MSF2_SOC(dev_soc);
>>> + DeviceState *dev, *armv7m;
>>> + SysBusDevice *busdev;
>>> + Error *err = NULL;
>>> + int i;
>>> +
>>> + MemoryRegion *system_memory = get_system_memory();
>>> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
>>> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
>>> + MemoryRegion *sram = g_new(MemoryRegion, 1);
>>> +
>>> + memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
>>> + &error_fatal);
>>> + /*
>>> + * On power-on, the eNVM region 0x60000000 is automatically
>>> + * remapped to the Cortex-M3 processor executable region
>>> + * start address (0x0). We do not support remapping other eNVM,
>>> + * eSRAM and DDR regions by guest(via Sysreg) currently.
>>> + */
>>> + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
>>>
>>
>> you can drop the ".alias", this function already prepends "alias "
>
>
> .remap sounds good?
>
> Thanks,
> Sundeep
>
>>
>>
>> + nvm, 0, s->envm_size);
>>> +
>>> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
>>> + memory_region_add_subregion(system_memory, 0, nvm_alias);
>>> +
>>> + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
>>> + &error_fatal);
>>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS,
>>> sram);
>>> +
>>> + armv7m = DEVICE(&s->armv7m);
>>> + qdev_prop_set_uint32(armv7m, "num-irq", 81);
>>> + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
>>> + object_property_set_link(OBJECT(&s->armv7m),
>>> OBJECT(get_system_memory()),
>>> + "memory", &error_abort);
>>> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized",
>>> &err);
>>> + if (err != NULL) {
>>> + error_propagate(errp, err);
>>> + return;
>>> + }
>>> +
>>> + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
>>> +
>>> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
>>> + if (serial_hds[i]) {
>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
>>> + qdev_get_gpio_in(armv7m, uart_irq[i]),
>>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
>>> + }
>>> + }
>>> +
>>> + dev = DEVICE(&s->timer);
>>> + /* APB0 clock is the timer input clock */
>>> + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
>>> + object_property_set_bool(OBJECT(&s->timer), true, "realized",
>>> &err);
>>> + if (err != NULL) {
>>> + error_propagate(errp, err);
>>> + return;
>>> + }
>>> + busdev = SYS_BUS_DEVICE(dev);
>>> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
>>> + sysbus_connect_irq(busdev, 0,
>>> + qdev_get_gpio_in(armv7m, timer_irq[0]));
>>> + sysbus_connect_irq(busdev, 1,
>>> + qdev_get_gpio_in(armv7m, timer_irq[1]));
>>> +
>>> + dev = DEVICE(&s->sysreg);
>>> + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
>>> + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
>>> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized",
>>> &err);
>>> + if (err != NULL) {
>>> + error_propagate(errp, err);
>>> + return;
>>> + }
>>> + busdev = SYS_BUS_DEVICE(dev);
>>> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
>>> +
>>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>>> + gchar *bus_name;
>>> +
>>> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>>> &err);
>>> + if (err != NULL) {
>>> + error_propagate(errp, err);
>>> + return;
>>> + }
>>> +
>>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>> + qdev_get_gpio_in(armv7m, spi_irq[i]));
>>> +
>>> + /* Alias controller SPI bus to the SoC itself */
>>> + bus_name = g_strdup_printf("spi%d", i);
>>> + object_property_add_alias(OBJECT(s), bus_name,
>>> + OBJECT(&s->spi[i]), "spi",
>>> + &error_abort);
>>> + g_free(bus_name);
>>> + }
>>> +}
>>> +
>>> +static Property m2sxxx_soc_properties[] = {
>>> + /*
>>> + * part name specifies the type of SmartFusion2 device variant(this
>>> + * property is for information purpose only.
>>> + */
>>> + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
>>> + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size,
>>> MSF2_ENVM_MAX_SIZE),
>>> + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
>>> + MSF2_ESRAM_MAX_SIZE),
>>> + /* Libero GUI shows 100Mhz as default for clocks */
>>> + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
>>> + /* default divisors in Libero GUI */
>>> + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2),
>>> + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2),
>>> + DEFINE_PROP_END_OF_LIST(),
>>> +};
>>> +
>>> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
>>> +{
>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>> +
>>> + dc->realize = m2sxxx_soc_realize;
>>> + dc->props = m2sxxx_soc_properties;
>>> +}
>>> +
>>> +static const TypeInfo m2sxxx_soc_info = {
>>> + .name = TYPE_MSF2_SOC,
>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>> + .instance_size = sizeof(MSF2State),
>>> + .instance_init = m2sxxx_soc_initfn,
>>> + .class_init = m2sxxx_soc_class_init,
>>> +};
>>> +
>>> +static void m2sxxx_soc_types(void)
>>> +{
>>> + type_register_static(&m2sxxx_soc_info);
>>> +}
>>> +
>>> +type_init(m2sxxx_soc_types)
>>> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
>>> new file mode 100644
>>> index 0000000..eb239fa
>>> --- /dev/null
>>> +++ b/include/hw/arm/msf2-soc.h
>>> @@ -0,0 +1,66 @@
>>> +/*
>>> + * Microsemi Smartfusion2 SoC
>>> + *
>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person
>>> obtaining a copy
>>> + * of this software and associated documentation files (the
>>> "Software"), to deal
>>> + * in the Software without restriction, including without limitation
>>> the rights
>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>>> sell
>>> + * copies of the Software, and to permit persons to whom the Software is
>>> + * furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>>> SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>> OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>> ARISING FROM,
>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>>> DEALINGS IN
>>> + * THE SOFTWARE.
>>> + */
>>> +
>>> +#ifndef HW_ARM_MSF2_SOC_H
>>> +#define HW_ARM_MSF2_SOC_H
>>> +
>>> +#include "hw/arm/armv7m.h"
>>> +#include "hw/timer/mss-timer.h"
>>> +#include "hw/misc/msf2-sysreg.h"
>>> +#include "hw/ssi/mss-spi.h"
>>> +
>>> +#define TYPE_MSF2_SOC "msf2-soc"
>>> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
>>> +
>>> +#define MSF2_NUM_SPIS 2
>>> +#define MSF2_NUM_UARTS 2
>>> +
>>> +/*
>>> + * System timer consists of two programmable 32-bit
>>> + * decrementing counters that generate individual interrupts to
>>> + * the Cortex-M3 processor
>>> + */
>>> +#define MSF2_NUM_TIMERS 2
>>> +
>>> +typedef struct MSF2State {
>>> + /*< private >*/
>>> + SysBusDevice parent_obj;
>>> + /*< public >*/
>>> +
>>> + ARMv7MState armv7m;
>>> +
>>> + char *part_name;
>>> + uint64_t envm_size;
>>> + uint64_t esram_size;
>>> +
>>> + uint32_t m3clk;
>>> + uint32_t apb0div;
>>> + uint32_t apb1div;
>>> +
>>> + MSF2SysregState sysreg;
>>> + MSSTimerState timer;
>>> + MSSSpiState spi[MSF2_NUM_SPIS];
>>> +} MSF2State;
>>> +
>>> +#endif
>>>
>>>
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC
2017-09-13 9:21 ` sundeep subbaraya
@ 2017-09-13 17:07 ` sundeep subbaraya
2017-09-13 17:24 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-13 17:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Wed, Sep 13, 2017 at 2:51 PM, sundeep subbaraya <sundeep.lkml@gmail.com>
wrote:
> Hi Philippe,
>
> All patches got Reviewed-by. Do you want me to change alias to remap and
> send
> v9 or wait so that you get time to review?
>
> Sorry. My bad, I overlooked your comment. I will just drop alias and send
v9.
Thanks,
Sundeep
> Thanks,
> Sundeep
>
> On Fri, Sep 8, 2017 at 12:56 PM, sundeep subbaraya <sundeep.lkml@gmail.com
> > wrote:
>
>> Hi Philippe,
>>
>> On Fri, Sep 8, 2017 at 3:08 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
>> wrote:
>>
>>> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>>>
>>>> Smartfusion2 SoC has hardened Microcontroller subsystem
>>>> and flash based FPGA fabric. This patch adds support for
>>>> Microcontroller subsystem in the SoC.
>>>>
>>>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>>> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
>>>> ---
>>>> default-configs/arm-softmmu.mak | 1 +
>>>> hw/arm/Makefile.objs | 1 +
>>>> hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++++++++++
>>>> ++++++++++
>>>> include/hw/arm/msf2-soc.h | 66 ++++++++++++
>>>> 4 files changed, 286 insertions(+)
>>>> create mode 100644 hw/arm/msf2-soc.c
>>>> create mode 100644 include/hw/arm/msf2-soc.h
>>>>
>>>> diff --git a/default-configs/arm-softmmu.mak
>>>> b/default-configs/arm-softmmu.mak
>>>> index bbdd3c1..5059d13 100644
>>>> --- a/default-configs/arm-softmmu.mak
>>>> +++ b/default-configs/arm-softmmu.mak
>>>> @@ -129,3 +129,4 @@ CONFIG_ACPI=y
>>>> CONFIG_SMBIOS=y
>>>> CONFIG_ASPEED_SOC=y
>>>> CONFIG_GPIO_KEY=y
>>>> +CONFIG_MSF2=y
>>>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>>>> index a2e56ec..df36a03 100644
>>>> --- a/hw/arm/Makefile.objs
>>>> +++ b/hw/arm/Makefile.objs
>>>> @@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
>>>> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
>>>> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
>>>> obj-$(CONFIG_MPS2) += mps2.o
>>>> +obj-$(CONFIG_MSF2) += msf2-soc.o
>>>> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
>>>> new file mode 100644
>>>> index 0000000..47fffa4
>>>> --- /dev/null
>>>> +++ b/hw/arm/msf2-soc.c
>>>> @@ -0,0 +1,218 @@
>>>> +/*
>>>> + * SmartFusion2 SoC emulation.
>>>> + *
>>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person
>>>> obtaining a copy
>>>> + * of this software and associated documentation files (the
>>>> "Software"), to deal
>>>> + * in the Software without restriction, including without limitation
>>>> the rights
>>>> + * to use, copy, modify, merge, publish, distribute, sublicense,
>>>> and/or sell
>>>> + * copies of the Software, and to permit persons to whom the Software
>>>> is
>>>> + * furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be
>>>> included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>> EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>>> MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>>>> SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
>>>> OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>>> ARISING FROM,
>>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>>>> DEALINGS IN
>>>> + * THE SOFTWARE.
>>>> + */
>>>> +
>>>> +#include "qemu/osdep.h"
>>>> +#include "qapi/error.h"
>>>> +#include "qemu-common.h"
>>>> +#include "hw/arm/arm.h"
>>>> +#include "exec/address-spaces.h"
>>>> +#include "hw/char/serial.h"
>>>> +#include "hw/boards.h"
>>>> +#include "sysemu/block-backend.h"
>>>> +#include "qemu/cutils.h"
>>>> +#include "hw/arm/msf2-soc.h"
>>>> +
>>>> +#define MSF2_TIMER_BASE 0x40004000
>>>> +#define MSF2_SYSREG_BASE 0x40038000
>>>> +
>>>> +#define ENVM_BASE_ADDRESS 0x60000000
>>>> +
>>>> +#define SRAM_BASE_ADDRESS 0x20000000
>>>> +
>>>> +#define MSF2_ENVM_MAX_SIZE (512 * K_BYTE)
>>>> +
>>>> +/*
>>>> + * eSRAM max size is 80k without SECDED(Single error correction and
>>>> + * dual error detection) feature and 64k with SECDED.
>>>> + * We do not support SECDED now.
>>>> + */
>>>> +#define MSF2_ESRAM_MAX_SIZE (80 * K_BYTE)
>>>> +
>>>> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 ,
>>>> 0x40011000 };
>>>> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 ,
>>>> 0x40010000 };
>>>> +
>>>> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
>>>> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
>>>> +static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
>>>> +
>>>> +static void m2sxxx_soc_initfn(Object *obj)
>>>> +{
>>>> + MSF2State *s = MSF2_SOC(obj);
>>>> + int i;
>>>> +
>>>> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
>>>> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
>>>> +
>>>> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
>>>> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
>>>> +
>>>> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
>>>> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
>>>> +
>>>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>>>> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>>> + TYPE_MSS_SPI);
>>>> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>>> + }
>>>> +}
>>>> +
>>>> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
>>>> +{
>>>> + MSF2State *s = MSF2_SOC(dev_soc);
>>>> + DeviceState *dev, *armv7m;
>>>> + SysBusDevice *busdev;
>>>> + Error *err = NULL;
>>>> + int i;
>>>> +
>>>> + MemoryRegion *system_memory = get_system_memory();
>>>> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
>>>> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
>>>> + MemoryRegion *sram = g_new(MemoryRegion, 1);
>>>> +
>>>> + memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
>>>> + &error_fatal);
>>>> + /*
>>>> + * On power-on, the eNVM region 0x60000000 is automatically
>>>> + * remapped to the Cortex-M3 processor executable region
>>>> + * start address (0x0). We do not support remapping other eNVM,
>>>> + * eSRAM and DDR regions by guest(via Sysreg) currently.
>>>> + */
>>>> + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
>>>>
>>>
>>> you can drop the ".alias", this function already prepends "alias "
>>
>>
>> .remap sounds good?
>>
>> Thanks,
>> Sundeep
>>
>>>
>>>
>>> + nvm, 0, s->envm_size);
>>>> +
>>>> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS,
>>>> nvm);
>>>> + memory_region_add_subregion(system_memory, 0, nvm_alias);
>>>> +
>>>> + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
>>>> + &error_fatal);
>>>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS,
>>>> sram);
>>>> +
>>>> + armv7m = DEVICE(&s->armv7m);
>>>> + qdev_prop_set_uint32(armv7m, "num-irq", 81);
>>>> + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
>>>> + object_property_set_link(OBJECT(&s->armv7m),
>>>> OBJECT(get_system_memory()),
>>>> + "memory", &error_abort);
>>>> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized",
>>>> &err);
>>>> + if (err != NULL) {
>>>> + error_propagate(errp, err);
>>>> + return;
>>>> + }
>>>> +
>>>> + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
>>>> +
>>>> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
>>>> + if (serial_hds[i]) {
>>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
>>>> + qdev_get_gpio_in(armv7m, uart_irq[i]),
>>>> + 115200, serial_hds[i],
>>>> DEVICE_NATIVE_ENDIAN);
>>>> + }
>>>> + }
>>>> +
>>>> + dev = DEVICE(&s->timer);
>>>> + /* APB0 clock is the timer input clock */
>>>> + qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk /
>>>> s->apb0div);
>>>> + object_property_set_bool(OBJECT(&s->timer), true, "realized",
>>>> &err);
>>>> + if (err != NULL) {
>>>> + error_propagate(errp, err);
>>>> + return;
>>>> + }
>>>> + busdev = SYS_BUS_DEVICE(dev);
>>>> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
>>>> + sysbus_connect_irq(busdev, 0,
>>>> + qdev_get_gpio_in(armv7m, timer_irq[0]));
>>>> + sysbus_connect_irq(busdev, 1,
>>>> + qdev_get_gpio_in(armv7m, timer_irq[1]));
>>>> +
>>>> + dev = DEVICE(&s->sysreg);
>>>> + qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
>>>> + qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
>>>> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized",
>>>> &err);
>>>> + if (err != NULL) {
>>>> + error_propagate(errp, err);
>>>> + return;
>>>> + }
>>>> + busdev = SYS_BUS_DEVICE(dev);
>>>> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
>>>> +
>>>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>>>> + gchar *bus_name;
>>>> +
>>>> + object_property_set_bool(OBJECT(&s->spi[i]), true,
>>>> "realized", &err);
>>>> + if (err != NULL) {
>>>> + error_propagate(errp, err);
>>>> + return;
>>>> + }
>>>> +
>>>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>>> + qdev_get_gpio_in(armv7m, spi_irq[i]));
>>>> +
>>>> + /* Alias controller SPI bus to the SoC itself */
>>>> + bus_name = g_strdup_printf("spi%d", i);
>>>> + object_property_add_alias(OBJECT(s), bus_name,
>>>> + OBJECT(&s->spi[i]), "spi",
>>>> + &error_abort);
>>>> + g_free(bus_name);
>>>> + }
>>>> +}
>>>> +
>>>> +static Property m2sxxx_soc_properties[] = {
>>>> + /*
>>>> + * part name specifies the type of SmartFusion2 device variant(this
>>>> + * property is for information purpose only.
>>>> + */
>>>> + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
>>>> + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size,
>>>> MSF2_ENVM_MAX_SIZE),
>>>> + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
>>>> + MSF2_ESRAM_MAX_SIZE),
>>>> + /* Libero GUI shows 100Mhz as default for clocks */
>>>> + DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
>>>> + /* default divisors in Libero GUI */
>>>> + DEFINE_PROP_UINT32("apb0div", MSF2State, apb0div, 2),
>>>> + DEFINE_PROP_UINT32("apb1div", MSF2State, apb1div, 2),
>>>> + DEFINE_PROP_END_OF_LIST(),
>>>> +};
>>>> +
>>>> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
>>>> +{
>>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>>> +
>>>> + dc->realize = m2sxxx_soc_realize;
>>>> + dc->props = m2sxxx_soc_properties;
>>>> +}
>>>> +
>>>> +static const TypeInfo m2sxxx_soc_info = {
>>>> + .name = TYPE_MSF2_SOC,
>>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>>> + .instance_size = sizeof(MSF2State),
>>>> + .instance_init = m2sxxx_soc_initfn,
>>>> + .class_init = m2sxxx_soc_class_init,
>>>> +};
>>>> +
>>>> +static void m2sxxx_soc_types(void)
>>>> +{
>>>> + type_register_static(&m2sxxx_soc_info);
>>>> +}
>>>> +
>>>> +type_init(m2sxxx_soc_types)
>>>> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
>>>> new file mode 100644
>>>> index 0000000..eb239fa
>>>> --- /dev/null
>>>> +++ b/include/hw/arm/msf2-soc.h
>>>> @@ -0,0 +1,66 @@
>>>> +/*
>>>> + * Microsemi Smartfusion2 SoC
>>>> + *
>>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person
>>>> obtaining a copy
>>>> + * of this software and associated documentation files (the
>>>> "Software"), to deal
>>>> + * in the Software without restriction, including without limitation
>>>> the rights
>>>> + * to use, copy, modify, merge, publish, distribute, sublicense,
>>>> and/or sell
>>>> + * copies of the Software, and to permit persons to whom the Software
>>>> is
>>>> + * furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be
>>>> included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>> EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>>> MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>>>> SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
>>>> OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>>> ARISING FROM,
>>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>>>> DEALINGS IN
>>>> + * THE SOFTWARE.
>>>> + */
>>>> +
>>>> +#ifndef HW_ARM_MSF2_SOC_H
>>>> +#define HW_ARM_MSF2_SOC_H
>>>> +
>>>> +#include "hw/arm/armv7m.h"
>>>> +#include "hw/timer/mss-timer.h"
>>>> +#include "hw/misc/msf2-sysreg.h"
>>>> +#include "hw/ssi/mss-spi.h"
>>>> +
>>>> +#define TYPE_MSF2_SOC "msf2-soc"
>>>> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
>>>> +
>>>> +#define MSF2_NUM_SPIS 2
>>>> +#define MSF2_NUM_UARTS 2
>>>> +
>>>> +/*
>>>> + * System timer consists of two programmable 32-bit
>>>> + * decrementing counters that generate individual interrupts to
>>>> + * the Cortex-M3 processor
>>>> + */
>>>> +#define MSF2_NUM_TIMERS 2
>>>> +
>>>> +typedef struct MSF2State {
>>>> + /*< private >*/
>>>> + SysBusDevice parent_obj;
>>>> + /*< public >*/
>>>> +
>>>> + ARMv7MState armv7m;
>>>> +
>>>> + char *part_name;
>>>> + uint64_t envm_size;
>>>> + uint64_t esram_size;
>>>> +
>>>> + uint32_t m3clk;
>>>> + uint32_t apb0div;
>>>> + uint32_t apb1div;
>>>> +
>>>> + MSF2SysregState sysreg;
>>>> + MSSTimerState timer;
>>>> + MSSSpiState spi[MSF2_NUM_SPIS];
>>>> +} MSF2State;
>>>> +
>>>> +#endif
>>>>
>>>>
>>
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC
2017-09-13 9:21 ` sundeep subbaraya
2017-09-13 17:07 ` sundeep subbaraya
@ 2017-09-13 17:24 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-13 17:24 UTC (permalink / raw)
To: sundeep subbaraya
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Sundeep,
On 09/13/2017 06:21 AM, sundeep subbaraya wrote:
> All patches got Reviewed-by. Do you want me to change alias to remap and
> send
This is just cosmetic for the "alias MSF2.eNVM.alias":
(qemu) info mtree
address-space: cpu-memory
0000000000000000-ffffffffffffffff (prio 0, i/o): armv7m-container
0000000000000000-ffffffffffffffff (prio -1, i/o): system
0000000000000000-000000000003ffff (prio 0, i/o): alias
MSF2.eNVM.alias @MSF2.eNVM 0000000000000000-000000000003ffff
0000000020000000-000000002000ffff (prio 0, ram): MSF2.eSRAM
0000000060000000-000000006003ffff (prio 0, rom): MSF2.eNVM
00000000a0000000-00000000a3ffffff (prio 0, ram): ddr-ram
> v9 or wait so that you get time to review?
I have a draft for your patch 2, I'll send within the day.
Regards,
Phil.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC
2017-09-08 7:24 ` sundeep subbaraya
@ 2017-09-14 4:10 ` Philippe Mathieu-Daudé
2017-09-14 17:06 ` Alistair Francis
0 siblings, 1 reply; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-14 4:10 UTC (permalink / raw)
To: sundeep subbaraya
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
On 09/08/2017 04:24 AM, sundeep subbaraya wrote:
> Hi Phillipe,
>
> On Fri, Sep 8, 2017 at 3:14 AM, Philippe Mathieu-Daudé <f4bug@amsat.org
> <mailto:f4bug@amsat.org>> wrote:
>
> Hi Subbaraya,
>
> very good work!
>
> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>
> Hi Qemu-devel,
>
> I am trying to add Smartfusion2 SoC.
> SoC is from Microsemi and System on Module(SOM)
> board is from Emcraft systems. Smartfusion2 has hardened
> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
> At the moment only system timer, sysreg and SPI
> controller are modelled.
>
> Testing:
> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial
> mon:stdio \
> -kernel u-boot.bin -display none -drive
> file=spi.bin,if=mtd,format=raw
>
>
> "-M emcraft-sf2" ;)
>
>
> copy/paste error :)
>
>
> U-Boot 2010.03-00147-g7da5092 (Jul 03 2017 - 09:04:50)
>
> CPU : SmartFusion2 SoC (Cortex-M3 Hard IP)
> Freqs: CORTEX-M3=142MHz,PCLK0=71MHz,PCLK1=71MHz
> Board: M2S-FG484-SOM Rev 1A, www.emcraft.com <http://www.emcraft.com>
> DRAM: 64 MB
> *** Warning - bad CRC, using default environment
>
> In: serial
> Out: serial
> Err: serial
> Net: M2S_MAC
> Hit any key to stop autoboot: 0
> 16384 KiB S25FL128P_64K at 0:0 is now current device
> ## Booting kernel from Legacy Image at a0007fc0 ...
> Image Name: dtskernel
> Image Type: ARM Linux Kernel Image (uncompressed)
> Data Size: 2664224 Bytes = 2.5 MB
> Load Address: a0008000
> Entry Point: a0008001
> Verifying Checksum ... OK
> Loading Kernel Image ... OK
> OK
>
> Starting kernel ...
>
> NVIC: Bad read offset 0xd74
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.5.0-00001-g3aa90e8-dirty
> (sundeep@sundeep-Vostro-3458) (gcc version 5.4.0 (GCC) ) #102
> PREEMPT Tue May 16 19:43:40 IST 2017
> [ 0.000000] CPU: ARMv7-M [410fc231] revision 1 (ARMv7M), cr=00000000
> [ 0.000000] CPU: unknown data cache, unknown instruction cache
> [ 0.000000] Machine model: Microsemi SmartFusion 2 development board
> [ 0.000000] Kernel command line: console=ttyS0,115200n8 panic=10
> mem=64M@0xa0000000 earlyprintk
> [ 0.000000] Memory: 62204K/65536K available (1472K kernel code,
> 73K rwdata, 652K rodata, 400K init, 120K bss, 3332K reserved, 0K
> cma-reserved)
> [ 0.000000] NR_IRQS:16 nr_irqs:16 16
> [ 0.001178] sched_clock: 32 bits at 83MHz, resolution 12ns, wraps
> every 25873297401ns
> [ 0.003085] clocksource: msf2_clocksource: mask: 0xffffffff
> max_cycles: 0xffffffff, max_idle_ns: 23027234290 ns
> [ 0.009732] timer at 40004000, irq=16
> [ 0.014475] Calibrating delay loop... 442.36 BogoMIPS (lpj=2211840)
> [ 0.653685] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
> [ 0.690789] console [ttyS0] disabled
> [ 0.696659] 40000000.serial: ttyS0 at MMIO 0x40000000 (irq = 17,
> base_baud = 5187500) is a 16550
> [ 0.702725] console [ttyS0] enabled
> [ 0.826251] Freeing unused kernel memory: 400K (a021c000 - a0280000)
> init started: BusyBox v1.24.1 (2017-05-15 09:57:00 IST)
> ~ #
>
> (qemu) info mtree
> address-space: cpu-memory
> 0000000000000000-ffffffffffffffff (prio 0, i/o): armv7m-container
> 0000000000000000-ffffffffffffffff (prio -1, i/o): system
> 0000000000000000-000000000003ffff (prio 0, i/o): alias
> MSF2.eNVM.alias @MSF2.eNVM 0000000000000000-000000000003ffff
> 0000000020000000-000000002000ffff (prio 0, ram): MSF2.eSRAM
> 0000000040000000-000000004000001f (prio 0, i/o): serial
> 0000000040001000-000000004000103f (prio 0, i/o): mss-spi
> 0000000040004000-000000004000402f (prio 0, i/o): mss-timer
> 0000000040011000-000000004001103f (prio 0, i/o): mss-spi
> 0000000040038000-00000000400382ff (prio 0, i/o): msf2-sysreg
> 0000000060000000-000000006003ffff (prio 0, rom): MSF2.eNVM
> 00000000a0000000-00000000a3ffffff (prio 0, ram): ddr-ram
> 0000000022000000-0000000023ffffff (prio 0, i/o): bitband
> 0000000042000000-0000000043ffffff (prio 0, i/o): bitband
> 00000000e000e000-00000000e000efff (prio 0, i/o): nvic
> 00000000e000e000-00000000e000efff (prio 0, i/o): nvic_sysregs
> 00000000e000e010-00000000e000e0ef (prio 1, i/o): systick
>
> (qemu) info qtree
> bus: main-system-bus
> type System
> dev: msf2-soc, id ""
> part-name = "M2S010"
> eNVM-size = 262144 (0x40000)
> eSRAM-size = 65536 (0x10000)
> m3clk = 142000000 (0x876bf80)
> apb0div = 2 (0x2)
> apb1div = 2 (0x2)
> dev: mss-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 0000000040011000/0000000000000040
> bus: spi
> type SSI
> dev: mss-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 0000000040001000/0000000000000040
> bus: spi
> type SSI
> dev: s25sl12801, id ""
> gpio-in "ssi-gpio-cs" 1
> nonvolatile-cfg = 36863 (0x8fff)
> spansion-cr1nv = 0 (0x0)
> spansion-cr2nv = 1 (0x1)
> spansion-cr3nv = 2 (0x2)
> spansion-cr4nv = 16 (0x10)
> drive = "mtd0"
> dev: mss-timer, id ""
> gpio-out "sysbus-irq" 2
> clock-frequency = 71000000 (0x43b5fc0)
> mmio 0000000040004000/0000000000000030
> dev: msf2-sysreg, id ""
> apb0divisor = 2 (0x2)
> apb1divisor = 2 (0x2)
> mmio 0000000040038000/0000000000000300
>
> So far:
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org
> <mailto:f4bug@amsat.org>>
>
>
> Thanks for testing.
>
>
> Just some comments (no need to fix):
>
>
> Thank you, I will look into these errors once the patchset gets into the
> tree.
>
>
> M2S-FG484-SOM> reset
> resetting ...
> M2S-FG484-SOM>
>
> Hmm no reset, I was expecting some unimp/guest-error warning.
>
> M2S-FG484-SOM> tftpboot
> m2s_eth_init: FIFO initialization timeout
> *** m2s_mac_dump_regs FIFO init:
> DMA TX CTRL=00000000;DESC=00000000;STAT=00000000
> DMA RX CTRL=00000000;DESC=00000000;STAT=00000000
> DMA IRQ 00000000/00000000
> CFG1=00000000;CFG2=00000000;IFG=00000000;HD=00000000;MFL=00000000
> IFCTRL=00000000;IFSTAT=00000000;ADR1=00000000;ADR2=00000000
> FIFO CFG 00000000/00000000/00000000/00000000/00000000/00000000/
> FIFO ACC
> 00000000/00000000/00000000/00000000/00000000/00000000/00000000/00000000/
>
> (same unimp/guest-error warning)
>
> If device is not implemented how do I print warning when guest access
> that device?
in hw/arm/msf2-soc.c:
create_unimplemented_device("emac", 0x40041000, 0x1000);
and while here:
create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
create_unimplemented_device("rtc", 0x40017000, 0x1000);
create_unimplemented_device("usb", 0x40043000, 0x1000);
Then you'll see unimp access running "qemu-system-arm -d unimp"
This can be another patch although.
Regards,
Phil.
>
> Thanks,
> Sundeep
>
>
> M2S-FG484-SOM> sf erase 0 0x1000
> UNHANDLED EXCEPTION: HARD FAULT
> R0 = 00000072 R1 = 00000072
> R2 = 09fa3af0 R3 = 004c8000
> R12 = 00000004 LR = 00000a27
> PC = 0000ec98 PSR = 01000000
> [hang]
> IN:
> 0x0000029e: e7fe b.n 0x29e
>
>
>
>
>
> Binaries u-boot.bin and spi.bin are at:
> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
> <https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git>
>
> U-boot is from Emcraft with modified
> - SPI driver not to use PDMA.
> - ugly hack to pass dtb to kernel in r1.
> @
> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
> <https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git>
>
> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
> driver added by myself @
> https://github.com/Subbaraya-Sundeep/linux.git
> <https://github.com/Subbaraya-Sundeep/linux.git>
>
> v8:
> memory_region_init_ram to memory_region_init_rom in soc
> %s/emcraft_sf2_init/emcraft_sf2_s2s010_init/g in som
> Added mc->ignore_memory_transaction_failures = true in som
> as per latest commit.
> Code simplifications as suggested by Alistair in sysreg
> and ssi.
>
> v7:
> Removed vmstate_register_ram_global as per latest commit
> Moved header files to C which are local to C source files
> Removed abort() from msf2-sysreg.c
> Added VMStateDescription in mss-timer.c
>
> v6:
> Moved some defines from header files to source files
> Added properties m3clk, apb0div, apb0div1 properties
> to soc.
> Added properties apb0divisor, apb1divisor to sysreg
> Update system_clock_source in msf2-soc.c
> Changed machine name smartfusion2-som->emcraft-sf2
>
> v5
> As per Philippe comments:
> Added abort in Sysreg if guest tries to remap memory
> other than default mapping.
> Use of CONFIG_MSF2 in Makefile for soc.c
> Fixed incorrect logic in timer model.
> Renamed msf2-timer.c -> mss-timer.c
> msf2-spi.c -> mss-spi.c also type names
> Renamed function msf2_init->emcraft_sf2_init in msf2-som.c
> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
> properties to soc.
> Pass soc part-name,memory size and clock rate
> properties from som.
> v4:
> Fixed build failure by using PRIx macros.
> v3:
> Added SoC file and board file as per Alistair comments.
> v2:
> Added SPI controller so that u-boot loads kernel from spi
> flash.
> v1:
> Initial patch set with timer and sysreg
>
> Thanks,
> Sundeep
>
>
> Subbaraya Sundeep (5):
> msf2: Add Smartfusion2 System timer
> msf2: Microsemi Smartfusion2 System Register block
> msf2: Add Smartfusion2 SPI controller
> msf2: Add Smartfusion2 SoC
> msf2: Add Emcraft's Smartfusion2 SOM kit
>
> default-configs/arm-softmmu.ma <http://arm-softmmu.ma>k | 1 +
> hw/arm/Makefile.objs | 1 +
> hw/arm/msf2-soc.c | 218 ++++++++++++++++++++++
> hw/arm/msf2-som.c | 95 ++++++++++
> hw/misc/Makefile.objs | 1 +
> hw/misc/msf2-sysreg.c | 195 +++++++++++++++++++
> hw/ssi/Makefile.objs | 1 +
> hw/ssi/mss-spi.c | 404
> ++++++++++++++++++++++++++++++++++++++++
> hw/timer/Makefile.objs | 1 +
> hw/timer/mss-timer.c | 289
> ++++++++++++++++++++++++++++
> include/hw/arm/msf2-soc.h | 66 +++++++
> include/hw/misc/msf2-sysreg.h | 78 ++++++++
> include/hw/ssi/mss-spi.h | 58 ++++++
> include/hw/timer/mss-timer.h | 64 +++++++
> 14 files changed, 1472 insertions(+)
> create mode 100644 hw/arm/msf2-soc.c
> create mode 100644 hw/arm/msf2-som.c
> create mode 100644 hw/misc/msf2-sysreg.c
> create mode 100644 hw/ssi/mss-spi.c
> create mode 100644 hw/timer/mss-timer.c
> create mode 100644 include/hw/arm/msf2-soc.h
> create mode 100644 include/hw/misc/msf2-sysreg.h
> create mode 100644 include/hw/ssi/mss-spi.h
> create mode 100644 include/hw/timer/mss-timer.h
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
@ 2017-09-14 4:36 ` Philippe Mathieu-Daudé
2017-09-14 13:13 ` Peter Maydell
` (2 more replies)
0 siblings, 3 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-14 4:36 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm, peter.maydell, alistair23
Cc: crosthwaite.peter
Hi Sundeep,
On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
> Added Sytem register block of Smartfusion2.
> This block has PLL registers which are accessed by guest.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> hw/misc/Makefile.objs | 1 +
> hw/misc/msf2-sysreg.c | 195 ++++++++++++++++++++++++++++++++++++++++++
> include/hw/misc/msf2-sysreg.h | 78 +++++++++++++++++
> 3 files changed, 274 insertions(+)
> create mode 100644 hw/misc/msf2-sysreg.c
> create mode 100644 include/hw/misc/msf2-sysreg.h
>
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index 29fb922..e8f0a02 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
> obj-$(CONFIG_AUX) += auxbus.o
> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
> obj-y += mmio_interface.o
> +obj-$(CONFIG_MSF2) += msf2-sysreg.o
> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
> new file mode 100644
> index 0000000..40d603d
> --- /dev/null
> +++ b/hw/misc/msf2-sysreg.c
> @@ -0,0 +1,195 @@
> +/*
> + * System Register block model of Microsemi SmartFusion2.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "hw/misc/msf2-sysreg.h"
> +
> +#ifndef MSF2_SYSREG_ERR_DEBUG
> +#define MSF2_SYSREG_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt "\n", __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static inline int msf2_divbits(uint32_t div)
Please directly use ctz32() instead of msf2_divbits()
> +{
> + int ret = 0;
> +
> + switch (div) {
> + case 1:
> + ret = 0;
> + break;
> + case 2:
> + ret = 1;
> + break;
> + case 4:
> + ret = 2;
> + break;
> + case 8:
> + ret = 4;
> + break;
> + case 16:
> + ret = 5;
> + break;
> + case 32:
> + ret = 6;
> + break;
> + default:
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static void msf2_sysreg_reset(DeviceState *d)
> +{
> + MSF2SysregState *s = MSF2_SYSREG(d);
> +
> + DB_PRINT("RESET");
> +
> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
> + s->regs[MSSDDR_PLL_STATUS] = 0x3;
> + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
> + msf2_divbits(s->apb1div) << 2;
> +}
> +
> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + MSF2SysregState *s = opaque;
> + uint32_t ret = 0;
> +
> + offset >>= 2;
> + if (offset < ARRAY_SIZE(s->regs)) {
This comment is controversial, I'll let Peter nod.
The SYSREG behaves differently regarding which bus access it (CPU, AHB).
You are implementing CPU access to the SYSREG, the registers have
different permissions when accessed by the CPU. (see the SmartFusion2
User Guide: Table 21-1 "Register Types" and Table 21-2 "Register Map").
I'd think of this stub:
switch(reg) {
case register_supported1:
case register_supported2:
case register_supported3:
ret = s->regs[offset];
trace_msf2_sysreg_read(offset, ret);
break;
case RO-U:
qemu_log_mask(LOG_GUEST_ERROR, "Illegal AHB access 0x%08"...
break;
case W1P:
qemu_log_mask(LOG_GUEST_ERROR, "Illegal read access ...
break;
case RW:
case RW-P:
case RO:
case RO-P:
default:
ret = s->regs[offset];
qemu_log_mask(LOG_UNIMP, "...
break;
}
Anyway keep this comment for further improvements, it's probably not
useful for your use case.
> + ret = s->regs[offset];
> + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32,
> + offset << 2, ret);
Can you replace DB_PRINT by traces? such:
trace_msf2_sysreg_read(...);
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
> + offset << 2);
> + }
> +
> + return ret;
> +}
> +
> +static void msf2_sysreg_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + MSF2SysregState *s = opaque;
> + uint32_t newval = val;
> +
> + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64,
> + offset, val);
> +
> + offset >>= 2;
> +
> + switch (offset) {
> + case MSSDDR_PLL_STATUS:
trace_msf2_sysreg_write_pll_status();
> + break;
> +
> + case ESRAM_CR:
> + if (newval != s->regs[ESRAM_CR]) {
> + qemu_log_mask(LOG_GUEST_ERROR,
Since this isn't a guest error, use LOG_UNIMP instead.
> + TYPE_MSF2_SYSREG": eSRAM remapping not supported\n");
> + }
> + break;
> +
> + case DDR_CR:
> + if (newval != s->regs[DDR_CR]) {
> + qemu_log_mask(LOG_GUEST_ERROR,
LOG_UNIMP
> + TYPE_MSF2_SYSREG": DDR remapping not supported\n");
> + }
> + break;
> +
> + case ENVM_REMAP_BASE_CR:
> + if (newval != s->regs[ENVM_REMAP_BASE_CR]) {
> + qemu_log_mask(LOG_GUEST_ERROR,
LOG_UNIMP
> + TYPE_MSF2_SYSREG": eNVM remapping not supported\n");
> + }
> + break;
> +
Or shorter:
case ESRAM_CR:
case DDR_CR:
case ENVM_REMAP_BASE_CR:
oldval = s->regs[offset];
if (oldval ^ newval) {
qemu_log_mask(LOG_UNIMP,
TYPE_MSF2_SYSREG": remapping not supported\n");
}
break;
> + default:
> + if (offset < ARRAY_SIZE(s->regs)) {
trace_msf2_sysreg_write(offset, val, s->regs[offset]);
> + s->regs[offset] = newval;
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
> + offset << 2);
> + }
> + break;
> + }
> +}
Good work, almost there, next respin should be ready for Peter to take
in arm-next :)
Regards,
Phil.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block
2017-09-14 4:36 ` Philippe Mathieu-Daudé
@ 2017-09-14 13:13 ` Peter Maydell
2017-09-14 15:30 ` sundeep subbaraya
2017-09-14 15:34 ` sundeep subbaraya
2017-09-17 23:57 ` Philippe Mathieu-Daudé
2 siblings, 1 reply; 28+ messages in thread
From: Peter Maydell @ 2017-09-14 13:13 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Subbaraya Sundeep, QEMU Developers, qemu-arm, Alistair Francis,
Peter Crosthwaite
On 14 September 2017 at 05:36, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
>> + unsigned size)
>> +{
>> + MSF2SysregState *s = opaque;
>> + uint32_t ret = 0;
>> +
>> + offset >>= 2;
>> + if (offset < ARRAY_SIZE(s->regs)) {
>
>
> This comment is controversial, I'll let Peter nod.
>
> The SYSREG behaves differently regarding which bus access it (CPU, AHB).
> You are implementing CPU access to the SYSREG, the registers have different
> permissions when accessed by the CPU. (see the SmartFusion2 User Guide:
> Table 21-1 "Register Types" and Table 21-2 "Register Map").
>
> I'd think of this stub:
>
> switch(reg) {
> case register_supported1:
> case register_supported2:
> case register_supported3:
> ret = s->regs[offset];
> trace_msf2_sysreg_read(offset, ret);
> break;
> case RO-U:
> qemu_log_mask(LOG_GUEST_ERROR, "Illegal AHB access 0x%08"...
> break;
> case W1P:
> qemu_log_mask(LOG_GUEST_ERROR, "Illegal read access ...
> break;
> case RW:
> case RW-P:
> case RO:
> case RO-P:
> default:
> ret = s->regs[offset];
> qemu_log_mask(LOG_UNIMP, "...
> break;
> }
This doesn't look entirely right, since this is the read interface.
Shouldn't we be allowing pretty much all of these register types
except maybe W1P to do a read?
On the other hand, in the write function we should probably not allow
writes to registers documented as read only.
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block
2017-09-14 13:13 ` Peter Maydell
@ 2017-09-14 15:30 ` sundeep subbaraya
2017-09-14 18:05 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-14 15:30 UTC (permalink / raw)
To: Peter Maydell
Cc: Philippe Mathieu-Daudé,
QEMU Developers, qemu-arm, Alistair Francis, Peter Crosthwaite
Hi Philippe,
On Thu, Sep 14, 2017 at 6:43 PM, Peter Maydell <peter.maydell@linaro.org>
wrote:
> On 14 September 2017 at 05:36, Philippe Mathieu-Daudé <f4bug@amsat.org>
> wrote:
> > On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
> >> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
> >> + unsigned size)
> >> +{
> >> + MSF2SysregState *s = opaque;
> >> + uint32_t ret = 0;
> >> +
> >> + offset >>= 2;
> >> + if (offset < ARRAY_SIZE(s->regs)) {
> >
> >
> > This comment is controversial, I'll let Peter nod.
> >
> > The SYSREG behaves differently regarding which bus access it (CPU, AHB).
> > You are implementing CPU access to the SYSREG, the registers have
> different
> > permissions when accessed by the CPU. (see the SmartFusion2 User Guide:
> > Table 21-1 "Register Types" and Table 21-2 "Register Map").
>
CPU is also one of the bus masters in AHB matrix (Fig 6.1 in page 248).
>
> > I'd think of this stub:
> >
> > switch(reg) {
> > case register_supported1:
> > case register_supported2:
> > case register_supported3:
> > ret = s->regs[offset];
> > trace_msf2_sysreg_read(offset, ret);
> > break;
> > case RO-U:
> > qemu_log_mask(LOG_GUEST_ERROR, "Illegal AHB access 0x%08"...
> > break;
> > case W1P:
> > qemu_log_mask(LOG_GUEST_ERROR, "Illegal read access ...
> > break;
> > case RW:
> > case RW-P:
> > case RO:
> > case RO-P:
> > default:
> > ret = s->regs[offset];
> > qemu_log_mask(LOG_UNIMP, "...
> > break;
> > }
>
This sounds good to me and will fix later by rearranging registers in enum
sorted
based on type (RO, RW, etc.,) and use those ranges in switch case.
>
> This doesn't look entirely right, since this is the read interface.
> Shouldn't we be allowing pretty much all of these register types
> except maybe W1P to do a read?
>
Peter, some of the registers are not allowed to access by CPU and are only
set during
device programming. For those registers Philippe is suggesting to log
"Illegal AHB access"
when guest is trying to read/write.
Thanks,
Sundeep
>
> On the other hand, in the write function we should probably not allow
> writes to registers documented as read only.
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block
2017-09-14 4:36 ` Philippe Mathieu-Daudé
2017-09-14 13:13 ` Peter Maydell
@ 2017-09-14 15:34 ` sundeep subbaraya
2017-09-17 23:57 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-14 15:34 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Alistair Francis,
Peter Crosthwaite
Hi Philippe,
On Thu, Sep 14, 2017 at 10:06 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Sundeep,
>
>
> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>
>> Added Sytem register block of Smartfusion2.
>> This block has PLL registers which are accessed by guest.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> hw/misc/Makefile.objs | 1 +
>> hw/misc/msf2-sysreg.c | 195 ++++++++++++++++++++++++++++++
>> ++++++++++++
>> include/hw/misc/msf2-sysreg.h | 78 +++++++++++++++++
>> 3 files changed, 274 insertions(+)
>> create mode 100644 hw/misc/msf2-sysreg.c
>> create mode 100644 include/hw/misc/msf2-sysreg.h
>>
>> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
>> index 29fb922..e8f0a02 100644
>> --- a/hw/misc/Makefile.objs
>> +++ b/hw/misc/Makefile.objs
>> @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
>> obj-$(CONFIG_AUX) += auxbus.o
>> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
>> obj-y += mmio_interface.o
>> +obj-$(CONFIG_MSF2) += msf2-sysreg.o
>> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
>> new file mode 100644
>> index 0000000..40d603d
>> --- /dev/null
>> +++ b/hw/misc/msf2-sysreg.c
>> @@ -0,0 +1,195 @@
>> +/*
>> + * System Register block model of Microsemi SmartFusion2.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version
>> + * 2 of the License, or (at your option) any later version.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qemu/log.h"
>> +#include "hw/misc/msf2-sysreg.h"
>> +
>> +#ifndef MSF2_SYSREG_ERR_DEBUG
>> +#define MSF2_SYSREG_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> + if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \
>> + qemu_log("%s: " fmt "\n", __func__, ## args); \
>> + } \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static inline int msf2_divbits(uint32_t div)
>>
>
> Please directly use ctz32() instead of msf2_divbits()
>
> ctz32() will not work for input 8,16,32 so need to use msf2_divbits().
>
> +{
>> + int ret = 0;
>> +
>> + switch (div) {
>> + case 1:
>> + ret = 0;
>> + break;
>> + case 2:
>> + ret = 1;
>> + break;
>> + case 4:
>> + ret = 2;
>> + break;
>> + case 8:
>> + ret = 4;
>> + break;
>> + case 16:
>> + ret = 5;
>> + break;
>> + case 32:
>> + ret = 6;
>> + break;
>> + default:
>> + break;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void msf2_sysreg_reset(DeviceState *d)
>> +{
>> + MSF2SysregState *s = MSF2_SYSREG(d);
>> +
>> + DB_PRINT("RESET");
>> +
>> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
>> + s->regs[MSSDDR_PLL_STATUS] = 0x3;
>> + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |
>> + msf2_divbits(s->apb1div) << 2;
>> +}
>> +
>> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
>> + unsigned size)
>> +{
>> + MSF2SysregState *s = opaque;
>> + uint32_t ret = 0;
>> +
>> + offset >>= 2;
>> + if (offset < ARRAY_SIZE(s->regs)) {
>>
>
> This comment is controversial, I'll let Peter nod.
>
> The SYSREG behaves differently regarding which bus access it (CPU, AHB).
> You are implementing CPU access to the SYSREG, the registers have
> different permissions when accessed by the CPU. (see the SmartFusion2 User
> Guide: Table 21-1 "Register Types" and Table 21-2 "Register Map").
>
> I'd think of this stub:
>
> switch(reg) {
> case register_supported1:
> case register_supported2:
> case register_supported3:
> ret = s->regs[offset];
> trace_msf2_sysreg_read(offset, ret);
> break;
> case RO-U:
> qemu_log_mask(LOG_GUEST_ERROR, "Illegal AHB access 0x%08"...
> break;
> case W1P:
> qemu_log_mask(LOG_GUEST_ERROR, "Illegal read access ...
> break;
> case RW:
> case RW-P:
> case RO:
> case RO-P:
> default:
> ret = s->regs[offset];
> qemu_log_mask(LOG_UNIMP, "...
> break;
> }
>
> Anyway keep this comment for further improvements, it's probably not
> useful for your use case.
Sure will remember this comment and fix it later.
>
>
> + ret = s->regs[offset];
>> + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32,
>> + offset << 2, ret);
>>
>
> Can you replace DB_PRINT by traces? such:
>
> trace_msf2_sysreg_read(...);
Ok
>
>
> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
>> + offset << 2);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void msf2_sysreg_write(void *opaque, hwaddr offset,
>> + uint64_t val, unsigned size)
>> +{
>> + MSF2SysregState *s = opaque;
>> + uint32_t newval = val;
>> +
>> + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64,
>> + offset, val);
>> +
>> + offset >>= 2;
>> +
>> + switch (offset) {
>> + case MSSDDR_PLL_STATUS:
>>
> trace_msf2_sysreg_write_pll_status();
>
> + break;
>> +
>> + case ESRAM_CR:
>> + if (newval != s->regs[ESRAM_CR]) {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>>
>
> Since this isn't a guest error, use LOG_UNIMP instead.
>
> Ok
> + TYPE_MSF2_SYSREG": eSRAM remapping not
>> supported\n");
>> + }
>> + break;
>> +
>> + case DDR_CR:
>> + if (newval != s->regs[DDR_CR]) {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>>
>
> LOG_UNIMP
>
> Ok
> + TYPE_MSF2_SYSREG": DDR remapping not supported\n");
>> + }
>> + break;
>> +
>> + case ENVM_REMAP_BASE_CR:
>> + if (newval != s->regs[ENVM_REMAP_BASE_CR]) {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>>
>
> LOG_UNIMP
>
> Ok
> + TYPE_MSF2_SYSREG": eNVM remapping not
>> supported\n");
>> + }
>> + break;
>> +
>>
>
> Or shorter:
>
> case ESRAM_CR:
> case DDR_CR:
> case ENVM_REMAP_BASE_CR:
> oldval = s->regs[offset];
> if (oldval ^ newval) {
> qemu_log_mask(LOG_UNIMP,
> TYPE_MSF2_SYSREG": remapping not supported\n");
> }
> break;
>
> Ok
>
> + default:
>> + if (offset < ARRAY_SIZE(s->regs)) {
>>
>
> trace_msf2_sysreg_write(offset, val, s->regs[offset]);
>
> + s->regs[offset] = newval;
>> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: Bad offset 0x%08" HWADDR_PRIx "\n",
>> __func__,
>> + offset << 2);
>> + }
>> + break;
>> + }
>> +}
>>
>
> Good work, almost there, next respin should be ready for Peter to take in
> arm-next :)
>
> Thank you,
Sundeep
> Regards,
>
> Phil.
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC
2017-09-14 4:10 ` Philippe Mathieu-Daudé
@ 2017-09-14 17:06 ` Alistair Francis
2017-09-14 17:17 ` Peter Maydell
0 siblings, 1 reply; 28+ messages in thread
From: Alistair Francis @ 2017-09-14 17:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: sundeep subbaraya, QEMU Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
On Wed, Sep 13, 2017 at 9:10 PM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 09/08/2017 04:24 AM, sundeep subbaraya wrote:
>>
>> Hi Phillipe,
>>
>> On Fri, Sep 8, 2017 at 3:14 AM, Philippe Mathieu-Daudé <f4bug@amsat.org
>> <mailto:f4bug@amsat.org>> wrote:
>>
>> Hi Subbaraya,
>>
>> very good work!
>>
>> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>>
>> Hi Qemu-devel,
>>
>> I am trying to add Smartfusion2 SoC.
>> SoC is from Microsemi and System on Module(SOM)
>> board is from Emcraft systems. Smartfusion2 has hardened
>> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
>> At the moment only system timer, sysreg and SPI
>> controller are modelled.
>>
>> Testing:
>> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial
>> mon:stdio \
>> -kernel u-boot.bin -display none -drive
>> file=spi.bin,if=mtd,format=raw
>>
>>
>> "-M emcraft-sf2" ;)
>>
>>
>> copy/paste error :)
>>
>>
>> U-Boot 2010.03-00147-g7da5092 (Jul 03 2017 - 09:04:50)
>>
>> CPU : SmartFusion2 SoC (Cortex-M3 Hard IP)
>> Freqs: CORTEX-M3=142MHz,PCLK0=71MHz,PCLK1=71MHz
>> Board: M2S-FG484-SOM Rev 1A, www.emcraft.com <http://www.emcraft.com>
>>
>> DRAM: 64 MB
>> *** Warning - bad CRC, using default environment
>>
>> In: serial
>> Out: serial
>> Err: serial
>> Net: M2S_MAC
>> Hit any key to stop autoboot: 0
>> 16384 KiB S25FL128P_64K at 0:0 is now current device
>> ## Booting kernel from Legacy Image at a0007fc0 ...
>> Image Name: dtskernel
>> Image Type: ARM Linux Kernel Image (uncompressed)
>> Data Size: 2664224 Bytes = 2.5 MB
>> Load Address: a0008000
>> Entry Point: a0008001
>> Verifying Checksum ... OK
>> Loading Kernel Image ... OK
>> OK
>>
>> Starting kernel ...
>>
>> NVIC: Bad read offset 0xd74
>> [ 0.000000] Booting Linux on physical CPU 0x0
>> [ 0.000000] Linux version 4.5.0-00001-g3aa90e8-dirty
>> (sundeep@sundeep-Vostro-3458) (gcc version 5.4.0 (GCC) ) #102
>> PREEMPT Tue May 16 19:43:40 IST 2017
>> [ 0.000000] CPU: ARMv7-M [410fc231] revision 1 (ARMv7M),
>> cr=00000000
>> [ 0.000000] CPU: unknown data cache, unknown instruction cache
>> [ 0.000000] Machine model: Microsemi SmartFusion 2 development
>> board
>> [ 0.000000] Kernel command line: console=ttyS0,115200n8 panic=10
>> mem=64M@0xa0000000 earlyprintk
>> [ 0.000000] Memory: 62204K/65536K available (1472K kernel code,
>> 73K rwdata, 652K rodata, 400K init, 120K bss, 3332K reserved, 0K
>> cma-reserved)
>> [ 0.000000] NR_IRQS:16 nr_irqs:16 16
>> [ 0.001178] sched_clock: 32 bits at 83MHz, resolution 12ns, wraps
>> every 25873297401ns
>> [ 0.003085] clocksource: msf2_clocksource: mask: 0xffffffff
>> max_cycles: 0xffffffff, max_idle_ns: 23027234290 ns
>> [ 0.009732] timer at 40004000, irq=16
>> [ 0.014475] Calibrating delay loop... 442.36 BogoMIPS (lpj=2211840)
>> [ 0.653685] Serial: 8250/16550 driver, 1 ports, IRQ sharing
>> disabled
>> [ 0.690789] console [ttyS0] disabled
>> [ 0.696659] 40000000.serial: ttyS0 at MMIO 0x40000000 (irq = 17,
>> base_baud = 5187500) is a 16550
>> [ 0.702725] console [ttyS0] enabled
>> [ 0.826251] Freeing unused kernel memory: 400K (a021c000 -
>> a0280000)
>> init started: BusyBox v1.24.1 (2017-05-15 09:57:00 IST)
>> ~ #
>>
>> (qemu) info mtree
>> address-space: cpu-memory
>> 0000000000000000-ffffffffffffffff (prio 0, i/o): armv7m-container
>> 0000000000000000-ffffffffffffffff (prio -1, i/o): system
>> 0000000000000000-000000000003ffff (prio 0, i/o): alias
>> MSF2.eNVM.alias @MSF2.eNVM 0000000000000000-000000000003ffff
>> 0000000020000000-000000002000ffff (prio 0, ram): MSF2.eSRAM
>> 0000000040000000-000000004000001f (prio 0, i/o): serial
>> 0000000040001000-000000004000103f (prio 0, i/o): mss-spi
>> 0000000040004000-000000004000402f (prio 0, i/o): mss-timer
>> 0000000040011000-000000004001103f (prio 0, i/o): mss-spi
>> 0000000040038000-00000000400382ff (prio 0, i/o): msf2-sysreg
>> 0000000060000000-000000006003ffff (prio 0, rom): MSF2.eNVM
>> 00000000a0000000-00000000a3ffffff (prio 0, ram): ddr-ram
>> 0000000022000000-0000000023ffffff (prio 0, i/o): bitband
>> 0000000042000000-0000000043ffffff (prio 0, i/o): bitband
>> 00000000e000e000-00000000e000efff (prio 0, i/o): nvic
>> 00000000e000e000-00000000e000efff (prio 0, i/o): nvic_sysregs
>> 00000000e000e010-00000000e000e0ef (prio 1, i/o): systick
>>
>> (qemu) info qtree
>> bus: main-system-bus
>> type System
>> dev: msf2-soc, id ""
>> part-name = "M2S010"
>> eNVM-size = 262144 (0x40000)
>> eSRAM-size = 65536 (0x10000)
>> m3clk = 142000000 (0x876bf80)
>> apb0div = 2 (0x2)
>> apb1div = 2 (0x2)
>> dev: mss-spi, id ""
>> gpio-out "sysbus-irq" 2
>> mmio 0000000040011000/0000000000000040
>> bus: spi
>> type SSI
>> dev: mss-spi, id ""
>> gpio-out "sysbus-irq" 2
>> mmio 0000000040001000/0000000000000040
>> bus: spi
>> type SSI
>> dev: s25sl12801, id ""
>> gpio-in "ssi-gpio-cs" 1
>> nonvolatile-cfg = 36863 (0x8fff)
>> spansion-cr1nv = 0 (0x0)
>> spansion-cr2nv = 1 (0x1)
>> spansion-cr3nv = 2 (0x2)
>> spansion-cr4nv = 16 (0x10)
>> drive = "mtd0"
>> dev: mss-timer, id ""
>> gpio-out "sysbus-irq" 2
>> clock-frequency = 71000000 (0x43b5fc0)
>> mmio 0000000040004000/0000000000000030
>> dev: msf2-sysreg, id ""
>> apb0divisor = 2 (0x2)
>> apb1divisor = 2 (0x2)
>> mmio 0000000040038000/0000000000000300
>>
>> So far:
>> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org
>> <mailto:f4bug@amsat.org>>
>>
>>
>> Thanks for testing.
>>
>>
>> Just some comments (no need to fix):
>>
>>
>> Thank you, I will look into these errors once the patchset gets into the
>> tree.
>>
>>
>> M2S-FG484-SOM> reset
>> resetting ...
>> M2S-FG484-SOM>
>>
>> Hmm no reset, I was expecting some unimp/guest-error warning.
>>
>> M2S-FG484-SOM> tftpboot
>> m2s_eth_init: FIFO initialization timeout
>> *** m2s_mac_dump_regs FIFO init:
>> DMA TX CTRL=00000000;DESC=00000000;STAT=00000000
>> DMA RX CTRL=00000000;DESC=00000000;STAT=00000000
>> DMA IRQ 00000000/00000000
>> CFG1=00000000;CFG2=00000000;IFG=00000000;HD=00000000;MFL=00000000
>> IFCTRL=00000000;IFSTAT=00000000;ADR1=00000000;ADR2=00000000
>> FIFO CFG 00000000/00000000/00000000/00000000/00000000/00000000/
>> FIFO ACC
>>
>> 00000000/00000000/00000000/00000000/00000000/00000000/00000000/00000000/
>>
>> (same unimp/guest-error warning)
>>
>> If device is not implemented how do I print warning when guest access that
>> device?
>
>
> in hw/arm/msf2-soc.c:
>
> create_unimplemented_device("emac", 0x40041000, 0x1000);
>
> and while here:
>
> create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
> create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
> create_unimplemented_device("rtc", 0x40017000, 0x1000);
> create_unimplemented_device("usb", 0x40043000, 0x1000);
>
> Then you'll see unimp access running "qemu-system-arm -d unimp"
>
> This can be another patch although.
Once you have all the devices there you can enable bus access errors
as well. That's a future patch set though.
Thanks,
Alistair
>
> Regards,
>
> Phil.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
@ 2017-09-14 17:14 ` Peter Maydell
2017-09-14 17:45 ` Philippe Mathieu-Daudé
2017-09-15 6:31 ` sundeep subbaraya
0 siblings, 2 replies; 28+ messages in thread
From: Peter Maydell @ 2017-09-14 17:14 UTC (permalink / raw)
To: Subbaraya Sundeep
Cc: QEMU Developers, qemu-arm, Peter Crosthwaite, Alistair Francis,
Philippe Mathieu-Daudé
On 7 September 2017 at 20:24, Subbaraya Sundeep <sundeep.lkml@gmail.com> wrote:
> Emulated Emcraft's Smartfusion2 System On Module starter
> kit.
> +static void emcraft_sf2_machine_init(MachineClass *mc)
> +{
> + mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
> + mc->init = emcraft_sf2_s2s010_init;
> + mc->ignore_memory_transaction_failures = true;
Please don't set ignore_memory_transaction_failures in new boards.
This is a legacy-old-code-only flag.
New boards should define enough devices, either properly
or using create_unimplemented_device(), to make whatever code
they're being tested against run.
This is a firm requirement for this code to go into master,
because once we let a board in with the flag set it's almost
impossible to clear it because we don't know what guest
code that previously worked on the board will now break.
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC
2017-09-14 17:06 ` Alistair Francis
@ 2017-09-14 17:17 ` Peter Maydell
0 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2017-09-14 17:17 UTC (permalink / raw)
To: Alistair Francis
Cc: Philippe Mathieu-Daudé,
sundeep subbaraya, QEMU Developers, qemu-arm, Peter Crosthwaite
On 14 September 2017 at 18:06, Alistair Francis <alistair23@gmail.com> wrote:
> Once you have all the devices there you can enable bus access errors
> as well. That's a future patch set though.
Ah, I hadn't noticed this code was opting out of bus access
errors; I don't want to permit new boards which do that,
so we do need to fix that in this round. (I just sent an
email to that effect in reply to patch 1.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit
2017-09-14 17:14 ` Peter Maydell
@ 2017-09-14 17:45 ` Philippe Mathieu-Daudé
2017-09-15 6:31 ` sundeep subbaraya
1 sibling, 0 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-14 17:45 UTC (permalink / raw)
To: Peter Maydell
Cc: Subbaraya Sundeep, QEMU Developers, qemu-arm, Peter Crosthwaite,
Alistair Francis
On 09/14/2017 02:14 PM, Peter Maydell wrote:
> On 7 September 2017 at 20:24, Subbaraya Sundeep <sundeep.lkml@gmail.com> wrote:
>> Emulated Emcraft's Smartfusion2 System On Module starter
>> kit.
>> +static void emcraft_sf2_machine_init(MachineClass *mc)
>> +{
>> + mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
>> + mc->init = emcraft_sf2_s2s010_init;
>> + mc->ignore_memory_transaction_failures = true;
>
> Please don't set ignore_memory_transaction_failures in new boards.
> This is a legacy-old-code-only flag.
What about adding a such check in scripts/checkpatch.pl ?
if ($line =~ /ignore_memory_transaction_failures\s+=/) {
ERROR("ignore_memory_transaction_failures() is a
legacy-old-code-only flag\n" . $herecurr);
}
>
> New boards should define enough devices, either properly
> or using create_unimplemented_device(), to make whatever code
> they're being tested against run.
>
> This is a firm requirement for this code to go into master,
> because once we let a board in with the flag set it's almost
> impossible to clear it because we don't know what guest
> code that previously worked on the board will now break.
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block
2017-09-14 15:30 ` sundeep subbaraya
@ 2017-09-14 18:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-14 18:05 UTC (permalink / raw)
To: sundeep subbaraya, Peter Maydell
Cc: QEMU Developers, qemu-arm, Alistair Francis, Peter Crosthwaite
>>>> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
>>>> + unsigned size)
>>>> +{
>>>> + MSF2SysregState *s = opaque;
>>>> + uint32_t ret = 0;
>>>> +
>>>> + offset >>= 2;
>>>> + if (offset < ARRAY_SIZE(s->regs)) {
>>>
>>>
>>> This comment is controversial, I'll let Peter nod.
>>>
>>> The SYSREG behaves differently regarding which bus access it (CPU, AHB).
>>> You are implementing CPU access to the SYSREG, the registers have
>> different
>>> permissions when accessed by the CPU. (see the SmartFusion2 User Guide:
>>> Table 21-1 "Register Types" and Table 21-2 "Register Map").
>>
>
> CPU is also one of the bus masters in AHB matrix (Fig 6.1 in page 248).
I was worried about Fabric access but Peter remembered me QEMU doesn't
model it ;)
>>> I'd think of this stub:
>>>
>>> switch(reg) {
>>> case register_supported1:
>>> case register_supported2:
>>> case register_supported3:
>>> ret = s->regs[offset];
>>> trace_msf2_sysreg_read(offset, ret);
>>> break;
>>> case RO-U:
>>> qemu_log_mask(LOG_GUEST_ERROR, "Illegal AHB access 0x%08"...
>>> break;
>>> case W1P:
>>> qemu_log_mask(LOG_GUEST_ERROR, "Illegal read access ...
>>> break;
>>> case RW:
>>> case RW-P:
>>> case RO:
>>> case RO-P:
>>> default:
>>> ret = s->regs[offset];
>>> qemu_log_mask(LOG_UNIMP, "...
>>> break;
>>> }
>>
>
> This sounds good to me and will fix later by rearranging registers in enum
> sorted
> based on type (RO, RW, etc.,) and use those ranges in switch case.
The Register API (hw/register.h) is helpful to check such properties but
might turn your code harder to read.
>>
>> This doesn't look entirely right, since this is the read interface.
>> Shouldn't we be allowing pretty much all of these register types
>> except maybe W1P to do a read?
>>
>
> Peter, some of the registers are not allowed to access by CPU and are only
> set during
> device programming. For those registers Philippe is suggesting to log
> "Illegal AHB access"
> when guest is trying to read/write.
I was worried about accessing those registers when the flash
WriteProtect bit is set, however the eNVM flash library is not Open
Source, it is unlikely a guest access those registers, and if it is the
library then MicroSemi already tried it on real hardware.
There is probably no need to worry about "Illegal AHB access" :)
>> On the other hand, in the write function we should probably not allow
>> writes to registers documented as read only.
Surely.
trace_msf2_sysreg_write(offset, s->regs[offset], ret);
switch(reg) {
case register_supported1:
case register_supported2:
case register_supported3:
s->regs[offset] = ret;
break;
case RO:
case RO-P:
case RO-U:
qemu_log_mask(LOG_GUEST_ERROR, "Illegal write access on RO...
break;
default:
qemu_log_mask(LOG_UNIMP, "...
break;
}
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit
2017-09-14 17:14 ` Peter Maydell
2017-09-14 17:45 ` Philippe Mathieu-Daudé
@ 2017-09-15 6:31 ` sundeep subbaraya
1 sibling, 0 replies; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-15 6:31 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, qemu-arm, Peter Crosthwaite, Alistair Francis,
Philippe Mathieu-Daudé
Hi Peter,
On Thu, Sep 14, 2017 at 10:44 PM, Peter Maydell <peter.maydell@linaro.org>
wrote:
> On 7 September 2017 at 20:24, Subbaraya Sundeep <sundeep.lkml@gmail.com>
> wrote:
> > Emulated Emcraft's Smartfusion2 System On Module starter
> > kit.
> > +static void emcraft_sf2_machine_init(MachineClass *mc)
> > +{
> > + mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
> > + mc->init = emcraft_sf2_s2s010_init;
> > + mc->ignore_memory_transaction_failures = true;
>
> Please don't set ignore_memory_transaction_failures in new boards.
> This is a legacy-old-code-only flag.
>
> New boards should define enough devices, either properly
> or using create_unimplemented_device(), to make whatever code
> they're being tested against run.
>
> This is a firm requirement for this code to go into master,
> because once we let a board in with the flag set it's almost
> impossible to clear it because we don't know what guest
> code that previously worked on the board will now break.
>
Ok. I am working on it and will send next spin with this fix.
Thanks,
Sundeep
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block
2017-09-14 4:36 ` Philippe Mathieu-Daudé
2017-09-14 13:13 ` Peter Maydell
2017-09-14 15:34 ` sundeep subbaraya
@ 2017-09-17 23:57 ` Philippe Mathieu-Daudé
2017-09-18 6:29 ` sundeep subbaraya
2 siblings, 1 reply; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-09-17 23:57 UTC (permalink / raw)
To: Subbaraya Sundeep
Cc: qemu-devel, qemu-arm, peter.maydell, alistair23, crosthwaite.peter
Hi Sundeep,
On 09/14/2017 01:36 AM, Philippe Mathieu-Daudé wrote:
> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
[...]
>> +static inline int msf2_divbits(uint32_t div)
>
> Please directly use ctz32() instead of msf2_divbits()
It seems you missed this review comment in your v9.
>
>> +{
>> + int ret = 0;
>> +
>> + switch (div) {
>> + case 1:
>> + ret = 0;
>> + break;
>> + case 2:
>> + ret = 1;
>> + break;
>> + case 4:
>> + ret = 2;
>> + break;
>> + case 8:
>> + ret = 4;
>> + break;
>> + case 16:
>> + ret = 5;
>> + break;
>> + case 32:
>> + ret = 6;
>> + break;
>> + default:
>> + break;
>> + }
>> +
>> + return ret;
>> +}
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block
2017-09-17 23:57 ` Philippe Mathieu-Daudé
@ 2017-09-18 6:29 ` sundeep subbaraya
0 siblings, 0 replies; 28+ messages in thread
From: sundeep subbaraya @ 2017-09-18 6:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Alistair Francis,
Peter Crosthwaite
Hi Philippe,
On Mon, Sep 18, 2017 at 5:27 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Sundeep,
>
> On 09/14/2017 01:36 AM, Philippe Mathieu-Daudé wrote:
>
>> On 09/07/2017 04:24 PM, Subbaraya Sundeep wrote:
>>
> [...]
>
>> +static inline int msf2_divbits(uint32_t div)
>>>
>>
>> Please directly use ctz32() instead of msf2_divbits()
>>
>
> It seems you missed this review comment in your v9.
ctz32(1) = 0
ctz32(2) = 1
ctz32(4) = 2
ctz32(8) = 3
ctz32(16) = 4
ctz32(32) = 5
but for inputs 8,16,32 output should be 4,5,6 so didn't use ctz32().
I replied to this comment in the same mail chain earlier. Please check.
Thanks,
Sundeep
>
>
>
>> +{
>>> + int ret = 0;
>>> +
>>> + switch (div) {
>>> + case 1:
>>> + ret = 0;
>>> + break;
>>> + case 2:
>>> + ret = 1;
>>> + break;
>>> + case 4:
>>> + ret = 2;
>>> + break;
>>> + case 8:
>>> + ret = 4;
>>> + break;
>>> + case 16:
>>> + ret = 5;
>>> + break;
>>> + case 32:
>>> + ret = 6;
>>> + break;
>>> + default:
>>> + break;
>>> + }
>>> +
>>> + return ret;
>>> +}
>>>
>>
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2017-09-18 6:29 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-07 19:24 [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
2017-09-14 4:36 ` Philippe Mathieu-Daudé
2017-09-14 13:13 ` Peter Maydell
2017-09-14 15:30 ` sundeep subbaraya
2017-09-14 18:05 ` Philippe Mathieu-Daudé
2017-09-14 15:34 ` sundeep subbaraya
2017-09-17 23:57 ` Philippe Mathieu-Daudé
2017-09-18 6:29 ` sundeep subbaraya
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
2017-09-12 23:50 ` Alistair Francis
2017-09-13 2:21 ` sundeep subbaraya
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
2017-09-07 21:38 ` Philippe Mathieu-Daudé
2017-09-08 7:26 ` sundeep subbaraya
2017-09-13 9:21 ` sundeep subbaraya
2017-09-13 17:07 ` sundeep subbaraya
2017-09-13 17:24 ` Philippe Mathieu-Daudé
2017-09-07 19:24 ` [Qemu-devel] [Qemu devel v8 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
2017-09-14 17:14 ` Peter Maydell
2017-09-14 17:45 ` Philippe Mathieu-Daudé
2017-09-15 6:31 ` sundeep subbaraya
2017-09-07 21:44 ` [Qemu-devel] [Qemu devel v8 PATCH 0/5] Add support for Smartfusion2 SoC Philippe Mathieu-Daudé
2017-09-08 7:24 ` sundeep subbaraya
2017-09-14 4:10 ` Philippe Mathieu-Daudé
2017-09-14 17:06 ` Alistair Francis
2017-09-14 17:17 ` Peter Maydell
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