From: "Souza, Jose" <jose.souza@intel.com> To: "Roper, Matthew D" <matthew.d.roper@intel.com> Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org> Subject: Re: [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation Date: Tue, 12 Nov 2019 18:30:22 +0000 [thread overview] Message-ID: <f61fa8c2035fdf13b6c577bbffc7c3e943108e36.camel@intel.com> (raw) In-Reply-To: <20191112171657.GK21445@mdroper-desk1.amr.corp.intel.com> On Tue, 2019-11-12 at 09:16 -0800, Matt Roper wrote: > On Tue, Nov 05, 2019 at 05:45:00PM -0800, José Roberto de Souza > wrote: > > PSR2 HW only support a limited number of bits per pixel, if mode > > has > > more than supported PSR2 should not be enabled. > > > > BSpec: 50422 > > BSpec: 7713 > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index c1d133362b76..0d84ea28bc6f 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; > > int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; > > - int psr_max_h = 0, psr_max_v = 0; > > + int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; > > > > if (!dev_priv->psr.sink_psr2_support) > > return false; > > @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > if (INTEL_GEN(dev_priv) >= 12) { > > psr_max_h = 5120; > > psr_max_v = 3200; > > + max_bpp = 30; > > } else if (INTEL_GEN(dev_priv) >= 10 || > > IS_GEMINILAKE(dev_priv)) { > > psr_max_h = 4096; > > psr_max_v = 2304; > > + max_bpp = 24; > > } else if (IS_GEN(dev_priv, 9)) { > > psr_max_h = 3640; > > psr_max_v = 2304; > > + max_bpp = 24; > > } > > > > if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { > > @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > return false; > > } > > > > + if (crtc_state->pipe_bpp > max_bpp) { > > + DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max > > supported %d\n", > > + crtc_state->pipe_bpp, max_bpp); > > + return false; > > + } > > The wording of the bspec is "PSR2 is limited to 30bpp 10:10:10" and > "PSR2 is limited to 24bpp 8:8:8" --- that wording makes it sound like > you need to use that one specific mode rather than it being an upper > limit? I.e., do we need an == test here rather than >? It works with lower than the limit: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7312/shard-tglb4/igt@kms_psr2_su@frontbuffer.html https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7309/shard-iclb2/igt@kms_psr@psr2_basic.html But I agree with you, BSpec should have "limited up to Xbpp", going toopen a issue. > > > Matt > > > + > > /* > > * HW sends SU blocks of size four scan lines, which means the > > starting > > * X coordinate and Y granularity requirements will always be > > met. We > > -- > > 2.24.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: "Souza, Jose" <jose.souza@intel.com> To: "Roper, Matthew D" <matthew.d.roper@intel.com> Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation Date: Tue, 12 Nov 2019 18:30:22 +0000 [thread overview] Message-ID: <f61fa8c2035fdf13b6c577bbffc7c3e943108e36.camel@intel.com> (raw) Message-ID: <20191112183022.8IT7IAJzIS9PKXOGIWLsSacd6IvhaM0wsa8cfoVXnhQ@z> (raw) In-Reply-To: <20191112171657.GK21445@mdroper-desk1.amr.corp.intel.com> On Tue, 2019-11-12 at 09:16 -0800, Matt Roper wrote: > On Tue, Nov 05, 2019 at 05:45:00PM -0800, José Roberto de Souza > wrote: > > PSR2 HW only support a limited number of bits per pixel, if mode > > has > > more than supported PSR2 should not be enabled. > > > > BSpec: 50422 > > BSpec: 7713 > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index c1d133362b76..0d84ea28bc6f 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; > > int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; > > - int psr_max_h = 0, psr_max_v = 0; > > + int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; > > > > if (!dev_priv->psr.sink_psr2_support) > > return false; > > @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > if (INTEL_GEN(dev_priv) >= 12) { > > psr_max_h = 5120; > > psr_max_v = 3200; > > + max_bpp = 30; > > } else if (INTEL_GEN(dev_priv) >= 10 || > > IS_GEMINILAKE(dev_priv)) { > > psr_max_h = 4096; > > psr_max_v = 2304; > > + max_bpp = 24; > > } else if (IS_GEN(dev_priv, 9)) { > > psr_max_h = 3640; > > psr_max_v = 2304; > > + max_bpp = 24; > > } > > > > if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { > > @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > return false; > > } > > > > + if (crtc_state->pipe_bpp > max_bpp) { > > + DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max > > supported %d\n", > > + crtc_state->pipe_bpp, max_bpp); > > + return false; > > + } > > The wording of the bspec is "PSR2 is limited to 30bpp 10:10:10" and > "PSR2 is limited to 24bpp 8:8:8" --- that wording makes it sound like > you need to use that one specific mode rather than it being an upper > limit? I.e., do we need an == test here rather than >? It works with lower than the limit: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7312/shard-tglb4/igt@kms_psr2_su@frontbuffer.html https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7309/shard-iclb2/igt@kms_psr@psr2_basic.html But I agree with you, BSpec should have "limited up to Xbpp", going toopen a issue. > > > Matt > > > + > > /* > > * HW sends SU blocks of size four scan lines, which means the > > starting > > * X coordinate and Y granularity requirements will always be > > met. We > > -- > > 2.24.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-12 18:30 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-06 1:45 [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation José Roberto de Souza 2019-11-06 1:45 ` [Intel-gfx] " José Roberto de Souza 2019-11-06 1:45 ` [PATCH 2/5] drm/i915/psr: Refactor psr short pulse handler José Roberto de Souza 2019-11-06 1:45 ` [Intel-gfx] " José Roberto de Souza 2019-11-12 17:31 ` Matt Roper 2019-11-12 17:31 ` [Intel-gfx] " Matt Roper 2019-11-06 1:45 ` [PATCH 3/5] drm/i915/psr: Enable ALPM lock timeout error interruption José Roberto de Souza 2019-11-06 1:45 ` [Intel-gfx] " José Roberto de Souza 2019-11-06 1:45 ` [PATCH 4/5] drm/i915/psr: Check if sink PSR capability changed José Roberto de Souza 2019-11-06 1:45 ` [Intel-gfx] " José Roberto de Souza 2019-11-06 1:45 ` [PATCH 5/5] drm/i915/vbt: Parse power conservation features block José Roberto de Souza 2019-11-06 1:45 ` [Intel-gfx] " José Roberto de Souza 2019-11-12 21:21 ` Matt Roper 2019-11-12 21:21 ` [Intel-gfx] " Matt Roper 2019-11-12 23:56 ` Souza, Jose 2019-11-12 23:56 ` [Intel-gfx] " Souza, Jose 2019-11-26 0:47 ` Souza, Jose 2019-11-26 0:47 ` [Intel-gfx] " Souza, Jose 2019-11-27 18:02 ` Matt Roper 2019-11-27 18:02 ` [Intel-gfx] " Matt Roper 2019-11-27 22:48 ` Souza, Jose 2019-11-27 22:48 ` [Intel-gfx] " Souza, Jose 2019-11-06 2:27 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/psr: Add bits per pixel limitation Patchwork 2019-11-06 2:27 ` [Intel-gfx] " Patchwork 2019-11-06 23:24 ` ✓ Fi.CI.IGT: " Patchwork 2019-11-06 23:24 ` [Intel-gfx] " Patchwork 2019-11-12 17:16 ` [PATCH 1/5] " Matt Roper 2019-11-12 17:16 ` [Intel-gfx] " Matt Roper 2019-11-12 18:30 ` Souza, Jose [this message] 2019-11-12 18:30 ` Souza, Jose 2019-11-13 19:15 ` Lucas De Marchi 2019-11-13 19:15 ` [Intel-gfx] " Lucas De Marchi 2019-11-13 19:12 ` Lucas De Marchi 2019-11-13 19:12 ` [Intel-gfx] " Lucas De Marchi
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