[RFC v3 00/28] Implicit dev_priv removal and GT compartmentalization

[RFC v3 00/28] Implicit dev_priv removal and GT compartmentalization

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This time round series still starts with some implicit dev_priv removal, but
after in the following round the feedback was to not go with intel_uncore but
introduce intel_gt, most patches have been reworked to reflect this.

Also, while nosing around in the code I have spotted more opportunities to
compartmentalize, either using intel_gt, or some other object as appropriate.

This should overall help with making the GT and display split inside struct
drm_i915_private clearer.

Tvrtko Ursulin (28):
  drm/i915: Convert intel_vgt_(de)balloon to uncore
  drm/i915: Introduce struct intel_gt as replacement for anonymous
    i915->gt
  drm/i915: Move intel_gt initialization to a separate file
  drm/i915: Store some backpointers in struct intel_gt
  drm/i915: Make i915_check_and_clear_faults take intel_gt
  drm/i915: Convert i915_gem_init_swizzling to intel_gt
  drm/i915: Convert init_unused_rings to intel_gt
  drm/i915: Convert gt workarounds to intel_gt
  drm/i915: Store backpointer to intel_gt in the engine
  drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt
  drm/i915: Convert i915_ppgtt_init_hw to intel_gt
  drm/i915: Consolidate some open coded mmio rmw
  drm/i915: Convert i915_gem_init_hw to intel_gt
  drm/i915: Move intel_engines_resume into common init
  drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw
  drm/i915: Compartmentalize i915_ggtt_probe_hw
  drm/i915: Compartmentalize i915_ggtt_init_hw
  drm/i915: Make ggtt invalidation work on ggtt
  drm/i915: Store intel_gt backpointer in vm
  drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings
  drm/i915/gtt: Reduce source verbosity by caching repeated dereferences
  drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt
  drm/i915: Compartmentalize timeline_init/park/fini
  drm/i915: Compartmentalize i915_ggtt_cleanup_hw
  drm/i915: Compartmentalize i915_gem_init_ggtt
  drm/i915: Store ggtt pointer in intel_gt
  drm/i915: Compartmentalize ring buffer creation
  drm/i915: Make timelines gt centric

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |   2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c    |   5 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c    |   3 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  13 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h  |   2 +
 drivers/gpu/drm/i915/gt/intel_gt.c            | 231 +++++++
 drivers/gpu/drm/i915/gt/intel_gt.h            |  25 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h      |  69 ++
 drivers/gpu/drm/i915/gt/intel_lrc.c           |   9 +-
 drivers/gpu/drm/i915/gt/intel_mocs.c          |  52 +-
 drivers/gpu/drm/i915/gt/intel_mocs.h          |   3 +-
 drivers/gpu/drm/i915/gt/intel_reset.c         | 126 +---
 drivers/gpu/drm/i915/gt/intel_reset.h         |   2 -
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c    |  19 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  10 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.h   |   6 +-
 drivers/gpu/drm/i915/gt/mock_engine.c         |   4 +-
 drivers/gpu/drm/i915/i915_drv.c               |   7 +-
 drivers/gpu/drm/i915/i915_drv.h               |  45 +-
 drivers/gpu/drm/i915/i915_gem.c               | 197 +++---
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 601 ++++++++++--------
 drivers/gpu/drm/i915/i915_gem_gtt.h           |   6 +-
 drivers/gpu/drm/i915/i915_timeline.c          | 110 ++--
 drivers/gpu/drm/i915/i915_timeline.h          |   7 +-
 drivers/gpu/drm/i915/i915_timeline_types.h    |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c              |  24 +-
 drivers/gpu/drm/i915/i915_vgpu.h              |   4 +-
 drivers/gpu/drm/i915/i915_vma.c               |   3 +-
 drivers/gpu/drm/i915/intel_wopcm.c            |  31 +-
 drivers/gpu/drm/i915/intel_wopcm.h            |   4 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |   2 +-
 .../gpu/drm/i915/selftests/i915_timeline.c    |   8 +-
 .../gpu/drm/i915/selftests/mock_timeline.c    |   2 +-
 34 files changed, 954 insertions(+), 681 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_types.h

-- 
2.20.1

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[RFC 01/28] drm/i915: Convert intel_vgt_(de)balloon to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Furthermore these calls really operate on ggtt so it logically makes sense
if they take it as parameter.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 ++--
 drivers/gpu/drm/i915/i915_vgpu.c    | 24 ++++++++++++++----------
 drivers/gpu/drm/i915/i915_vgpu.h    |  4 ++--
 3 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7be72388b052..90d9669ff313 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2859,7 +2859,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
 			       intel_wopcm_guc_size(&dev_priv->wopcm));
 
-	ret = intel_vgt_balloon(dev_priv);
+	ret = intel_vgt_balloon(ggtt);
 	if (ret)
 		return ret;
 
@@ -2930,7 +2930,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 	ggtt_release_guc_top(ggtt);
 
 	if (drm_mm_initialized(&ggtt->vm.mm)) {
-		intel_vgt_deballoon(dev_priv);
+		intel_vgt_deballoon(ggtt);
 		i915_address_space_fini(&ggtt->vm);
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 94d3992b599d..41ed9a3f52b4 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -117,17 +117,17 @@ static void vgt_deballoon_space(struct i915_ggtt *ggtt,
  * This function is called to deallocate the ballooned-out graphic memory, when
  * driver is unloaded or when ballooning fails.
  */
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
+void intel_vgt_deballoon(struct i915_ggtt *ggtt)
 {
 	int i;
 
-	if (!intel_vgpu_active(dev_priv))
+	if (!intel_vgpu_active(ggtt->vm.i915))
 		return;
 
 	DRM_DEBUG("VGT deballoon.\n");
 
 	for (i = 0; i < 4; i++)
-		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
+		vgt_deballoon_space(ggtt, &bl_info.space[i]);
 }
 
 static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -195,22 +195,26 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt,
  * Returns:
  * zero on success, non-zero if configuration invalid or ballooning failed
  */
-int intel_vgt_balloon(struct drm_i915_private *dev_priv)
+int intel_vgt_balloon(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
 	unsigned long ggtt_end = ggtt->vm.total;
 
 	unsigned long mappable_base, mappable_size, mappable_end;
 	unsigned long unmappable_base, unmappable_size, unmappable_end;
 	int ret;
 
-	if (!intel_vgpu_active(dev_priv))
+	if (!intel_vgpu_active(ggtt->vm.i915))
 		return 0;
 
-	mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
-	mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
-	unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
-	unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
+	mappable_base =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
+	mappable_size =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
+	unmappable_base =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
+	unmappable_size =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
 
 	mappable_end = mappable_base + mappable_size;
 	unmappable_end = unmappable_base + unmappable_size;
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index ebe1b7bced98..e918f418503f 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,7 +42,7 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
 }
 
-int intel_vgt_balloon(struct drm_i915_private *dev_priv);
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
+int intel_vgt_balloon(struct i915_ggtt *ggtt);
+void intel_vgt_deballoon(struct i915_ggtt *ggtt);
 
 #endif /* _I915_VGPU_H_ */
-- 
2.20.1

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[RFC 02/28] drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We have long been slighlty annoyed by the anonymous i915->gt.

Promote it to a separate structure and give it its own header.

This is a first step towards cleaning up the separation between i915 and gt.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 61 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h          | 42 +---------------
 2 files changed, 63 insertions(+), 40 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_types.h

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
new file mode 100644
index 000000000000..cf32ca401b74
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -0,0 +1,61 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_GT_TYPES__
+#define __INTEL_GT_TYPES__
+
+#include <linux/ktime.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/notifier.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include "i915_vma.h"
+#include "intel_wakeref.h"
+
+struct intel_gt {
+	struct i915_gt_timelines {
+		struct mutex mutex; /* protects list, tainted by GPU */
+		struct list_head active_list;
+
+		/* Pack multiple timelines' seqnos into the same page */
+		spinlock_t hwsp_lock;
+		struct list_head hwsp_free_list;
+	} timelines;
+
+	struct list_head active_rings;
+
+	struct intel_wakeref wakeref;
+
+	struct list_head closed_vma;
+	spinlock_t closed_lock; /* guards the list of closed_vma */
+
+	/**
+	 * Is the GPU currently considered idle, or busy executing
+	 * userspace requests? Whilst idle, we allow runtime power
+	 * management to power down the hardware and display clocks.
+	 * In order to reduce the effect on performance, there
+	 * is a slight delay before we do so.
+	 */
+	intel_wakeref_t awake;
+
+	struct blocking_notifier_head pm_notifications;
+
+	ktime_t last_init_time;
+
+	struct i915_vma *scratch;
+
+	/*
+	 * We must never wait on the GPU while holding a lock as we
+	 * may need to perform a GPU reset. So while we don't need to
+	 * serialise wait/reset with an explicit lock, we do want
+	 * lockdep to detect potential dependency cycles.
+	 */
+	struct lockdep_map reset_lockmap;
+};
+
+#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90d94d904e65..e2c8813c9355 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -65,6 +65,7 @@
 
 #include "gt/intel_lrc.h"
 #include "gt/intel_engine.h"
+#include "gt/intel_gt_types.h"
 #include "gt/intel_workarounds.h"
 
 #include "intel_bios.h"
@@ -1870,46 +1871,7 @@ struct drm_i915_private {
 	} perf;
 
 	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
-	struct {
-		struct i915_gt_timelines {
-			struct mutex mutex; /* protects list, tainted by GPU */
-			struct list_head active_list;
-
-			/* Pack multiple timelines' seqnos into the same page */
-			spinlock_t hwsp_lock;
-			struct list_head hwsp_free_list;
-		} timelines;
-
-		struct list_head active_rings;
-
-		struct intel_wakeref wakeref;
-
-		struct list_head closed_vma;
-		spinlock_t closed_lock; /* guards the list of closed_vma */
-
-		/**
-		 * Is the GPU currently considered idle, or busy executing
-		 * userspace requests? Whilst idle, we allow runtime power
-		 * management to power down the hardware and display clocks.
-		 * In order to reduce the effect on performance, there
-		 * is a slight delay before we do so.
-		 */
-		intel_wakeref_t awake;
-
-		struct blocking_notifier_head pm_notifications;
-
-		ktime_t last_init_time;
-
-		struct i915_vma *scratch;
-
-		/*
-		 * We must never wait on the GPU while holding a lock as we
-		 * may need to perform a GPU reset. So while we don't need to
-		 * serialise wait/reset with an explicit lock, we do want
-		 * lockdep to detect potential dependency cycles.
-		 */
-		struct lockdep_map reset_lockmap;
-	} gt;
+	struct intel_gt gt;
 
 	struct {
 		struct notifier_block pm_notifier;
-- 
2.20.1

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[RFC 03/28] drm/i915: Move intel_gt initialization to a separate file

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

As it will grow in a following patch make a new home for it.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Makefile      |  1 +
 drivers/gpu/drm/i915/gt/intel_gt.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h | 14 ++++++++++++++
 drivers/gpu/drm/i915/i915_gem.c    |  9 ++-------
 4 files changed, 36 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c0a7b2994077..8df1bf2855d0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -73,6 +73,7 @@ gt-y += \
 	gt/intel_context.o \
 	gt/intel_engine_cs.o \
 	gt/intel_engine_pm.o \
+	gt/intel_gt.o \
 	gt/intel_gt_pm.o \
 	gt/intel_hangcheck.o \
 	gt/intel_lrc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
new file mode 100644
index 000000000000..e91ffd2dc4fa
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -0,0 +1,19 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_gt.h"
+
+void intel_gt_init(struct intel_gt *gt)
+{
+	static struct lock_class_key reset_key;
+
+	INIT_LIST_HEAD(&gt->active_rings);
+	INIT_LIST_HEAD(&gt->closed_vma);
+
+	spin_lock_init(&gt->closed_lock);
+
+	lockdep_init_map(&gt->reset_lockmap, "i915.reset", &reset_key, 0);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
new file mode 100644
index 000000000000..d0b599dd6d0f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_GT__
+#define __INTEL_GT__
+
+#include "gt/intel_gt_types.h"
+
+void intel_gt_init(struct intel_gt *gt);
+
+#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4bbded4aa936..d5897e13897b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -44,6 +44,7 @@
 #include "gem/i915_gem_pm.h"
 #include "gem/i915_gemfs.h"
 #include "gt/intel_engine_pm.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_mocs.h"
 #include "gt/intel_reset.h"
@@ -1746,17 +1747,11 @@ static void i915_gem_init__mm(struct drm_i915_private *i915)
 
 int i915_gem_init_early(struct drm_i915_private *dev_priv)
 {
-	static struct lock_class_key reset_key;
 	int err;
 
+	intel_gt_init(&dev_priv->gt);
 	intel_gt_pm_init(dev_priv);
 
-	INIT_LIST_HEAD(&dev_priv->gt.active_rings);
-	INIT_LIST_HEAD(&dev_priv->gt.closed_vma);
-	spin_lock_init(&dev_priv->gt.closed_lock);
-	lockdep_init_map(&dev_priv->gt.reset_lockmap,
-			 "i915.reset", &reset_key, 0);
-
 	i915_gem_init__mm(dev_priv);
 	i915_gem_init__pm(dev_priv);
 
-- 
2.20.1

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[RFC 04/28] drm/i915: Store some backpointers in struct intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We need an easy way to get back to i915 and uncore.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c       | 7 ++++++-
 drivers/gpu/drm/i915/gt/intel_gt.h       | 4 +++-
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 6 ++++++
 drivers/gpu/drm/i915/i915_gem.c          | 2 +-
 4 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index e91ffd2dc4fa..29e8dc766ba4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -4,12 +4,17 @@
  * Copyright © 2019 Intel Corporation
  */
 
+#include "i915_drv.h"
+
 #include "intel_gt.h"
 
-void intel_gt_init(struct intel_gt *gt)
+void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
 {
 	static struct lock_class_key reset_key;
 
+	gt->i915 = i915;
+	gt->uncore = &i915->uncore;
+
 	INIT_LIST_HEAD(&gt->active_rings);
 	INIT_LIST_HEAD(&gt->closed_vma);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index d0b599dd6d0f..f57ff3758f54 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -9,6 +9,8 @@
 
 #include "gt/intel_gt_types.h"
 
-void intel_gt_init(struct intel_gt *gt);
+struct drm_i915_private;
+
+void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
 
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index cf32ca401b74..99e30f8cfbe0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -17,7 +17,13 @@
 #include "i915_vma.h"
 #include "intel_wakeref.h"
 
+struct drm_i915_private;
+struct intel_uncore;
+
 struct intel_gt {
+	struct drm_i915_private *i915;
+	struct intel_uncore *uncore;
+
 	struct i915_gt_timelines {
 		struct mutex mutex; /* protects list, tainted by GPU */
 		struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d5897e13897b..7fdf252f9322 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1749,7 +1749,7 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
 {
 	int err;
 
-	intel_gt_init(&dev_priv->gt);
+	intel_gt_init(&dev_priv->gt, dev_priv);
 	intel_gt_pm_init(dev_priv);
 
 	i915_gem_init__mm(dev_priv);
-- 
2.20.1

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[RFC 05/28] drm/i915: Make i915_check_and_clear_faults take intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing the conversion and elimination of implicit dev_priv.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.c        | 129 ++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h        |   5 +
 drivers/gpu/drm/i915/gt/intel_reset.c     | 126 +--------------------
 drivers/gpu/drm/i915/gt/intel_reset.h     |   2 -
 drivers/gpu/drm/i915/i915_drv.c           |   3 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c       |   6 +-
 7 files changed, 145 insertions(+), 130 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c0d986db5a75..35a9f754bcb9 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -28,6 +28,8 @@
 
 #include "i915_drv.h"
 
+#include "gt/intel_gt.h"
+
 #include "intel_engine.h"
 #include "intel_engine_pm.h"
 #include "intel_context.h"
@@ -453,7 +455,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
 
 	RUNTIME_INFO(i915)->num_engines = hweight32(mask);
 
-	i915_check_and_clear_faults(i915);
+	intel_gt_check_and_clear_faults(&i915->gt);
 
 	intel_setup_engine_capabilities(i915);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 29e8dc766ba4..58efcdd78119 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -7,6 +7,7 @@
 #include "i915_drv.h"
 
 #include "intel_gt.h"
+#include "intel_uncore.h"
 
 void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
 {
@@ -22,3 +23,131 @@ void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
 
 	lockdep_init_map(&gt->reset_lockmap, "i915.reset", &reset_key, 0);
 }
+
+static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
+{
+	intel_uncore_rmw(uncore, reg, 0, set);
+}
+
+static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
+{
+	intel_uncore_rmw(uncore, reg, clr, 0);
+}
+
+static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
+{
+	intel_uncore_rmw(uncore, reg, 0, 0);
+}
+
+static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
+{
+	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+	GEN6_RING_FAULT_REG_POSTING_READ(engine);
+}
+
+void
+intel_gt_clear_error_registers(struct intel_gt *gt,
+			       intel_engine_mask_t engine_mask)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
+	u32 eir;
+
+	if (!IS_GEN(i915, 2))
+		clear_register(uncore, PGTBL_ER);
+
+	if (INTEL_GEN(i915) < 4)
+		clear_register(uncore, IPEIR(RENDER_RING_BASE));
+	else
+		clear_register(uncore, IPEIR_I965);
+
+	clear_register(uncore, EIR);
+	eir = intel_uncore_read(uncore, EIR);
+	if (eir) {
+		/*
+		 * some errors might have become stuck,
+		 * mask them.
+		 */
+		DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
+		rmw_set(uncore, EMR, eir);
+		intel_uncore_write(uncore, GEN2_IIR,
+				   I915_MASTER_ERROR_INTERRUPT);
+	}
+
+	if (INTEL_GEN(i915) >= 8) {
+		rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
+		intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
+	} else if (INTEL_GEN(i915) >= 6) {
+		struct intel_engine_cs *engine;
+		enum intel_engine_id id;
+
+		for_each_engine_masked(engine, i915, engine_mask, id)
+			gen8_clear_engine_error_register(engine);
+	}
+}
+
+static void gen6_check_faults(struct intel_gt *gt)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	u32 fault;
+
+	for_each_engine(engine, gt->i915, id) {
+		fault = GEN6_RING_FAULT_REG_READ(engine);
+		if (fault & RING_FAULT_VALID) {
+			DRM_DEBUG_DRIVER("Unexpected fault\n"
+					 "\tAddr: 0x%08lx\n"
+					 "\tAddress space: %s\n"
+					 "\tSource ID: %d\n"
+					 "\tType: %d\n",
+					 fault & PAGE_MASK,
+					 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
+					 RING_FAULT_SRCID(fault),
+					 RING_FAULT_FAULT_TYPE(fault));
+		}
+	}
+}
+
+static void gen8_check_faults(struct intel_gt *gt)
+{
+	struct intel_uncore *uncore = gt->uncore;
+	u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
+
+	if (fault & RING_FAULT_VALID) {
+		u32 fault_data0, fault_data1;
+		u64 fault_addr;
+
+		fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);
+		fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);
+		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+			     ((u64)fault_data0 << 12);
+
+		DRM_DEBUG_DRIVER("Unexpected fault\n"
+				 "\tAddr: 0x%08x_%08x\n"
+				 "\tAddress space: %s\n"
+				 "\tEngine ID: %d\n"
+				 "\tSource ID: %d\n"
+				 "\tType: %d\n",
+				 upper_32_bits(fault_addr),
+				 lower_32_bits(fault_addr),
+				 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+				 GEN8_RING_FAULT_ENGINE_ID(fault),
+				 RING_FAULT_SRCID(fault),
+				 RING_FAULT_FAULT_TYPE(fault));
+	}
+}
+
+void intel_gt_check_and_clear_faults(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+
+	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
+	if (INTEL_GEN(i915) >= 8)
+		gen8_check_faults(gt);
+	else if (INTEL_GEN(i915) >= 6)
+		gen6_check_faults(gt);
+	else
+		return;
+
+	intel_gt_clear_error_registers(gt, ALL_ENGINES);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index f57ff3758f54..d4f585151527 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -7,10 +7,15 @@
 #ifndef __INTEL_GT__
 #define __INTEL_GT__
 
+#include "gt/intel_engine_types.h"
 #include "gt/intel_gt_types.h"
 
 struct drm_i915_private;
 
 void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
 
+void intel_gt_check_and_clear_faults(struct intel_gt *gt);
+void intel_gt_clear_error_registers(struct intel_gt *gt,
+				    intel_engine_mask_t engine_mask);
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 8ba7af8b7ced..c786ac5d47d1 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -13,6 +13,7 @@
 #include "i915_gpu_error.h"
 #include "i915_irq.h"
 #include "intel_engine_pm.h"
+#include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_reset.h"
 
@@ -24,16 +25,6 @@
 /* XXX How to handle concurrent GGTT updates using tiling registers? */
 #define RESET_UNDER_STOP_MACHINE 0
 
-static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
-{
-	intel_uncore_rmw(uncore, reg, 0, set);
-}
-
-static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
-{
-	intel_uncore_rmw(uncore, reg, clr, 0);
-}
-
 static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 {
 	intel_uncore_rmw_fw(uncore, reg, 0, set);
@@ -1158,119 +1149,6 @@ static void i915_reset_device(struct drm_i915_private *i915,
 		kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
 }
 
-static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
-{
-	intel_uncore_rmw(uncore, reg, 0, 0);
-}
-
-static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
-{
-	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
-	GEN6_RING_FAULT_REG_POSTING_READ(engine);
-}
-
-static void clear_error_registers(struct drm_i915_private *i915,
-				  intel_engine_mask_t engine_mask)
-{
-	struct intel_uncore *uncore = &i915->uncore;
-	u32 eir;
-
-	if (!IS_GEN(i915, 2))
-		clear_register(uncore, PGTBL_ER);
-
-	if (INTEL_GEN(i915) < 4)
-		clear_register(uncore, IPEIR(RENDER_RING_BASE));
-	else
-		clear_register(uncore, IPEIR_I965);
-
-	clear_register(uncore, EIR);
-	eir = intel_uncore_read(uncore, EIR);
-	if (eir) {
-		/*
-		 * some errors might have become stuck,
-		 * mask them.
-		 */
-		DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
-		rmw_set(uncore, EMR, eir);
-		intel_uncore_write(uncore, GEN2_IIR,
-				   I915_MASTER_ERROR_INTERRUPT);
-	}
-
-	if (INTEL_GEN(i915) >= 8) {
-		rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
-		intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
-	} else if (INTEL_GEN(i915) >= 6) {
-		struct intel_engine_cs *engine;
-		enum intel_engine_id id;
-
-		for_each_engine_masked(engine, i915, engine_mask, id)
-			gen8_clear_engine_error_register(engine);
-	}
-}
-
-static void gen6_check_faults(struct drm_i915_private *dev_priv)
-{
-	struct intel_engine_cs *engine;
-	enum intel_engine_id id;
-	u32 fault;
-
-	for_each_engine(engine, dev_priv, id) {
-		fault = GEN6_RING_FAULT_REG_READ(engine);
-		if (fault & RING_FAULT_VALID) {
-			DRM_DEBUG_DRIVER("Unexpected fault\n"
-					 "\tAddr: 0x%08lx\n"
-					 "\tAddress space: %s\n"
-					 "\tSource ID: %d\n"
-					 "\tType: %d\n",
-					 fault & PAGE_MASK,
-					 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
-					 RING_FAULT_SRCID(fault),
-					 RING_FAULT_FAULT_TYPE(fault));
-		}
-	}
-}
-
-static void gen8_check_faults(struct drm_i915_private *dev_priv)
-{
-	u32 fault = I915_READ(GEN8_RING_FAULT_REG);
-
-	if (fault & RING_FAULT_VALID) {
-		u32 fault_data0, fault_data1;
-		u64 fault_addr;
-
-		fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
-		fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
-		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
-			     ((u64)fault_data0 << 12);
-
-		DRM_DEBUG_DRIVER("Unexpected fault\n"
-				 "\tAddr: 0x%08x_%08x\n"
-				 "\tAddress space: %s\n"
-				 "\tEngine ID: %d\n"
-				 "\tSource ID: %d\n"
-				 "\tType: %d\n",
-				 upper_32_bits(fault_addr),
-				 lower_32_bits(fault_addr),
-				 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
-				 GEN8_RING_FAULT_ENGINE_ID(fault),
-				 RING_FAULT_SRCID(fault),
-				 RING_FAULT_FAULT_TYPE(fault));
-	}
-}
-
-void i915_check_and_clear_faults(struct drm_i915_private *i915)
-{
-	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
-	if (INTEL_GEN(i915) >= 8)
-		gen8_check_faults(i915);
-	else if (INTEL_GEN(i915) >= 6)
-		gen6_check_faults(i915);
-	else
-		return;
-
-	clear_error_registers(i915, ALL_ENGINES);
-}
-
 /**
  * i915_handle_error - handle a gpu error
  * @i915: i915 device private
@@ -1319,7 +1197,7 @@ void i915_handle_error(struct drm_i915_private *i915,
 
 	if (flags & I915_ERROR_CAPTURE) {
 		i915_capture_error_state(i915, engine_mask, msg);
-		clear_error_registers(i915, engine_mask);
+		intel_gt_clear_error_registers(&i915->gt, engine_mask);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index 580ebdb59eca..03fba0ab3868 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -25,8 +25,6 @@ void i915_handle_error(struct drm_i915_private *i915,
 		       const char *fmt, ...);
 #define I915_ERROR_CAPTURE BIT(0)
 
-void i915_check_and_clear_faults(struct drm_i915_private *i915);
-
 void i915_reset(struct drm_i915_private *i915,
 		intel_engine_mask_t stalled_mask,
 		const char *reason);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 254f7b7df306..97155c5eb7e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
 
 #include "gem/i915_gem_context.h"
 #include "gem/i915_gem_ioctls.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_reset.h"
 #include "gt/intel_workarounds.h"
@@ -2339,7 +2340,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	intel_uncore_resume_early(&dev_priv->uncore);
 
-	i915_check_and_clear_faults(dev_priv);
+	intel_gt_check_and_clear_faults(&dev_priv->gt);
 
 	if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
 		gen9_sanitize_dc_state(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 90d9669ff313..ac6ed459720e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -35,6 +35,8 @@
 
 #include <drm/i915_drm.h>
 
+#include "gt/intel_gt.h"
+
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
 #include "i915_trace.h"
@@ -2311,7 +2313,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) < 6)
 		return;
 
-	i915_check_and_clear_faults(dev_priv);
+	intel_gt_check_and_clear_faults(&dev_priv->gt);
 
 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
 
@@ -3620,7 +3622,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	struct i915_vma *vma, *vn;
 
-	i915_check_and_clear_faults(dev_priv);
+	intel_gt_check_and_clear_faults(&dev_priv->gt);
 
 	mutex_lock(&ggtt->vm.mutex);
 
-- 
2.20.1

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[RFC 06/28] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Start using the newly introduced struct intel_gt to fuse together correct
logical init flow with uncore for more removal of implicit dev_priv in
mmio access.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 37 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h |  2 ++
 drivers/gpu/drm/i915/i915_drv.c    |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h    |  1 -
 drivers/gpu/drm/i915/i915_gem.c    | 25 +-------------------
 5 files changed, 42 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 58efcdd78119..c6a67393ee72 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -151,3 +151,40 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 
 	intel_gt_clear_error_registers(gt, ALL_ENGINES);
 }
+
+void intel_gt_init_swizzling(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
+
+	if (INTEL_GEN(i915) < 5 ||
+	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+		return;
+
+	intel_uncore_write(uncore,
+			   DISP_ARB_CTL,
+			   intel_uncore_read(uncore, DISP_ARB_CTL) |
+			   DISP_TILE_SURFACE_SWIZZLING);
+
+	if (IS_GEN(i915, 5))
+		return;
+
+	intel_uncore_write(uncore,
+			   TILECTL,
+			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
+
+	if (IS_GEN(i915, 6))
+		intel_uncore_write(uncore,
+				   ARB_MODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
+	else if (IS_GEN(i915, 7))
+		intel_uncore_write(uncore,
+				   ARB_MODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
+	else if (IS_GEN(i915, 8))
+		intel_uncore_write(uncore,
+				   GAMTARBMODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
+	else
+		MISSING_CASE(INTEL_GEN(i915));
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index d4f585151527..e026b2dc1115 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -18,4 +18,6 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt);
 void intel_gt_clear_error_registers(struct intel_gt *gt,
 				    intel_engine_mask_t engine_mask);
 
+void intel_gt_init_swizzling(struct intel_gt *gt);
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 97155c5eb7e1..1df76f7c717e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2935,7 +2935,7 @@ static int intel_runtime_suspend(struct device *kdev)
 
 		intel_uc_resume(dev_priv);
 
-		i915_gem_init_swizzling(dev_priv);
+		intel_gt_init_swizzling(&dev_priv->gt);
 		i915_gem_restore_fences(dev_priv);
 
 		enable_rpm_wakeref_asserts(dev_priv);
@@ -3036,7 +3036,7 @@ static int intel_runtime_resume(struct device *kdev)
 	 * No point of rolling back things in case of an error, as the best
 	 * we can do is to hope that things will still work (and disable RPM).
 	 */
-	i915_gem_init_swizzling(dev_priv);
+	intel_gt_init_swizzling(&dev_priv->gt);
 	i915_gem_restore_fences(dev_priv);
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e2c8813c9355..1eb203fdee60 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2586,7 +2586,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
 void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
 void i915_gem_fini(struct drm_i915_private *dev_priv);
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7fdf252f9322..5c0db934315b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1205,29 +1205,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 	mutex_unlock(&i915->drm.struct_mutex);
 }
 
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
-{
-	if (INTEL_GEN(dev_priv) < 5 ||
-	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
-		return;
-
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-				 DISP_TILE_SURFACE_SWIZZLING);
-
-	if (IS_GEN(dev_priv, 5))
-		return;
-
-	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
-	if (IS_GEN(dev_priv, 6))
-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
-	else if (IS_GEN(dev_priv, 7))
-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
-	else if (IS_GEN(dev_priv, 8))
-		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
-	else
-		BUG();
-}
-
 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
 {
 	I915_WRITE(RING_CTL(base), 0);
@@ -1274,7 +1251,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	/* ...and determine whether they are sticking. */
 	intel_gt_verify_workarounds(dev_priv, "init");
 
-	i915_gem_init_swizzling(dev_priv);
+	intel_gt_init_swizzling(&dev_priv->gt);
 
 	/*
 	 * At least 830 can leave some of the unused rings
-- 
2.20.1

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[RFC 07/28] drm/i915: Convert init_unused_rings to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 42 ++++++++++++++++++---------------
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5c0db934315b..50be1d1d6f34 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1205,28 +1205,32 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 	mutex_unlock(&i915->drm.struct_mutex);
 }
 
-static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
+static void init_unused_ring(struct intel_gt *gt, u32 base)
 {
-	I915_WRITE(RING_CTL(base), 0);
-	I915_WRITE(RING_HEAD(base), 0);
-	I915_WRITE(RING_TAIL(base), 0);
-	I915_WRITE(RING_START(base), 0);
+	struct intel_uncore *uncore = gt->uncore;
+
+	intel_uncore_write(uncore, RING_CTL(base), 0);
+	intel_uncore_write(uncore, RING_HEAD(base), 0);
+	intel_uncore_write(uncore, RING_TAIL(base), 0);
+	intel_uncore_write(uncore, RING_START(base), 0);
 }
 
-static void init_unused_rings(struct drm_i915_private *dev_priv)
+static void init_unused_rings(struct intel_gt *gt)
 {
-	if (IS_I830(dev_priv)) {
-		init_unused_ring(dev_priv, PRB1_BASE);
-		init_unused_ring(dev_priv, SRB0_BASE);
-		init_unused_ring(dev_priv, SRB1_BASE);
-		init_unused_ring(dev_priv, SRB2_BASE);
-		init_unused_ring(dev_priv, SRB3_BASE);
-	} else if (IS_GEN(dev_priv, 2)) {
-		init_unused_ring(dev_priv, SRB0_BASE);
-		init_unused_ring(dev_priv, SRB1_BASE);
-	} else if (IS_GEN(dev_priv, 3)) {
-		init_unused_ring(dev_priv, PRB1_BASE);
-		init_unused_ring(dev_priv, PRB2_BASE);
+	struct drm_i915_private *i915 = gt->i915;
+
+	if (IS_I830(i915)) {
+		init_unused_ring(gt, PRB1_BASE);
+		init_unused_ring(gt, SRB0_BASE);
+		init_unused_ring(gt, SRB1_BASE);
+		init_unused_ring(gt, SRB2_BASE);
+		init_unused_ring(gt, SRB3_BASE);
+	} else if (IS_GEN(i915, 2)) {
+		init_unused_ring(gt, SRB0_BASE);
+		init_unused_ring(gt, SRB1_BASE);
+	} else if (IS_GEN(i915, 3)) {
+		init_unused_ring(gt, PRB1_BASE);
+		init_unused_ring(gt, PRB2_BASE);
 	}
 }
 
@@ -1259,7 +1263,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	 * will prevent c3 entry. Makes sure all unused rings
 	 * are totally idle.
 	 */
-	init_unused_rings(dev_priv);
+	init_unused_rings(&dev_priv->gt);
 
 	BUG_ON(!dev_priv->kernel_context);
 	ret = i915_terminally_wedged(dev_priv);
-- 
2.20.1

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[RFC 08/28] drm/i915: Convert gt workarounds to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More conversion of i915_gem_init_hw to uncore.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++-----
 drivers/gpu/drm/i915/gt/intel_workarounds.h |  6 +++---
 drivers/gpu/drm/i915/i915_gem.c             |  4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 165b0a45e009..0b3308e39a17 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -6,6 +6,7 @@
 
 #include "i915_drv.h"
 #include "intel_context.h"
+#include "intel_gt.h"
 #include "intel_workarounds.h"
 
 /**
@@ -984,9 +985,9 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 	spin_unlock_irqrestore(&uncore->lock, flags);
 }
 
-void intel_gt_apply_workarounds(struct drm_i915_private *i915)
+void intel_gt_apply_workarounds(struct intel_gt *gt)
 {
-	wa_list_apply(&i915->uncore, &i915->gt_wa_list);
+	wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
 }
 
 static bool wa_list_verify(struct intel_uncore *uncore,
@@ -1005,10 +1006,9 @@ static bool wa_list_verify(struct intel_uncore *uncore,
 	return ok;
 }
 
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-				 const char *from)
+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
 {
-	return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
+	return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.h b/drivers/gpu/drm/i915/gt/intel_workarounds.h
index 3761a6ee58bb..8c9c769c2204 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.h
@@ -14,6 +14,7 @@
 struct drm_i915_private;
 struct i915_request;
 struct intel_engine_cs;
+struct intel_gt;
 
 static inline void intel_wa_list_free(struct i915_wa_list *wal)
 {
@@ -25,9 +26,8 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);
 int intel_engine_emit_ctx_wa(struct i915_request *rq);
 
 void intel_gt_init_workarounds(struct drm_i915_private *i915);
-void intel_gt_apply_workarounds(struct drm_i915_private *i915);
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-				 const char *from);
+void intel_gt_apply_workarounds(struct intel_gt *gt);
+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from);
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine);
 void intel_engine_apply_whitelist(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 50be1d1d6f34..27d93fc8d20b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1251,9 +1251,9 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
 	/* Apply the GT workarounds... */
-	intel_gt_apply_workarounds(dev_priv);
+	intel_gt_apply_workarounds(&dev_priv->gt);
 	/* ...and determine whether they are sticking. */
-	intel_gt_verify_workarounds(dev_priv, "init");
+	intel_gt_verify_workarounds(&dev_priv->gt, "init");
 
 	intel_gt_init_swizzling(&dev_priv->gt);
 
-- 
2.20.1

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[RFC 09/28] drm/i915: Store backpointer to intel_gt in the engine

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

It will come useful in the next patch.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 1 +
 drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 35a9f754bcb9..c2d87c50dd6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -316,6 +316,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
 	engine->id = id;
 	engine->mask = BIT(id);
 	engine->i915 = dev_priv;
+	engine->gt = &dev_priv->gt;
 	engine->uncore = &dev_priv->uncore;
 	__sprint_engine_name(engine->name, info);
 	engine->hw_id = engine->guc_id = info->hw_id;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 01223864237a..343c4459e8a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -34,6 +34,7 @@ struct drm_i915_reg_table;
 struct i915_gem_context;
 struct i915_request;
 struct i915_sched_attr;
+struct intel_gt;
 struct intel_uncore;
 
 typedef u8 intel_engine_mask_t;
@@ -266,6 +267,7 @@ struct intel_engine_execlists {
 
 struct intel_engine_cs {
 	struct drm_i915_private *i915;
+	struct intel_gt *gt;
 	struct intel_uncore *uncore;
 	char name[INTEL_ENGINE_CS_MAX_NAME];
 
-- 
2.20.1

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[RFC 10/28] drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 52 +++++++++++++++++-----------
 drivers/gpu/drm/i915/gt/intel_mocs.h |  3 +-
 drivers/gpu/drm/i915/i915_gem.c      |  2 +-
 3 files changed, 35 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 79df66022d3a..aef8aa5b0b4d 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -23,6 +23,7 @@
 #include "i915_drv.h"
 
 #include "intel_engine.h"
+#include "intel_gt.h"
 #include "intel_mocs.h"
 #include "intel_lrc.h"
 
@@ -239,7 +240,7 @@ static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
 
 /**
  * get_mocs_settings()
- * @dev_priv:	i915 device.
+ * @gt:		gt device
  * @table:      Output table that will be made to point at appropriate
  *	      MOCS values for the device.
  *
@@ -249,33 +250,34 @@ static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
  *
  * Return: true if there are applicable MOCS settings for the device.
  */
-static bool get_mocs_settings(struct drm_i915_private *dev_priv,
+static bool get_mocs_settings(struct intel_gt *gt,
 			      struct drm_i915_mocs_table *table)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	bool result = false;
 
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (INTEL_GEN(i915) >= 11) {
 		table->size  = ARRAY_SIZE(icelake_mocs_table);
 		table->table = icelake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
 		result = true;
-	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = skylake_mocs_table;
 		result = true;
-	} else if (IS_GEN9_LP(dev_priv)) {
+	} else if (IS_GEN9_LP(i915)) {
 		table->size  = ARRAY_SIZE(broxton_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = broxton_mocs_table;
 		result = true;
 	} else {
-		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
+		WARN_ONCE(INTEL_GEN(i915) >= 9,
 			  "Platform that should have a MOCS table does not.\n");
 	}
 
 	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
-	if (IS_GEN(dev_priv, 9)) {
+	if (IS_GEN(i915, 9)) {
 		int i;
 
 		for (i = 0; i < table->size; i++)
@@ -330,12 +332,13 @@ static u32 get_entry_control(const struct drm_i915_mocs_table *table,
  */
 void intel_mocs_init_engine(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
+	struct intel_gt *gt = engine->gt;
+	struct intel_uncore *uncore = gt->uncore;
 	struct drm_i915_mocs_table table;
 	unsigned int index;
 	u32 unused_value;
 
-	if (!get_mocs_settings(dev_priv, &table))
+	if (!get_mocs_settings(gt, &table))
 		return;
 
 	/* Set unused values to PTE */
@@ -344,12 +347,16 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
 	for (index = 0; index < table.size; index++) {
 		u32 value = get_entry_control(&table, index);
 
-		I915_WRITE(mocs_register(engine->id, index), value);
+		intel_uncore_write(uncore,
+				   mocs_register(engine->id, index),
+				   value);
 	}
 
 	/* All remaining entries are also unused */
 	for (; index < table.n_entries; index++)
-		I915_WRITE(mocs_register(engine->id, index), unused_value);
+		intel_uncore_write(uncore,
+				   mocs_register(engine->id, index),
+				   unused_value);
 }
 
 /**
@@ -494,13 +501,14 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
  *
  * Return: Nothing.
  */
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
+void intel_mocs_init_l3cc_table(struct intel_gt *gt)
 {
+	struct intel_uncore *uncore = gt->uncore;
 	struct drm_i915_mocs_table table;
 	unsigned int i;
 	u16 unused_value;
 
-	if (!get_mocs_settings(dev_priv, &table))
+	if (!get_mocs_settings(gt, &table))
 		return;
 
 	/* Set unused values to PTE */
@@ -510,23 +518,27 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
 		u16 low = get_entry_l3cc(&table, 2 * i);
 		u16 high = get_entry_l3cc(&table, 2 * i + 1);
 
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, low, high));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, low, high));
 	}
 
 	/* Odd table size - 1 left over */
 	if (table.size & 0x01) {
 		u16 low = get_entry_l3cc(&table, 2 * i);
 
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, low, unused_value));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, low, unused_value));
 		i++;
 	}
 
 	/* All remaining entries are also unused */
 	for (; i < table.n_entries / 2; i++)
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, unused_value, unused_value));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, unused_value,
+						unused_value));
 }
 
 /**
@@ -550,7 +562,7 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
 	struct drm_i915_mocs_table t;
 	int ret;
 
-	if (get_mocs_settings(rq->i915, &t)) {
+	if (get_mocs_settings(rq->engine->gt, &t)) {
 		/* Program the RCS control registers */
 		ret = emit_mocs_control_table(rq, &t);
 		if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 0913704a1af2..8b9813e6f9ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -52,9 +52,10 @@
 struct drm_i915_private;
 struct i915_request;
 struct intel_engine_cs;
+struct intel_gt;
 
 int intel_rcs_context_init_mocs(struct i915_request *rq);
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
+void intel_mocs_init_l3cc_table(struct intel_gt *gt);
 void intel_mocs_init_engine(struct intel_engine_cs *engine);
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 27d93fc8d20b..49c7c7b87bdc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1289,7 +1289,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 		goto out;
 	}
 
-	intel_mocs_init_l3cc_table(dev_priv);
+	intel_mocs_init_l3cc_table(&dev_priv->gt);
 
 	/* Only when the HW is re-initialised, can we replay the requests */
 	ret = intel_engines_resume(dev_priv);
-- 
2.20.1

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[RFC 11/28] drm/i915: Convert i915_ppgtt_init_hw to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c     |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c | 102 ++++++++++++++++++----------
 drivers/gpu/drm/i915/i915_gem_gtt.h |   3 +-
 3 files changed, 68 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 49c7c7b87bdc..e54cd30534dc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1270,7 +1270,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	if (ret)
 		goto out;
 
-	ret = i915_ppgtt_init_hw(dev_priv);
+	ret = i915_ppgtt_init_hw(&dev_priv->gt);
 	if (ret) {
 		DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 		goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ac6ed459720e..651ca5ed08a1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -43,6 +43,7 @@
 #include "i915_vgpu.h"
 #include "intel_drv.h"
 #include "intel_frontbuffer.h"
+#include "gt/intel_gt.h"
 
 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
 
@@ -1694,25 +1695,29 @@ static inline void gen6_write_pde(const struct gen6_ppgtt *ppgtt,
 		  ppgtt->pd_addr + pde);
 }
 
-static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
+static void gen7_ppgtt_enable(struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
 	struct intel_engine_cs *engine;
 	u32 ecochk, ecobits;
 	enum intel_engine_id id;
 
-	ecobits = I915_READ(GAC_ECO_BITS);
-	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
+	intel_uncore_write(uncore,
+			   GAC_ECO_BITS,
+			   ecobits | ECOBITS_PPGTT_CACHE64B);
 
-	ecochk = I915_READ(GAM_ECOCHK);
-	if (IS_HASWELL(dev_priv)) {
+	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
+	if (IS_HASWELL(i915)) {
 		ecochk |= ECOCHK_PPGTT_WB_HSW;
 	} else {
 		ecochk |= ECOCHK_PPGTT_LLC_IVB;
 		ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 	}
-	I915_WRITE(GAM_ECOCHK, ecochk);
+	intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
 
-	for_each_engine(engine, dev_priv, id) {
+	for_each_engine(engine, i915, id) {
 		/* GFX_MODE is per-ring on gen7+ */
 		ENGINE_WRITE(engine,
 			     RING_MODE_GEN7,
@@ -1720,22 +1725,30 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
+static void gen6_ppgtt_enable(struct intel_gt *gt)
 {
+	struct intel_uncore *uncore = gt->uncore;
 	u32 ecochk, gab_ctl, ecobits;
 
-	ecobits = I915_READ(GAC_ECO_BITS);
-	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
-		   ECOBITS_PPGTT_CACHE64B);
+	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
+	intel_uncore_write(uncore,
+			   GAC_ECO_BITS,
+			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
 
-	gab_ctl = I915_READ(GAB_CTL);
-	I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
+	intel_uncore_write(uncore,
+			   GAB_CTL,
+			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 
-	ecochk = I915_READ(GAM_ECOCHK);
-	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
+	intel_uncore_write(uncore,
+			   GAM_ECOCHK,
+			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
-	if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
-		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
+		intel_uncore_write(uncore,
+				   GFX_MODE,
+				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 }
 
 /* PPGTT support for Sandybdrige/Gen6 and later */
@@ -2187,21 +2200,32 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
 	return ERR_PTR(err);
 }
 
-static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
+static void gtt_write_workarounds(struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
+
 	/* This function is for gtt related workarounds. This function is
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
 	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
-	if (IS_BROADWELL(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
-	else if (IS_CHERRYVIEW(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-	else if (IS_GEN9_LP(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
-	else if (INTEL_GEN(dev_priv) >= 9)
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
+	if (IS_BROADWELL(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
+	else if (IS_CHERRYVIEW(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
+	else if (IS_GEN9_LP(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
+	else if (INTEL_GEN(i915) >= 9)
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 
 	/*
 	 * To support 64K PTEs we need to first enable the use of the
@@ -2214,21 +2238,25 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * 32K pages, but we don't currently have any support for it in our
 	 * driver.
 	 */
-	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
-	    INTEL_GEN(dev_priv) <= 10)
-		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
-			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
-			   GAMW_ECO_ENABLE_64K_IPS_FIELD);
+	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
+	    INTEL_GEN(i915) <= 10)
+		intel_uncore_write(uncore,
+				   GEN8_GAMW_ECO_DEV_RW_IA,
+				   intel_uncore_read(uncore,
+						     GEN8_GAMW_ECO_DEV_RW_IA) |
+				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
 }
 
-int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
+int i915_ppgtt_init_hw(struct intel_gt *gt)
 {
-	gtt_write_workarounds(dev_priv);
+	struct drm_i915_private *i915 = gt->i915;
+
+	gtt_write_workarounds(gt);
 
-	if (IS_GEN(dev_priv, 6))
-		gen6_ppgtt_enable(dev_priv);
-	else if (IS_GEN(dev_priv, 7))
-		gen7_ppgtt_enable(dev_priv);
+	if (IS_GEN(i915, 6))
+		gen6_ppgtt_enable(gt);
+	else if (IS_GEN(i915, 7))
+		gen7_ppgtt_enable(gt);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 63fa357c69de..f8c06288be65 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -64,6 +64,7 @@
 struct drm_i915_file_private;
 struct drm_i915_gem_object;
 struct i915_vma;
+struct intel_gt;
 
 typedef u32 gen6_pte_t;
 typedef u64 gen8_pte_t;
@@ -647,7 +648,7 @@ void i915_ggtt_disable_guc(struct drm_i915_private *i915);
 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
 
-int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
+int i915_ppgtt_init_hw(struct intel_gt *gt);
 
 struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
 
-- 
2.20.1

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[RFC 12/28] drm/i915: Consolidate some open coded mmio rmw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Replace some gen6/7 open coded rmw with intel_uncore_rmw.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +++++++++++++----------------
 1 file changed, 18 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 651ca5ed08a1..0810c1655224 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1700,13 +1700,10 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
 	struct drm_i915_private *i915 = gt->i915;
 	struct intel_uncore *uncore = gt->uncore;
 	struct intel_engine_cs *engine;
-	u32 ecochk, ecobits;
 	enum intel_engine_id id;
+	u32 ecochk;
 
-	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
-	intel_uncore_write(uncore,
-			   GAC_ECO_BITS,
-			   ecobits | ECOBITS_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
 
 	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
 	if (IS_HASWELL(i915)) {
@@ -1728,22 +1725,21 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
 static void gen6_ppgtt_enable(struct intel_gt *gt)
 {
 	struct intel_uncore *uncore = gt->uncore;
-	u32 ecochk, gab_ctl, ecobits;
 
-	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
-	intel_uncore_write(uncore,
-			   GAC_ECO_BITS,
-			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore,
+			 GAC_ECO_BITS,
+			 0,
+			 ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
 
-	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
-	intel_uncore_write(uncore,
-			   GAB_CTL,
-			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+	intel_uncore_rmw(uncore,
+			 GAB_CTL,
+			 0,
+			 GAB_CTL_CONT_AFTER_PAGEFAULT);
 
-	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
-	intel_uncore_write(uncore,
-			   GAM_ECOCHK,
-			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore,
+			 GAM_ECOCHK,
+			 0,
+			 ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
 	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
 		intel_uncore_write(uncore,
@@ -2240,11 +2236,10 @@ static void gtt_write_workarounds(struct intel_gt *gt)
 	 */
 	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
 	    INTEL_GEN(i915) <= 10)
-		intel_uncore_write(uncore,
-				   GEN8_GAMW_ECO_DEV_RW_IA,
-				   intel_uncore_read(uncore,
-						     GEN8_GAMW_ECO_DEV_RW_IA) |
-				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
+		intel_uncore_rmw(uncore,
+				 GEN8_GAMW_ECO_DEV_RW_IA,
+				 0,
+				 GAMW_ECO_ENABLE_64K_IPS_FIELD);
 }
 
 int i915_ppgtt_init_hw(struct intel_gt *gt)
-- 
2.20.1

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[RFC 13/28] drm/i915: Convert i915_gem_init_hw to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Actually the top level function remains but is split into a part which
writes to i915 and part which operates on intel_gt in order to initialize
the hardware.

GuC and engines are the only odd ones out remaining.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 66 ++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e54cd30534dc..b6f450e782e7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
 	}
 }
 
-int i915_gem_init_hw(struct drm_i915_private *dev_priv)
+static int init_hw(struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
 	int ret;
 
-	dev_priv->gt.last_init_time = ktime_get();
+	gt->last_init_time = ktime_get();
 
 	/* Double layer security blanket, see i915_gem_init() */
-	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 
-	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
-		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
+	if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
+		intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 
-	if (IS_HASWELL(dev_priv))
-		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
-			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
+	if (IS_HASWELL(i915))
+		intel_uncore_write(uncore,
+				   MI_PREDICATE_RESULT_2,
+				   IS_HSW_GT3(i915) ?
+				   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
 	/* Apply the GT workarounds... */
-	intel_gt_apply_workarounds(&dev_priv->gt);
+	intel_gt_apply_workarounds(gt);
 	/* ...and determine whether they are sticking. */
-	intel_gt_verify_workarounds(&dev_priv->gt, "init");
+	intel_gt_verify_workarounds(gt, "init");
 
-	intel_gt_init_swizzling(&dev_priv->gt);
+	intel_gt_init_swizzling(gt);
 
 	/*
 	 * At least 830 can leave some of the unused rings
@@ -1263,48 +1267,58 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	 * will prevent c3 entry. Makes sure all unused rings
 	 * are totally idle.
 	 */
-	init_unused_rings(&dev_priv->gt);
-
-	BUG_ON(!dev_priv->kernel_context);
-	ret = i915_terminally_wedged(dev_priv);
-	if (ret)
-		goto out;
+	init_unused_rings(gt);
 
-	ret = i915_ppgtt_init_hw(&dev_priv->gt);
+	ret = i915_ppgtt_init_hw(gt);
 	if (ret) {
 		DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 		goto out;
 	}
 
-	ret = intel_wopcm_init_hw(&dev_priv->wopcm);
+	ret = intel_wopcm_init_hw(&i915->wopcm);
 	if (ret) {
 		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
 		goto out;
 	}
 
 	/* We can't enable contexts until all firmware is loaded */
-	ret = intel_uc_init_hw(dev_priv);
+	ret = intel_uc_init_hw(i915);
 	if (ret) {
 		DRM_ERROR("Enabling uc failed (%d)\n", ret);
 		goto out;
 	}
 
-	intel_mocs_init_l3cc_table(&dev_priv->gt);
+	intel_mocs_init_l3cc_table(gt);
 
 	/* Only when the HW is re-initialised, can we replay the requests */
-	ret = intel_engines_resume(dev_priv);
+	ret = intel_engines_resume(i915);
 	if (ret)
 		goto cleanup_uc;
 
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
-	intel_engines_set_scheduler_caps(dev_priv);
 	return 0;
 
 cleanup_uc:
-	intel_uc_fini_hw(dev_priv);
+	intel_uc_fini_hw(i915);
 out:
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
+
+	return ret;
+}
+
+int i915_gem_init_hw(struct drm_i915_private *i915)
+{
+	int ret;
+
+	BUG_ON(!i915->kernel_context);
+	ret = i915_terminally_wedged(i915);
+	if (ret)
+		return ret;
+
+	ret = init_hw(&i915->gt);
+
+	intel_engines_set_scheduler_caps(i915);
 
 	return ret;
 }
-- 
2.20.1

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[RFC 14/28] drm/i915: Move intel_engines_resume into common init

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Since this part still operates on i915 and not intel_gt, move it to the
common (top-level) function.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 29 ++++++++++++++++++++++-------
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b6f450e782e7..77d9d092b2f4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1290,17 +1290,10 @@ static int init_hw(struct intel_gt *gt)
 
 	intel_mocs_init_l3cc_table(gt);
 
-	/* Only when the HW is re-initialised, can we replay the requests */
-	ret = intel_engines_resume(i915);
-	if (ret)
-		goto cleanup_uc;
-
 	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
 	return 0;
 
-cleanup_uc:
-	intel_uc_fini_hw(i915);
 out:
 	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
@@ -1309,6 +1302,7 @@ static int init_hw(struct intel_gt *gt)
 
 int i915_gem_init_hw(struct drm_i915_private *i915)
 {
+	struct intel_uncore *uncore = &i915->uncore;
 	int ret;
 
 	BUG_ON(!i915->kernel_context);
@@ -1316,7 +1310,28 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
 	if (ret)
 		return ret;
 
+	/* Double layer security blanket, see i915_gem_init() */
+	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
+
 	ret = init_hw(&i915->gt);
+	if (ret)
+		goto err_init;
+
+	/* Only when the HW is re-initialised, can we replay the requests */
+	ret = intel_engines_resume(i915);
+	if (ret)
+		goto err_engines;
+
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
+
+	intel_engines_set_scheduler_caps(i915);
+
+	return 0;
+
+err_engines:
+	intel_uc_fini_hw(i915);
+err_init:
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
 	intel_engines_set_scheduler_caps(i915);
 
-- 
2.20.1

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[RFC 15/28] drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More legacy mmio accessor removal. We pass in intel_gt explicitly allowing
code to use new intel_uncore_read/write helpers.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c    |  2 +-
 drivers/gpu/drm/i915/intel_wopcm.c | 31 ++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_wopcm.h |  4 +++-
 3 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 77d9d092b2f4..b7f88e2bd7df 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1275,7 +1275,7 @@ static int init_hw(struct intel_gt *gt)
 		goto out;
 	}
 
-	ret = intel_wopcm_init_hw(&i915->wopcm);
+	ret = intel_wopcm_init_hw(&i915->wopcm, gt);
 	if (ret) {
 		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
 		goto out;
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 7b4ba84b9fb8..931987e37241 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -225,17 +225,18 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
 	return 0;
 }
 
-static inline int write_and_verify(struct drm_i915_private *dev_priv,
-				   i915_reg_t reg, u32 val, u32 mask,
-				   u32 locked_bit)
+static int
+write_and_verify(struct intel_gt *gt,
+		 i915_reg_t reg, u32 val, u32 mask, u32 locked_bit)
 {
+	struct intel_uncore *uncore = gt->uncore;
 	u32 reg_val;
 
 	GEM_BUG_ON(val & ~mask);
 
-	I915_WRITE(reg, val);
+	intel_uncore_write(uncore, reg, val);
 
-	reg_val = I915_READ(reg);
+	reg_val = intel_uncore_read(uncore, reg);
 
 	return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
 }
@@ -250,29 +251,30 @@ static inline int write_and_verify(struct drm_i915_private *dev_priv,
  *
  * Return: 0 on success. -EIO if registers were locked with incorrect values.
  */
-int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
+int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt)
 {
-	struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
+	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
+	struct intel_uncore *uncore = gt->uncore;
 	u32 huc_agent;
 	u32 mask;
 	int err;
 
-	if (!USES_GUC(dev_priv))
+	if (!USES_GUC(i915))
 		return 0;
 
-	GEM_BUG_ON(!HAS_GUC(dev_priv));
+	GEM_BUG_ON(!HAS_GUC(i915));
 	GEM_BUG_ON(!wopcm->guc.size);
 	GEM_BUG_ON(!wopcm->guc.base);
 
-	err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, wopcm->guc.size,
+	err = write_and_verify(gt, GUC_WOPCM_SIZE, wopcm->guc.size,
 			       GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
 			       GUC_WOPCM_SIZE_LOCKED);
 	if (err)
 		goto err_out;
 
-	huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
+	huc_agent = USES_HUC(i915) ? HUC_LOADING_AGENT_GUC : 0;
 	mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
-	err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
+	err = write_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
 			       wopcm->guc.base | huc_agent, mask,
 			       GUC_WOPCM_OFFSET_VALID);
 	if (err)
@@ -283,8 +285,9 @@ int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
 err_out:
 	DRM_ERROR("Failed to init WOPCM registers:\n");
 	DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
-		  I915_READ(DMA_GUC_WOPCM_OFFSET));
-	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
+		  intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
+	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n",
+		  intel_uncore_read(uncore, GUC_WOPCM_SIZE));
 
 	return err;
 }
diff --git a/drivers/gpu/drm/i915/intel_wopcm.h b/drivers/gpu/drm/i915/intel_wopcm.h
index 114401971520..56aaed4d64ff 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_wopcm.h
@@ -9,6 +9,8 @@
 
 #include <linux/types.h>
 
+struct intel_gt;
+
 /**
  * struct intel_wopcm - Overall WOPCM info and WOPCM regions.
  * @size: Size of overall WOPCM.
@@ -41,6 +43,6 @@ static inline u32 intel_wopcm_guc_size(struct intel_wopcm *wopcm)
 
 void intel_wopcm_init_early(struct intel_wopcm *wopcm);
 int intel_wopcm_init(struct intel_wopcm *wopcm);
-int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
+int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt);
 
 #endif
-- 
2.20.1

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[RFC 16/28] drm/i915: Compartmentalize i915_ggtt_probe_hw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 31 +++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0810c1655224..c88213fa18af 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3507,21 +3507,16 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
 	return 0;
 }
 
-/**
- * i915_ggtt_probe_hw - Probe GGTT hardware location
- * @dev_priv: i915 device
- */
-int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
+static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct drm_i915_private *i915)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	int ret;
 
-	ggtt->vm.i915 = dev_priv;
-	ggtt->vm.dma = &dev_priv->drm.pdev->dev;
+	ggtt->vm.i915 = i915;
+	ggtt->vm.dma = &i915->drm.pdev->dev;
 
-	if (INTEL_GEN(dev_priv) <= 5)
+	if (INTEL_GEN(i915) <= 5)
 		ret = i915_gmch_probe(ggtt);
-	else if (INTEL_GEN(dev_priv) < 8)
+	else if (INTEL_GEN(i915) < 8)
 		ret = gen6_gmch_probe(ggtt);
 	else
 		ret = gen8_gmch_probe(ggtt);
@@ -3549,6 +3544,22 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
 	DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
 	DRM_DEBUG_DRIVER("DSM size = %lluM\n",
 			 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
+
+	return 0;
+}
+
+/**
+ * i915_ggtt_probe_hw - Probe GGTT hardware location
+ * @dev_priv: i915 device
+ */
+int i915_ggtt_probe_hw(struct drm_i915_private *i915)
+{
+	int ret;
+
+	ret = ggtt_probe_hw(&i915->ggtt, i915);
+	if (ret)
+		return ret;
+
 	if (intel_vtd_active())
 		DRM_INFO("VT-d active for gfx access\n");
 
-- 
2.20.1

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[RFC 17/28] drm/i915: Compartmentalize i915_ggtt_init_hw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 64 +++++++++++++++++++----------
 1 file changed, 42 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c88213fa18af..2232bd56e912 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3566,45 +3566,65 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 	return 0;
 }
 
-/**
- * i915_ggtt_init_hw - Initialize GGTT hardware
- * @dev_priv: i915 device
- */
-int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
+static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
-	int ret;
+	ggtt->vm.cleanup(&ggtt->vm);
+}
 
-	stash_init(&dev_priv->mm.wc_stash);
+static int ggtt_init_hw(struct i915_ggtt *ggtt)
+{
+	struct drm_i915_private *i915 = ggtt->vm.i915;
+	int ret = 0;
+
+	mutex_lock(&i915->drm.struct_mutex);
 
-	/* Note that we use page colouring to enforce a guard page at the
-	 * end of the address space. This is required as the CS may prefetch
-	 * beyond the end of the batch buffer, across the page boundary,
-	 * and beyond the end of the GTT if we do not provide a guard.
-	 */
-	mutex_lock(&dev_priv->drm.struct_mutex);
 	i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
 
 	ggtt->vm.is_ggtt = true;
 
 	/* Only VLV supports read-only GGTT mappings */
-	ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
+	ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
 
-	if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
+	if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
 		ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
-	mutex_unlock(&dev_priv->drm.struct_mutex);
 
-	if (!io_mapping_init_wc(&dev_priv->ggtt.iomap,
-				dev_priv->ggtt.gmadr.start,
-				dev_priv->ggtt.mappable_end)) {
+	if (!io_mapping_init_wc(&ggtt->iomap,
+				ggtt->gmadr.start,
+				ggtt->mappable_end)) {
+		ggtt_cleanup_hw(ggtt);
 		ret = -EIO;
-		goto out_gtt_cleanup;
+		goto out;
 	}
 
 	ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
 
 	i915_ggtt_init_fences(ggtt);
 
+out:
+	mutex_unlock(&i915->drm.struct_mutex);
+
+	return ret;
+}
+
+/**
+ * i915_ggtt_init_hw - Initialize GGTT hardware
+ * @dev_priv: i915 device
+ */
+int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
+{
+	int ret;
+
+	stash_init(&dev_priv->mm.wc_stash);
+
+	/* Note that we use page colouring to enforce a guard page at the
+	 * end of the address space. This is required as the CS may prefetch
+	 * beyond the end of the batch buffer, across the page boundary,
+	 * and beyond the end of the GTT if we do not provide a guard.
+	 */
+	ret = ggtt_init_hw(&dev_priv->ggtt);
+	if (ret)
+		return ret;
+
 	/*
 	 * Initialise stolen early so that we may reserve preallocated
 	 * objects for the BIOS to KMS transition.
@@ -3616,7 +3636,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
 	return 0;
 
 out_gtt_cleanup:
-	ggtt->vm.cleanup(&ggtt->vm);
+	ggtt_cleanup_hw(&dev_priv->ggtt);
 	return ret;
 }
 
-- 
2.20.1

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[RFC 18/28] drm/i915: Make ggtt invalidation work on ggtt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

It is more logical for ggtt invalidation to take ggtt as input parameter.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 51 ++++++++++++++---------------
 drivers/gpu/drm/i915/i915_gem_gtt.h |  2 +-
 2 files changed, 26 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2232bd56e912..95af45156cc2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -111,9 +111,9 @@
 static int
 i915_get_ggtt_vma_pages(struct i915_vma *vma);
 
-static void gen6_ggtt_invalidate(struct drm_i915_private *i915)
+static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
-	struct intel_uncore *uncore = &i915->uncore;
+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
 
 	/*
 	 * Note that as an uncached mmio write, this will flush the
@@ -122,24 +122,19 @@ static void gen6_ggtt_invalidate(struct drm_i915_private *i915)
 	intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 }
 
-static void guc_ggtt_invalidate(struct drm_i915_private *i915)
+static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
-	struct intel_uncore *uncore = &i915->uncore;
+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
 
-	gen6_ggtt_invalidate(i915);
+	gen6_ggtt_invalidate(ggtt);
 	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
-static void gmch_ggtt_invalidate(struct drm_i915_private *i915)
+static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
 	intel_gtt_chipset_flush();
 }
 
-static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
-{
-	i915->ggtt.invalidate(i915);
-}
-
 static int ppgtt_bind_vma(struct i915_vma *vma,
 			  enum i915_cache_level cache_level,
 			  u32 unused)
@@ -1876,7 +1871,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm,
 
 	if (flush) {
 		mark_tlbs_dirty(&ppgtt->base);
-		gen6_ggtt_invalidate(vm->i915);
+		gen6_ggtt_invalidate(&vm->i915->ggtt);
 	}
 
 	intel_runtime_pm_put(vm->i915, wakeref);
@@ -2025,7 +2020,7 @@ static int pd_vma_bind(struct i915_vma *vma,
 		gen6_write_pde(ppgtt, pde, pt);
 
 	mark_tlbs_dirty(&ppgtt->base);
-	gen6_ggtt_invalidate(ppgtt->base.vm.i915);
+	gen6_ggtt_invalidate(ggtt);
 
 	return 0;
 }
@@ -2340,7 +2335,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
 
 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
 
-	i915_ggtt_invalidate(dev_priv);
+	ggtt->invalidate(ggtt);
 }
 
 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
@@ -2386,7 +2381,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
 
 	gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
 
-	ggtt->invalidate(vm->i915);
+	ggtt->invalidate(ggtt);
 }
 
 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
@@ -2414,7 +2409,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 	 * We want to flush the TLBs only after we're certain all the PTE
 	 * updates have finished.
 	 */
-	ggtt->invalidate(vm->i915);
+	ggtt->invalidate(ggtt);
 }
 
 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
@@ -2429,7 +2424,7 @@ static void gen6_ggtt_insert_page(struct i915_address_space *vm,
 
 	iowrite32(vm->pte_encode(addr, level, flags), pte);
 
-	ggtt->invalidate(vm->i915);
+	ggtt->invalidate(ggtt);
 }
 
 /*
@@ -2455,7 +2450,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 	 * We want to flush the TLBs only after we're certain all the PTE
 	 * updates have finished.
 	 */
-	ggtt->invalidate(vm->i915);
+	ggtt->invalidate(ggtt);
 }
 
 static void nop_clear_range(struct i915_address_space *vm,
@@ -3650,25 +3645,29 @@ int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
 
 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
 {
-	GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
+	struct i915_ggtt *ggtt = &i915->ggtt;
 
-	i915->ggtt.invalidate = guc_ggtt_invalidate;
+	GEM_BUG_ON(ggtt->invalidate != gen6_ggtt_invalidate);
 
-	i915_ggtt_invalidate(i915);
+	ggtt->invalidate = guc_ggtt_invalidate;
+
+	ggtt->invalidate(ggtt);
 }
 
 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 {
+	struct i915_ggtt *ggtt = &i915->ggtt;
+
 	/* XXX Temporary pardon for error unload */
-	if (i915->ggtt.invalidate == gen6_ggtt_invalidate)
+	if (ggtt->invalidate == gen6_ggtt_invalidate)
 		return;
 
 	/* We should only be called after i915_ggtt_enable_guc() */
-	GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
+	GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
 
-	i915->ggtt.invalidate = gen6_ggtt_invalidate;
+	ggtt->invalidate = gen6_ggtt_invalidate;
 
-	i915_ggtt_invalidate(i915);
+	ggtt->invalidate(ggtt);
 }
 
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
@@ -3710,7 +3709,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 	}
 
 	ggtt->vm.closed = false;
-	i915_ggtt_invalidate(dev_priv);
+	ggtt->invalidate(ggtt);
 
 	mutex_unlock(&ggtt->vm.mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f8c06288be65..b541190db6e8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -401,7 +401,7 @@ struct i915_ggtt {
 
 	/** "Graphics Stolen Memory" holds the global PTEs */
 	void __iomem *gsm;
-	void (*invalidate)(struct drm_i915_private *dev_priv);
+	void (*invalidate)(struct i915_ggtt *ggtt);
 
 	bool do_idle_maps;
 
-- 
2.20.1

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[RFC 19/28] drm/i915: Store intel_gt backpointer in vm

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This will come useful in the following patch.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 16 ++++++++++------
 drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 95af45156cc2..0bc75c963955 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1587,9 +1587,11 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
 	return -ENOMEM;
 }
 
-static void ppgtt_init(struct drm_i915_private *i915,
-		       struct i915_ppgtt *ppgtt)
+static void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
+
+	ppgtt->vm.gt = gt;
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 	ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
@@ -1618,7 +1620,7 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	if (!ppgtt)
 		return ERR_PTR(-ENOMEM);
 
-	ppgtt_init(i915, ppgtt);
+	ppgtt_init(ppgtt, &i915->gt);
 
 	/*
 	 * From bdw, there is hw support for read-only pages in the PPGTT.
@@ -2155,7 +2157,7 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
 	if (!ppgtt)
 		return ERR_PTR(-ENOMEM);
 
-	ppgtt_init(i915, &ppgtt->base);
+	ppgtt_init(&ppgtt->base, &i915->gt);
 
 	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
@@ -3502,10 +3504,12 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
 	return 0;
 }
 
-static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct drm_i915_private *i915)
+static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	int ret;
 
+	ggtt->vm.gt = gt;
 	ggtt->vm.i915 = i915;
 	ggtt->vm.dma = &i915->drm.pdev->dev;
 
@@ -3551,7 +3555,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 {
 	int ret;
 
-	ret = ggtt_probe_hw(&i915->ggtt, i915);
+	ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index b541190db6e8..9a3d96370f07 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -297,6 +297,7 @@ struct i915_address_space {
 	struct kref ref;
 
 	struct drm_mm mm;
+	struct intel_gt *gt;
 	struct drm_i915_private *i915;
 	struct device *dma;
 	/* Every address space belongs to a struct file - except for the global
-- 
2.20.1

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[RFC 20/28] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0bc75c963955..516ffc4a521a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2323,23 +2323,28 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
 	return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
 }
 
-void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
+static void ggtt_suspend_mappings(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct drm_i915_private *i915 = ggtt->vm.i915;
 
 	/* Don't bother messing with faults pre GEN6 as we have little
 	 * documentation supporting that it's a good idea.
 	 */
-	if (INTEL_GEN(dev_priv) < 6)
+	if (INTEL_GEN(i915) < 6)
 		return;
 
-	intel_gt_check_and_clear_faults(&dev_priv->gt);
+	intel_gt_check_and_clear_faults(ggtt->vm.gt);
 
 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
 
 	ggtt->invalidate(ggtt);
 }
 
+void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
+{
+	ggtt_suspend_mappings(&dev_priv->ggtt);
+}
+
 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
 			       struct sg_table *pages)
 {
@@ -3674,12 +3679,11 @@ void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 	ggtt->invalidate(ggtt);
 }
 
-void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
+static void ggtt_restore_mappings(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	struct i915_vma *vma, *vn;
 
-	intel_gt_check_and_clear_faults(&dev_priv->gt);
+	intel_gt_check_and_clear_faults(ggtt->vm.gt);
 
 	mutex_lock(&ggtt->vm.mutex);
 
@@ -3716,6 +3720,11 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 	ggtt->invalidate(ggtt);
 
 	mutex_unlock(&ggtt->vm.mutex);
+}
+
+void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
+{
+	ggtt_restore_mappings(&dev_priv->ggtt);
 
 	if (INTEL_GEN(dev_priv) >= 8) {
 		struct intel_ppat *ppat = &dev_priv->ppat;
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[RFC 21/28] drm/i915/gtt: Reduce source verbosity by caching repeated dereferences

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

There is a lot of code in i915_gem_gtt.c which repeatadly dereferences
either ggtt or ppgtt in order to get to the vm. Cache those accesses in
local variables for better readability.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 254 +++++++++++++++-------------
 1 file changed, 134 insertions(+), 120 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 516ffc4a521a..d09a4d9b71da 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1004,10 +1004,11 @@ gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
 {
 	struct i915_page_directory *pd;
 	const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+	struct i915_address_space *vm = &ppgtt->vm;
 	gen8_pte_t *vaddr;
 	bool ret;
 
-	GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
+	GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(vm));
 	pd = pdp->page_directory[idx->pdpe];
 	vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
 	do {
@@ -1038,7 +1039,7 @@ gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
 					break;
 				}
 
-				GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
+				GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(vm));
 				pd = pdp->page_directory[idx->pdpe];
 			}
 
@@ -1352,16 +1353,17 @@ static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm,
 
 static void gen8_ppgtt_cleanup_4lvl(struct i915_ppgtt *ppgtt)
 {
+	struct i915_address_space *vm = &ppgtt->vm;
 	int i;
 
 	for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
-		if (ppgtt->pml4.pdps[i] == ppgtt->vm.scratch_pdp)
+		if (ppgtt->pml4.pdps[i] == vm->scratch_pdp)
 			continue;
 
-		gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, ppgtt->pml4.pdps[i]);
+		gen8_ppgtt_cleanup_3lvl(vm, ppgtt->pml4.pdps[i]);
 	}
 
-	cleanup_px(&ppgtt->vm, &ppgtt->pml4);
+	cleanup_px(vm, &ppgtt->pml4);
 }
 
 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
@@ -1590,18 +1592,19 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
 static void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
+	struct i915_address_space *vm = &ppgtt->vm;
 
-	ppgtt->vm.gt = gt;
-	ppgtt->vm.i915 = i915;
-	ppgtt->vm.dma = &i915->drm.pdev->dev;
-	ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
+	vm->gt = gt;
+	vm->i915 = i915;
+	vm->dma = &i915->drm.pdev->dev;
+	vm->total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
 
-	i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
+	i915_address_space_init(vm, VM_CLASS_PPGTT);
 
-	ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->vm.vma_ops.clear_pages = clear_pages;
+	vm->vma_ops.bind_vma    = ppgtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ppgtt_unbind_vma;
+	vm->vma_ops.set_pages   = ppgtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
 }
 
 /*
@@ -1613,6 +1616,7 @@ static void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
  */
 static struct i915_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 {
+	struct i915_address_space *vm;
 	struct i915_ppgtt *ppgtt;
 	int err;
 
@@ -1620,6 +1624,8 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	if (!ppgtt)
 		return ERR_PTR(-ENOMEM);
 
+	vm = &ppgtt->vm;
+
 	ppgtt_init(ppgtt, &i915->gt);
 
 	/*
@@ -1628,30 +1634,30 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	 * Gen11 has HSDES#:1807136187 unresolved. Disable ro support
 	 * for now.
 	 */
-	ppgtt->vm.has_read_only = INTEL_GEN(i915) != 11;
+	vm->has_read_only = INTEL_GEN(i915) != 11;
 
 	/* There are only few exceptions for gen >=6. chv and bxt.
 	 * And we are not sure about the latter so play safe for now.
 	 */
 	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
-		ppgtt->vm.pt_kmap_wc = true;
+		vm->pt_kmap_wc = true;
 
-	err = gen8_init_scratch(&ppgtt->vm);
+	err = gen8_init_scratch(vm);
 	if (err)
 		goto err_free;
 
-	if (i915_vm_is_4lvl(&ppgtt->vm)) {
-		err = setup_px(&ppgtt->vm, &ppgtt->pml4);
+	if (i915_vm_is_4lvl(vm)) {
+		err = setup_px(vm, &ppgtt->pml4);
 		if (err)
 			goto err_scratch;
 
-		gen8_initialize_pml4(&ppgtt->vm, &ppgtt->pml4);
+		gen8_initialize_pml4(vm, &ppgtt->pml4);
 
-		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
-		ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
-		ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
+		vm->allocate_va_range = gen8_ppgtt_alloc_4lvl;
+		vm->insert_entries = gen8_ppgtt_insert_4lvl;
+		vm->clear_range = gen8_ppgtt_clear_4lvl;
 	} else {
-		err = __pdp_init(&ppgtt->vm, &ppgtt->pdp);
+		err = __pdp_init(vm, &ppgtt->pdp);
 		if (err)
 			goto err_scratch;
 
@@ -1663,20 +1669,20 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 			}
 		}
 
-		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
-		ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
-		ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
+		vm->allocate_va_range = gen8_ppgtt_alloc_3lvl;
+		vm->insert_entries = gen8_ppgtt_insert_3lvl;
+		vm->clear_range = gen8_ppgtt_clear_3lvl;
 	}
 
 	if (intel_vgpu_active(i915))
 		gen8_ppgtt_notify_vgt(ppgtt, true);
 
-	ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
+	vm->cleanup = gen8_ppgtt_cleanup;
 
 	return ppgtt;
 
 err_scratch:
-	gen8_free_scratch(&ppgtt->vm);
+	gen8_free_scratch(vm);
 err_free:
 	kfree(ppgtt);
 	return ERR_PTR(err);
@@ -2325,7 +2331,8 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
 
 static void ggtt_suspend_mappings(struct i915_ggtt *ggtt)
 {
-	struct drm_i915_private *i915 = ggtt->vm.i915;
+	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *i915 = vm->i915;
 
 	/* Don't bother messing with faults pre GEN6 as we have little
 	 * documentation supporting that it's a good idea.
@@ -2333,9 +2340,9 @@ static void ggtt_suspend_mappings(struct i915_ggtt *ggtt)
 	if (INTEL_GEN(i915) < 6)
 		return;
 
-	intel_gt_check_and_clear_faults(ggtt->vm.gt);
+	intel_gt_check_and_clear_faults(vm->gt);
 
-	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
+	vm->clear_range(vm, 0, vm->total);
 
 	ggtt->invalidate(ggtt);
 }
@@ -2837,16 +2844,17 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
 
 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
 {
+	struct i915_address_space *vm = &ggtt->vm;
 	u64 size;
 	int ret;
 
-	if (!USES_GUC(ggtt->vm.i915))
+	if (!USES_GUC(vm->i915))
 		return 0;
 
-	GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
-	size = ggtt->vm.total - GUC_GGTT_TOP;
+	GEM_BUG_ON(vm->total <= GUC_GGTT_TOP);
+	size = vm->total - GUC_GGTT_TOP;
 
-	ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
+	ret = i915_gem_gtt_reserve(vm, &ggtt->uc_fw, size,
 				   GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
 				   PIN_NOEVICT);
 	if (ret)
@@ -2873,6 +2881,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 * of the aperture.
 	 */
 	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct i915_address_space *vm = &ggtt->vm;
 	unsigned long hole_start, hole_end;
 	struct drm_mm_node *entry;
 	int ret;
@@ -2891,7 +2900,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 		return ret;
 
 	/* Reserve a mappable slot for our lockless error capture */
-	ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
+	ret = drm_mm_insert_node_in_range(&vm->mm, &ggtt->error_capture,
 					  PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
 					  0, ggtt->mappable_end,
 					  DRM_MM_INSERT_LOW);
@@ -2908,15 +2917,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 		goto err_reserve;
 
 	/* Clear any non-preallocated blocks */
-	drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
+	drm_mm_for_each_hole(entry, &vm->mm, hole_start, hole_end) {
 		DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 			      hole_start, hole_end);
-		ggtt->vm.clear_range(&ggtt->vm, hole_start,
-				     hole_end - hole_start);
+		vm->clear_range(vm, hole_start, hole_end - hole_start);
 	}
 
 	/* And finally clear the reserved guard page */
-	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
+	vm->clear_range(vm, vm->total - PAGE_SIZE, PAGE_SIZE);
 
 	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
 		ret = init_aliasing_ppgtt(dev_priv);
@@ -2940,15 +2948,16 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 {
 	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct i915_address_space *vm = &ggtt->vm;
 	struct i915_vma *vma, *vn;
 	struct pagevec *pvec;
 
-	ggtt->vm.closed = true;
+	vm->closed = true;
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	fini_aliasing_ppgtt(dev_priv);
 
-	list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
+	list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link)
 		WARN_ON(i915_vma_unbind(vma));
 
 	if (drm_mm_node_allocated(&ggtt->error_capture))
@@ -2956,12 +2965,12 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 
 	ggtt_release_guc_top(ggtt);
 
-	if (drm_mm_initialized(&ggtt->vm.mm)) {
+	if (drm_mm_initialized(&vm->mm)) {
 		intel_vgt_deballoon(ggtt);
-		i915_address_space_fini(&ggtt->vm);
+		i915_address_space_fini(vm);
 	}
 
-	ggtt->vm.cleanup(&ggtt->vm);
+	vm->cleanup(vm);
 
 	pvec = &dev_priv->mm.wc_stash.pvec;
 	if (pvec->nr) {
@@ -3013,7 +3022,8 @@ static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
 
 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 {
-	struct drm_i915_private *dev_priv = ggtt->vm.i915;
+	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *dev_priv = vm->i915;
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	phys_addr_t phys_addr;
 	int ret;
@@ -3037,7 +3047,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 		return -ENOMEM;
 	}
 
-	ret = setup_scratch_page(&ggtt->vm, GFP_DMA32);
+	ret = setup_scratch_page(vm, GFP_DMA32);
 	if (ret) {
 		DRM_ERROR("Scratch setup failed\n");
 		/* iounmap will also get called at remove, but meh */
@@ -3045,9 +3055,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 		return ret;
 	}
 
-	ggtt->vm.scratch_pte =
-		ggtt->vm.pte_encode(ggtt->vm.scratch_page.daddr,
-				    I915_CACHE_NONE, 0);
+	vm->scratch_pte =
+		vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_NONE, 0);
 
 	return 0;
 }
@@ -3347,7 +3356,8 @@ static void setup_private_pat(struct drm_i915_private *dev_priv)
 
 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 {
-	struct drm_i915_private *dev_priv = ggtt->vm.i915;
+	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *dev_priv = vm->i915;
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	unsigned int size;
 	u16 snb_gmch_ctl;
@@ -3371,22 +3381,22 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 	else
 		size = gen8_get_total_gtt_size(snb_gmch_ctl);
 
-	ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
-	ggtt->vm.cleanup = gen6_gmch_remove;
-	ggtt->vm.insert_page = gen8_ggtt_insert_page;
-	ggtt->vm.clear_range = nop_clear_range;
+	vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
+	vm->cleanup = gen6_gmch_remove;
+	vm->insert_page = gen8_ggtt_insert_page;
+	vm->clear_range = nop_clear_range;
 	if (intel_scanout_needs_vtd_wa(dev_priv))
-		ggtt->vm.clear_range = gen8_ggtt_clear_range;
+		vm->clear_range = gen8_ggtt_clear_range;
 
-	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
+	vm->insert_entries = gen8_ggtt_insert_entries;
 
 	/* Serialize GTT updates with aperture access on BXT if VT-d is on. */
 	if (intel_ggtt_update_needs_vtd_wa(dev_priv) ||
 	    IS_CHERRYVIEW(dev_priv) /* fails with concurrent use/update */) {
-		ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
-		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
-		if (ggtt->vm.clear_range != nop_clear_range)
-			ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;
+		vm->insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
+		vm->insert_page    = bxt_vtd_ggtt_insert_page__BKL;
+		if (vm->clear_range != nop_clear_range)
+			vm->clear_range = bxt_vtd_ggtt_clear_range__BKL;
 
 		/* Prevent recursively calling stop_machine() and deadlocks. */
 		dev_info(dev_priv->drm.dev,
@@ -3396,12 +3406,12 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
 	ggtt->invalidate = gen6_ggtt_invalidate;
 
-	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
-	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
-	ggtt->vm.vma_ops.set_pages   = ggtt_set_pages;
-	ggtt->vm.vma_ops.clear_pages = clear_pages;
+	vm->vma_ops.bind_vma    = ggtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ggtt_unbind_vma;
+	vm->vma_ops.set_pages   = ggtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
 
-	ggtt->vm.pte_encode = gen8_pte_encode;
+	vm->pte_encode = gen8_pte_encode;
 
 	setup_private_pat(dev_priv);
 
@@ -3410,7 +3420,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
 {
-	struct drm_i915_private *dev_priv = ggtt->vm.i915;
+	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *dev_priv = vm->i915;
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	unsigned int size;
 	u16 snb_gmch_ctl;
@@ -3437,32 +3448,32 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
 	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 
 	size = gen6_get_total_gtt_size(snb_gmch_ctl);
-	ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
+	vm->total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
 
-	ggtt->vm.clear_range = nop_clear_range;
+	vm->clear_range = nop_clear_range;
 	if (!HAS_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
-		ggtt->vm.clear_range = gen6_ggtt_clear_range;
-	ggtt->vm.insert_page = gen6_ggtt_insert_page;
-	ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
-	ggtt->vm.cleanup = gen6_gmch_remove;
+		vm->clear_range = gen6_ggtt_clear_range;
+	vm->insert_page = gen6_ggtt_insert_page;
+	vm->insert_entries = gen6_ggtt_insert_entries;
+	vm->cleanup = gen6_gmch_remove;
 
 	ggtt->invalidate = gen6_ggtt_invalidate;
 
 	if (HAS_EDRAM(dev_priv))
-		ggtt->vm.pte_encode = iris_pte_encode;
+		vm->pte_encode = iris_pte_encode;
 	else if (IS_HASWELL(dev_priv))
-		ggtt->vm.pte_encode = hsw_pte_encode;
+		vm->pte_encode = hsw_pte_encode;
 	else if (IS_VALLEYVIEW(dev_priv))
-		ggtt->vm.pte_encode = byt_pte_encode;
+		vm->pte_encode = byt_pte_encode;
 	else if (INTEL_GEN(dev_priv) >= 7)
-		ggtt->vm.pte_encode = ivb_pte_encode;
+		vm->pte_encode = ivb_pte_encode;
 	else
-		ggtt->vm.pte_encode = snb_pte_encode;
+		vm->pte_encode = snb_pte_encode;
 
-	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
-	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
-	ggtt->vm.vma_ops.set_pages   = ggtt_set_pages;
-	ggtt->vm.vma_ops.clear_pages = clear_pages;
+	vm->vma_ops.bind_vma    = ggtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ggtt_unbind_vma;
+	vm->vma_ops.set_pages   = ggtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
 
 	return ggtt_probe_common(ggtt, size);
 }
@@ -3474,7 +3485,8 @@ static void i915_gmch_remove(struct i915_address_space *vm)
 
 static int i915_gmch_probe(struct i915_ggtt *ggtt)
 {
-	struct drm_i915_private *dev_priv = ggtt->vm.i915;
+	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *dev_priv = vm->i915;
 	phys_addr_t gmadr_base;
 	int ret;
 
@@ -3484,24 +3496,24 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
 		return -EIO;
 	}
 
-	intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
+	intel_gtt_get(&vm->total, &gmadr_base, &ggtt->mappable_end);
 
 	ggtt->gmadr =
 		(struct resource) DEFINE_RES_MEM(gmadr_base,
 						 ggtt->mappable_end);
 
 	ggtt->do_idle_maps = needs_idle_maps(dev_priv);
-	ggtt->vm.insert_page = i915_ggtt_insert_page;
-	ggtt->vm.insert_entries = i915_ggtt_insert_entries;
-	ggtt->vm.clear_range = i915_ggtt_clear_range;
-	ggtt->vm.cleanup = i915_gmch_remove;
+	vm->insert_page = i915_ggtt_insert_page;
+	vm->insert_entries = i915_ggtt_insert_entries;
+	vm->clear_range = i915_ggtt_clear_range;
+	vm->cleanup = i915_gmch_remove;
 
 	ggtt->invalidate = gmch_ggtt_invalidate;
 
-	ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
-	ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
-	ggtt->vm.vma_ops.set_pages   = ggtt_set_pages;
-	ggtt->vm.vma_ops.clear_pages = clear_pages;
+	vm->vma_ops.bind_vma    = ggtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ggtt_unbind_vma;
+	vm->vma_ops.set_pages   = ggtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
 
 	if (unlikely(ggtt->do_idle_maps))
 		DRM_INFO("applying Ironlake quirks for intel_iommu\n");
@@ -3512,11 +3524,12 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
+	struct i915_address_space *vm = &ggtt->vm;
 	int ret;
 
-	ggtt->vm.gt = gt;
-	ggtt->vm.i915 = i915;
-	ggtt->vm.dma = &i915->drm.pdev->dev;
+	vm->gt = gt;
+	vm->i915 = i915;
+	vm->dma = &i915->drm.pdev->dev;
 
 	if (INTEL_GEN(i915) <= 5)
 		ret = i915_gmch_probe(ggtt);
@@ -3527,24 +3540,23 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
 	if (ret)
 		return ret;
 
-	if ((ggtt->vm.total - 1) >> 32) {
+	if ((vm->total - 1) >> 32) {
 		DRM_ERROR("We never expected a Global GTT with more than 32bits"
 			  " of address space! Found %lldM!\n",
-			  ggtt->vm.total >> 20);
-		ggtt->vm.total = 1ULL << 32;
-		ggtt->mappable_end =
-			min_t(u64, ggtt->mappable_end, ggtt->vm.total);
+			  vm->total >> 20);
+		vm->total = 1ULL << 32;
+		ggtt->mappable_end = min_t(u64, ggtt->mappable_end, vm->total);
 	}
 
-	if (ggtt->mappable_end > ggtt->vm.total) {
+	if (ggtt->mappable_end > vm->total) {
 		DRM_ERROR("mappable aperture extends past end of GGTT,"
 			  " aperture=%pa, total=%llx\n",
-			  &ggtt->mappable_end, ggtt->vm.total);
-		ggtt->mappable_end = ggtt->vm.total;
+			  &ggtt->mappable_end, vm->total);
+		ggtt->mappable_end = vm->total;
 	}
 
 	/* GMADR is the PCI mmio aperture into the global GTT. */
-	DRM_DEBUG_DRIVER("GGTT size = %lluM\n", ggtt->vm.total >> 20);
+	DRM_DEBUG_DRIVER("GGTT size = %lluM\n", vm->total >> 20);
 	DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
 	DRM_DEBUG_DRIVER("DSM size = %lluM\n",
 			 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
@@ -3577,20 +3589,21 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
 
 static int ggtt_init_hw(struct i915_ggtt *ggtt)
 {
-	struct drm_i915_private *i915 = ggtt->vm.i915;
+	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *i915 = vm->i915;
 	int ret = 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
 
-	i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
+	i915_address_space_init(vm, VM_CLASS_GGTT);
 
-	ggtt->vm.is_ggtt = true;
+	vm->is_ggtt = true;
 
 	/* Only VLV supports read-only GGTT mappings */
-	ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
+	vm->has_read_only = IS_VALLEYVIEW(i915);
 
 	if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
-		ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
+		vm->mm.color_adjust = i915_gtt_color_adjust;
 
 	if (!io_mapping_init_wc(&ggtt->iomap,
 				ggtt->gmadr.start,
@@ -3681,24 +3694,25 @@ void i915_ggtt_disable_guc(struct drm_i915_private *i915)
 
 static void ggtt_restore_mappings(struct i915_ggtt *ggtt)
 {
+	struct i915_address_space *vm = &ggtt->vm;
 	struct i915_vma *vma, *vn;
 
-	intel_gt_check_and_clear_faults(ggtt->vm.gt);
+	intel_gt_check_and_clear_faults(vm->gt);
 
-	mutex_lock(&ggtt->vm.mutex);
+	mutex_lock(&vm->mutex);
 
 	/* First fill our portion of the GTT with scratch pages */
-	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
-	ggtt->vm.closed = true; /* skip rewriting PTE on VMA unbind */
+	vm->clear_range(vm, 0, vm->total);
+	vm->closed = true; /* skip rewriting PTE on VMA unbind */
 
 	/* clflush objects bound into the GGTT and rebind them. */
-	list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link) {
+	list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
 		struct drm_i915_gem_object *obj = vma->obj;
 
 		if (!(vma->flags & I915_VMA_GLOBAL_BIND))
 			continue;
 
-		mutex_unlock(&ggtt->vm.mutex);
+		mutex_unlock(&vm->mutex);
 
 		if (!i915_vma_unbind(vma))
 			goto lock;
@@ -3713,13 +3727,13 @@ static void ggtt_restore_mappings(struct i915_ggtt *ggtt)
 		}
 
 lock:
-		mutex_lock(&ggtt->vm.mutex);
+		mutex_lock(&vm->mutex);
 	}
 
-	ggtt->vm.closed = false;
+	vm->closed = false;
 	ggtt->invalidate(ggtt);
 
-	mutex_unlock(&ggtt->vm.mutex);
+	mutex_unlock(&vm->mutex);
 }
 
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
@@ -3730,7 +3744,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 		struct intel_ppat *ppat = &dev_priv->ppat;
 
 		bitmap_set(ppat->dirty, 0, ppat->max_entries);
-		dev_priv->ppat.update_hw(dev_priv);
+		ppat->update_hw(dev_priv);
 		return;
 	}
 }
-- 
2.20.1

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Re: [RFC 01/28] drm/i915: Convert intel_vgt_(de)balloon to uncore

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:12)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> More removal of implicit dev_priv from using old mmio accessors.
> 
> Furthermore these calls really operate on ggtt so it logically makes sense
> if they take it as parameter.

Yeah, I had expected them to take a vgpu, but these are functions that
steal from the global GTT.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c |  4 ++--
>  drivers/gpu/drm/i915/i915_vgpu.c    | 24 ++++++++++++++----------
>  drivers/gpu/drm/i915/i915_vgpu.h    |  4 ++--
>  3 files changed, 18 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7be72388b052..90d9669ff313 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2859,7 +2859,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>         ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
>                                intel_wopcm_guc_size(&dev_priv->wopcm));
>  
> -       ret = intel_vgt_balloon(dev_priv);
> +       ret = intel_vgt_balloon(ggtt);
>         if (ret)
>                 return ret;
>  
> @@ -2930,7 +2930,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
>         ggtt_release_guc_top(ggtt);
>  
>         if (drm_mm_initialized(&ggtt->vm.mm)) {
> -               intel_vgt_deballoon(dev_priv);
> +               intel_vgt_deballoon(ggtt);

As noted elsewhere, the init/fini sequence here is skewiff.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 02/28] drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:13)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> We have long been slighlty annoyed by the anonymous i915->gt.
> 
> Promote it to a separate structure and give it its own header.
> 
> This is a first step towards cleaning up the separation between i915 and gt.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 03/28] drm/i915: Move intel_gt initialization to a separate file

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:14)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> As it will grow in a following patch make a new home for it.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile      |  1 +
>  drivers/gpu/drm/i915/gt/intel_gt.c | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h | 14 ++++++++++++++
>  drivers/gpu/drm/i915/i915_gem.c    |  9 ++-------
>  4 files changed, 36 insertions(+), 7 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
>  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index c0a7b2994077..8df1bf2855d0 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -73,6 +73,7 @@ gt-y += \
>         gt/intel_context.o \
>         gt/intel_engine_cs.o \
>         gt/intel_engine_pm.o \
> +       gt/intel_gt.o \
>         gt/intel_gt_pm.o \
>         gt/intel_hangcheck.o \
>         gt/intel_lrc.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> new file mode 100644
> index 000000000000..e91ffd2dc4fa
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -0,0 +1,19 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include "intel_gt.h"
> +
> +void intel_gt_init(struct intel_gt *gt)
> +{
> +       static struct lock_class_key reset_key;
> +
> +       INIT_LIST_HEAD(&gt->active_rings);
> +       INIT_LIST_HEAD(&gt->closed_vma);
> +
> +       spin_lock_init(&gt->closed_lock);
> +
> +       lockdep_init_map(&gt->reset_lockmap, "i915.reset", &reset_key, 0);
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> new file mode 100644
> index 000000000000..d0b599dd6d0f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -0,0 +1,14 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef __INTEL_GT__
> +#define __INTEL_GT__
> +
> +#include "gt/intel_gt_types.h"
> +
> +void intel_gt_init(struct intel_gt *gt);
> +
> +#endif /* __INTEL_GT_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4bbded4aa936..d5897e13897b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -44,6 +44,7 @@
>  #include "gem/i915_gem_pm.h"
>  #include "gem/i915_gemfs.h"
>  #include "gt/intel_engine_pm.h"
> +#include "gt/intel_gt.h"
>  #include "gt/intel_gt_pm.h"
>  #include "gt/intel_mocs.h"
>  #include "gt/intel_reset.h"
> @@ -1746,17 +1747,11 @@ static void i915_gem_init__mm(struct drm_i915_private *i915)
>  
>  int i915_gem_init_early(struct drm_i915_private *dev_priv)
>  {
> -       static struct lock_class_key reset_key;
>         int err;
>  
> +       intel_gt_init(&dev_priv->gt);
>         intel_gt_pm_init(dev_priv);
>  
> -       INIT_LIST_HEAD(&dev_priv->gt.active_rings);
> -       INIT_LIST_HEAD(&dev_priv->gt.closed_vma);
> -       spin_lock_init(&dev_priv->gt.closed_lock);
> -       lockdep_init_map(&dev_priv->gt.reset_lockmap,
> -                        "i915.reset", &reset_key, 0);
> -
>         i915_gem_init__mm(dev_priv);
>         i915_gem_init__pm(dev_priv);

Please also fixup mock_gem_device to use the new function.
-Chris
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Re: [RFC 04/28] drm/i915: Store some backpointers in struct intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:15)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> We need an easy way to get back to i915 and uncore.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c       | 7 ++++++-
>  drivers/gpu/drm/i915/gt/intel_gt.h       | 4 +++-
>  drivers/gpu/drm/i915/gt/intel_gt_types.h | 6 ++++++
>  drivers/gpu/drm/i915/i915_gem.c          | 2 +-
>  4 files changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index e91ffd2dc4fa..29e8dc766ba4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -4,12 +4,17 @@
>   * Copyright © 2019 Intel Corporation
>   */
>  
> +#include "i915_drv.h"
> +
>  #include "intel_gt.h"
>  
> -void intel_gt_init(struct intel_gt *gt)
> +void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915)
>  {
>         static struct lock_class_key reset_key;
>  
> +       gt->i915 = i915;
> +       gt->uncore = &i915->uncore;
> +
>         INIT_LIST_HEAD(&gt->active_rings);
>         INIT_LIST_HEAD(&gt->closed_vma);
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index d0b599dd6d0f..f57ff3758f54 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -9,6 +9,8 @@
>  
>  #include "gt/intel_gt_types.h"
>  
> -void intel_gt_init(struct intel_gt *gt);
> +struct drm_i915_private;
> +
> +void intel_gt_init(struct intel_gt *gt, struct drm_i915_private *i915);
>  
>  #endif /* __INTEL_GT_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index cf32ca401b74..99e30f8cfbe0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -17,7 +17,13 @@
>  #include "i915_vma.h"
>  #include "intel_wakeref.h"
>  
> +struct drm_i915_private;
> +struct intel_uncore;
> +
>  struct intel_gt {
> +       struct drm_i915_private *i915;
> +       struct intel_uncore *uncore;
> +
>         struct i915_gt_timelines {
>                 struct mutex mutex; /* protects list, tainted by GPU */
>                 struct list_head active_list;
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index d5897e13897b..7fdf252f9322 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1749,7 +1749,7 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
>  {
>         int err;
>  
> -       intel_gt_init(&dev_priv->gt);
> +       intel_gt_init(&dev_priv->gt, dev_priv);
>         intel_gt_pm_init(dev_priv);
>  
>         i915_gem_init__mm(dev_priv);

Now this definitely requires mock_gem_device fixes.
Nevertheless,

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 05/28] drm/i915: Make i915_check_and_clear_faults take intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:16)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing the conversion and elimination of implicit dev_priv.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 06/28] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:17)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Start using the newly introduced struct intel_gt to fuse together correct
> logical init flow with uncore for more removal of implicit dev_priv in
> mmio access.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Looks fine, I might move it again later next to the fence registers, or
at least pull this and the detection into its own intel_gt_swizzling.c

Hmm, now that I said that, does that seem like a reasonable thing to do
right away, see i915_gem_fence_regs.c for the swizzle probe?
-Chris
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Re: [RFC 07/28] drm/i915: Convert init_unused_rings to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:18)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> More removal of implicit dev_priv from using old mmio accessors.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 08/28] drm/i915: Convert gt workarounds to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:19)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> More conversion of i915_gem_init_hw to uncore.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 09/28] drm/i915: Store backpointer to intel_gt in the engine

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:20)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> It will come useful in the next patch.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 09/28] drm/i915: Store backpointer to intel_gt in the engine

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:20)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> It will come useful in the next patch.

(Does this even constitute a functional change? ;)

> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 10/28] drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:21)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> More removal of implicit dev_priv from using old mmio accessors.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 11/28] drm/i915: Convert i915_ppgtt_init_hw to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:22)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> More removal of implicit dev_priv from using old mmio accessors.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

i915_gem_gtt.[ch] is an outlier at the moment, they need to migrate to
gt/ but are a clumsy mix of high and low level objects.

So while it says i915_gem on the front, intel_gt is the right home.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 13/28] drm/i915: Convert i915_gem_init_hw to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:24)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> More removal of implicit dev_priv from using old mmio accessors.
> 
> Actually the top level function remains but is split into a part which
> writes to i915 and part which operates on intel_gt in order to initialize
> the hardware.
> 
> GuC and engines are the only odd ones out remaining.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 66 ++++++++++++++++++++-------------
>  1 file changed, 40 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e54cd30534dc..b6f450e782e7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
>         }
>  }
>  
> -int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> +static int init_hw(struct intel_gt *gt)
>  {
> +       struct drm_i915_private *i915 = gt->i915;
> +       struct intel_uncore *uncore = gt->uncore;
>         int ret;
>  
> -       dev_priv->gt.last_init_time = ktime_get();
> +       gt->last_init_time = ktime_get();
>  
>         /* Double layer security blanket, see i915_gem_init() */
> -       intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> +       intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>  
> -       if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
> -               I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> +       if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
> +               intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>  
> -       if (IS_HASWELL(dev_priv))
> -               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> -                          LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> +       if (IS_HASWELL(i915))
> +               intel_uncore_write(uncore,
> +                                  MI_PREDICATE_RESULT_2,
> +                                  IS_HSW_GT3(i915) ?
> +                                  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>  
>         /* Apply the GT workarounds... */
> -       intel_gt_apply_workarounds(&dev_priv->gt);
> +       intel_gt_apply_workarounds(gt);

Would it be worth moving the above mmio into workarounds? Whilst you are
doing some spring cleaning :)

>         /* ...and determine whether they are sticking. */
> -       intel_gt_verify_workarounds(&dev_priv->gt, "init");
> +       intel_gt_verify_workarounds(gt, "init");
>  
> -       intel_gt_init_swizzling(&dev_priv->gt);
> +       intel_gt_init_swizzling(gt);
>  
>         /*
>          * At least 830 can leave some of the unused rings
> @@ -1263,48 +1267,58 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>          * will prevent c3 entry. Makes sure all unused rings
>          * are totally idle.
>          */
> -       init_unused_rings(&dev_priv->gt);
> -
> -       BUG_ON(!dev_priv->kernel_context);
> -       ret = i915_terminally_wedged(dev_priv);
> -       if (ret)
> -               goto out;
> +       init_unused_rings(gt);
>  
> -       ret = i915_ppgtt_init_hw(&dev_priv->gt);
> +       ret = i915_ppgtt_init_hw(gt);
>         if (ret) {
>                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
>                 goto out;
>         }
>  
> -       ret = intel_wopcm_init_hw(&dev_priv->wopcm);
> +       ret = intel_wopcm_init_hw(&i915->wopcm);
>         if (ret) {
>                 DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
>                 goto out;
>         }
>  
>         /* We can't enable contexts until all firmware is loaded */
> -       ret = intel_uc_init_hw(dev_priv);
> +       ret = intel_uc_init_hw(i915);

Sorting out the uc layering is an ongoing task. I think it probably
means our init_hw needs splitting.

>         if (ret) {
>                 DRM_ERROR("Enabling uc failed (%d)\n", ret);
>                 goto out;
>         }
>  
> -       intel_mocs_init_l3cc_table(&dev_priv->gt);
> +       intel_mocs_init_l3cc_table(gt);
>  
>         /* Only when the HW is re-initialised, can we replay the requests */
> -       ret = intel_engines_resume(dev_priv);
> +       ret = intel_engines_resume(i915);
>         if (ret)
>                 goto cleanup_uc;
>  
> -       intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> +       intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>  
> -       intel_engines_set_scheduler_caps(dev_priv);
>         return 0;
>  
>  cleanup_uc:
> -       intel_uc_fini_hw(dev_priv);
> +       intel_uc_fini_hw(i915);
>  out:
> -       intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> +       intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> +
> +       return ret;
> +}
> +
> +int i915_gem_init_hw(struct drm_i915_private *i915)

Do we also start to recognise this as i915_init_hw()? This is the driver
talking to the intel_gt and friends, not the driver setting up the GEM
api.
-Chris
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Re: [RFC 14/28] drm/i915: Move intel_engines_resume into common init

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:25)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Since this part still operates on i915 and not intel_gt, move it to the
> common (top-level) function.

Whilst I do agree with the splitting, I will note that
intel_engines_resume() operates within gt :) You just haven't moved the
engine list over to intel_gt yet :)

> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

It's an improvement, just leaves me wanting more
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 16/28] drm/i915: Compartmentalize i915_ggtt_probe_hw

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:27)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Having made start to better code compartmentalization by introducing
> struct intel_gt, continue the theme elsewhere in code by making functions
> take parameters take what logically makes most sense for them instead of
> the global struct drm_i915_private.

Is that a can of worms I see? :)

While you are here, care to pull in the gmch probe so we can drop the
frankenstein approach.
-Chris
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Re: [RFC 17/28] drm/i915: Compartmentalize i915_ggtt_init_hw

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:28)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Having made start to better code compartmentalization by introducing
> struct intel_gt, continue the theme elsewhere in code by making functions
> take parameters take what logically makes most sense for them instead of
> the global struct drm_i915_private.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Fair enough,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Tiny conflicts ahoy with struct_mutex removal.
-Chris
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Re: [RFC 18/28] drm/i915: Make ggtt invalidation work on ggtt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:29)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> It is more logical for ggtt invalidation to take ggtt as input parameter.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

There's a great saying about not bringing logic into driver development.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 20/28] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:31)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Having made start to better code compartmentalization by introducing
> struct intel_gt, continue the theme elsewhere in code by making functions
> take parameters take what logically makes most sense for them instead of
> the global struct drm_i915_private.

So I am debating whether this is better off as part of i915_ggtt and not
i915_address_space.
-Chris
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Re: [RFC 21/28] drm/i915/gtt: Reduce source verbosity by caching repeated dereferences

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 14:35:32)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> There is a lot of code in i915_gem_gtt.c which repeatadly dereferences
> either ggtt or ppgtt in order to get to the vm. Cache those accesses in
> local variables for better readability.

There isn't a dereference though, it's just using the base struct. Meh.

I don't really mind, but I chose to write it the other way, specifically
using vm to keep it short.

At the end of the day, the compiler *should* eliminate the redundant
local, so it is merely a matter of which readers prefer. I think I still
have a slight preference to using ppgtt throughout rather than mixing
ppgtt and vm for the same object.

> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 254 +++++++++++++++-------------
>  1 file changed, 134 insertions(+), 120 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 516ffc4a521a..d09a4d9b71da 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1004,10 +1004,11 @@ gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
>  {
>         struct i915_page_directory *pd;
>         const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
> +       struct i915_address_space *vm = &ppgtt->vm;
>         gen8_pte_t *vaddr;
>         bool ret;
>  
> -       GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
> +       GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(vm));
>         pd = pdp->page_directory[idx->pdpe];
>         vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
>         do {
> @@ -1038,7 +1039,7 @@ gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
>                                         break;
>                                 }
>  
> -                               GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
> +                               GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(vm));

I don't see any code here. :-p
-Chris
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[RFC 22/28] drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having introduced struct intel_gt (named the anonymous structure in i915)
we can start using it to compartmentalize our code better. It makes more
sense logically to have the code internally like this and it will also
help with future split between gt and display in i915.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c    |  5 +--
 .../drm/i915/gem/selftests/i915_gem_mman.c    |  3 +-
 drivers/gpu/drm/i915/gt/intel_gt.c            | 41 +++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h            |  2 +
 drivers/gpu/drm/i915/i915_drv.h               |  2 -
 drivers/gpu/drm/i915/i915_gem.c               | 40 ------------------
 drivers/gpu/drm/i915/i915_vma.c               |  3 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  2 +-
 8 files changed, 50 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 36b76c6a0a9d..9ae7743348f2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -27,6 +27,7 @@
 #include "i915_gem_context.h"
 #include "i915_gem_object.h"
 #include "i915_globals.h"
+#include "gt/intel_gt.h"
 #include "intel_frontbuffer.h"
 
 static struct i915_global_object {
@@ -367,7 +368,6 @@ void
 i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 				   unsigned int flush_domains)
 {
-	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 	struct i915_vma *vma;
 
 	assert_object_held(obj);
@@ -377,8 +377,6 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 
 	switch (obj->write_domain) {
 	case I915_GEM_DOMAIN_GTT:
-		i915_gem_flush_ggtt_writes(dev_priv);
-
 		intel_fb_obj_flush(obj,
 				   fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
 
@@ -386,6 +384,7 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 			if (vma->iomap)
 				continue;
 
+			intel_gt_flush_ggtt_writes(vma->vm->gt);
 			i915_vma_unset_ggtt_write(vma);
 		}
 		break;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index b92809418729..b46d57967bfa 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -6,6 +6,7 @@
 
 #include <linux/prime_numbers.h>
 
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "huge_gem_object.h"
 #include "i915_selftest.h"
@@ -143,7 +144,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
 		if (offset >= obj->base.size)
 			continue;
 
-		i915_gem_flush_ggtt_writes(to_i915(obj->base.dev));
+		intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
 
 		p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
 		cpu = kmap(p) + offset_in_page(offset);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index c6a67393ee72..7bf01365573a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -188,3 +188,44 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
 	else
 		MISSING_CASE(INTEL_GEN(i915));
 }
+
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	intel_wakeref_t wakeref;
+
+	/*
+	 * No actual flushing is required for the GTT write domain for reads
+	 * from the GTT domain. Writes to it "immediately" go to main memory
+	 * as far as we know, so there's no chipset flush. It also doesn't
+	 * land in the GPU render cache.
+	 *
+	 * However, we do have to enforce the order so that all writes through
+	 * the GTT land before any writes to the device, such as updates to
+	 * the GATT itself.
+	 *
+	 * We also have to wait a bit for the writes to land from the GTT.
+	 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
+	 * timing. This issue has only been observed when switching quickly
+	 * between GTT writes and CPU reads from inside the kernel on recent hw,
+	 * and it appears to only affect discrete GTT blocks (i.e. on LLC
+	 * system agents we cannot reproduce this behaviour, until Cannonlake
+	 * that was!).
+	 */
+
+	wmb();
+
+	if (INTEL_INFO(i915)->has_coherent_ggtt)
+		return;
+
+	i915_gem_chipset_flush(i915);
+
+	with_intel_runtime_pm(i915, wakeref) {
+		struct intel_uncore *uncore = gt->uncore;
+
+		spin_lock_irq(&uncore->lock);
+		intel_uncore_posting_read_fw(uncore,
+					     RING_HEAD(RENDER_RING_BASE));
+		spin_unlock_irq(&uncore->lock);
+	}
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index e026b2dc1115..700bb56d1e9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -20,4 +20,6 @@ void intel_gt_clear_error_registers(struct intel_gt *gt,
 
 void intel_gt_init_swizzling(struct intel_gt *gt);
 
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
+
 #endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1eb203fdee60..4987a048b3d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2648,8 +2648,6 @@ int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
 					 unsigned int flags);
 int i915_gem_evict_vm(struct i915_address_space *vm);
 
-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
-
 /* belongs in i915_gem_gtt.h */
 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b7f88e2bd7df..4f9aac62a8a4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -233,46 +233,6 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
 			       &args->size, &args->handle);
 }
 
-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
-{
-	intel_wakeref_t wakeref;
-
-	/*
-	 * No actual flushing is required for the GTT write domain for reads
-	 * from the GTT domain. Writes to it "immediately" go to main memory
-	 * as far as we know, so there's no chipset flush. It also doesn't
-	 * land in the GPU render cache.
-	 *
-	 * However, we do have to enforce the order so that all writes through
-	 * the GTT land before any writes to the device, such as updates to
-	 * the GATT itself.
-	 *
-	 * We also have to wait a bit for the writes to land from the GTT.
-	 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
-	 * timing. This issue has only been observed when switching quickly
-	 * between GTT writes and CPU reads from inside the kernel on recent hw,
-	 * and it appears to only affect discrete GTT blocks (i.e. on LLC
-	 * system agents we cannot reproduce this behaviour, until Cannonlake
-	 * that was!).
-	 */
-
-	wmb();
-
-	if (INTEL_INFO(dev_priv)->has_coherent_ggtt)
-		return;
-
-	i915_gem_chipset_flush(dev_priv);
-
-	with_intel_runtime_pm(dev_priv, wakeref) {
-		struct intel_uncore *uncore = &dev_priv->uncore;
-
-		spin_lock_irq(&uncore->lock);
-		intel_uncore_posting_read_fw(uncore,
-					     RING_HEAD(RENDER_RING_BASE));
-		spin_unlock_irq(&uncore->lock);
-	}
-}
-
 static int
 shmem_pread(struct page *page, int offset, int len, char __user *user_data,
 	    bool needs_clflush)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index cb341e4acf99..4f4695c351af 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -23,6 +23,7 @@
  */
 
 #include "gt/intel_engine.h"
+#include "gt/intel_gt.h"
 
 #include "i915_vma.h"
 
@@ -408,7 +409,7 @@ void i915_vma_flush_writes(struct i915_vma *vma)
 	if (!i915_vma_has_ggtt_write(vma))
 		return;
 
-	i915_gem_flush_ggtt_writes(vma->vm->i915);
+	intel_gt_flush_ggtt_writes(vma->vm->gt);
 
 	i915_vma_unset_ggtt_write(vma);
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 2093d08a7569..a67f0e9b4d5f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1195,7 +1195,7 @@ static int igt_ggtt_page(void *arg)
 		iowrite32(n, vaddr + n);
 		io_mapping_unmap_atomic(vaddr);
 	}
-	i915_gem_flush_ggtt_writes(i915);
+	intel_gt_flush_ggtt_writes(ggtt->vm.gt);
 
 	i915_random_reorder(order, count, &prng);
 	for (n = 0; n < count; n++) {
-- 
2.20.1

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[RFC 23/28] drm/i915: Compartmentalize timeline_init/park/fini

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing on the theme of better logical organization of our code, make
the first step towards making the timeline code better isolated from wider
struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_timeline.c | 67 +++++++++++++++++-----------
 1 file changed, 41 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_timeline.c b/drivers/gpu/drm/i915/i915_timeline.c
index 000e1a9b6750..4f1b696be42a 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -262,18 +262,23 @@ int i915_timeline_init(struct drm_i915_private *i915,
 	return 0;
 }
 
-void i915_timelines_init(struct drm_i915_private *i915)
+static void timelines_init(struct intel_gt *gt)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct i915_gt_timelines *timelines = &gt->timelines;
 
-	mutex_init(&gt->mutex);
-	INIT_LIST_HEAD(&gt->active_list);
+	mutex_init(&timelines->mutex);
+	INIT_LIST_HEAD(&timelines->active_list);
 
-	spin_lock_init(&gt->hwsp_lock);
-	INIT_LIST_HEAD(&gt->hwsp_free_list);
+	spin_lock_init(&timelines->hwsp_lock);
+	INIT_LIST_HEAD(&timelines->hwsp_free_list);
 
 	/* via i915_gem_wait_for_idle() */
-	i915_gem_shrinker_taints_mutex(i915, &gt->mutex);
+	i915_gem_shrinker_taints_mutex(gt->i915, &timelines->mutex);
+}
+
+void i915_timelines_init(struct drm_i915_private *i915)
+{
+	timelines_init(&i915->gt);
 }
 
 static void timeline_add_to_active(struct i915_timeline *tl)
@@ -294,6 +299,24 @@ static void timeline_remove_from_active(struct i915_timeline *tl)
 	mutex_unlock(&gt->mutex);
 }
 
+static void timelines_park(struct intel_gt *gt)
+{
+	struct i915_gt_timelines *timelines = &gt->timelines;
+	struct i915_timeline *timeline;
+
+	mutex_lock(&timelines->mutex);
+	list_for_each_entry(timeline, &timelines->active_list, link) {
+		/*
+		 * All known fences are completed so we can scrap
+		 * the current sync point tracking and start afresh,
+		 * any attempt to wait upon a previous sync point
+		 * will be skipped as the fence was signaled.
+		 */
+		i915_syncmap_free(&timeline->sync);
+	}
+	mutex_unlock(&timelines->mutex);
+}
+
 /**
  * i915_timelines_park - called when the driver idles
  * @i915: the drm_i915_private device
@@ -306,20 +329,7 @@ static void timeline_remove_from_active(struct i915_timeline *tl)
  */
 void i915_timelines_park(struct drm_i915_private *i915)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
-	struct i915_timeline *timeline;
-
-	mutex_lock(&gt->mutex);
-	list_for_each_entry(timeline, &gt->active_list, link) {
-		/*
-		 * All known fences are completed so we can scrap
-		 * the current sync point tracking and start afresh,
-		 * any attempt to wait upon a previous sync point
-		 * will be skipped as the fence was signaled.
-		 */
-		i915_syncmap_free(&timeline->sync);
-	}
-	mutex_unlock(&gt->mutex);
+	timelines_park(&i915->gt);
 }
 
 void i915_timeline_fini(struct i915_timeline *timeline)
@@ -564,14 +574,19 @@ void __i915_timeline_free(struct kref *kref)
 	kfree(timeline);
 }
 
-void i915_timelines_fini(struct drm_i915_private *i915)
+static void timelines_fini(struct intel_gt *gt)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct i915_gt_timelines *timelines = &gt->timelines;
 
-	GEM_BUG_ON(!list_empty(&gt->active_list));
-	GEM_BUG_ON(!list_empty(&gt->hwsp_free_list));
+	GEM_BUG_ON(!list_empty(&timelines->active_list));
+	GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
 
-	mutex_destroy(&gt->mutex);
+	mutex_destroy(&timelines->mutex);
+}
+
+void i915_timelines_fini(struct drm_i915_private *i915)
+{
+	timelines_fini(&i915->gt);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-- 
2.20.1

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[RFC 24/28] drm/i915: Compartmentalize i915_ggtt_cleanup_hw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing on the theme of better logical organization of our code, make
the first step towards making the ggtt code better isolated from wider
struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 54 +++++++++++++++++------------
 1 file changed, 31 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d09a4d9b71da..285a7a02c015 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2832,6 +2832,8 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
 	struct i915_ggtt *ggtt = &i915->ggtt;
 	struct i915_ppgtt *ppgtt;
 
+	mutex_lock(&i915->drm.struct_mutex);
+
 	ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
 	if (!ppgtt)
 		return;
@@ -2840,6 +2842,8 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
 
 	ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
 	ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
+
+	mutex_unlock(&i915->drm.struct_mutex);
 }
 
 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
@@ -2941,21 +2945,15 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
-/**
- * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
- * @dev_priv: i915 device
- */
-void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
+static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *i915 = vm->i915;
 	struct i915_vma *vma, *vn;
-	struct pagevec *pvec;
 
 	vm->closed = true;
 
-	mutex_lock(&dev_priv->drm.struct_mutex);
-	fini_aliasing_ppgtt(dev_priv);
+	mutex_lock(&i915->drm.struct_mutex);
 
 	list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link)
 		WARN_ON(i915_vma_unbind(vma));
@@ -2972,18 +2970,33 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 
 	vm->cleanup(vm);
 
-	pvec = &dev_priv->mm.wc_stash.pvec;
+	mutex_unlock(&i915->drm.struct_mutex);
+
+	arch_phys_wc_del(ggtt->mtrr);
+	io_mapping_fini(&ggtt->iomap);
+}
+
+/**
+ * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
+ * @dev_priv: i915 device
+ */
+void i915_ggtt_cleanup_hw(struct drm_i915_private *i915)
+{
+	struct pagevec *pvec;
+
+	fini_aliasing_ppgtt(i915);
+
+	ggtt_cleanup_hw(&i915->ggtt);
+
+	mutex_lock(&i915->drm.struct_mutex);
+	pvec = &i915->mm.wc_stash.pvec;
 	if (pvec->nr) {
 		set_pages_array_wb(pvec->pages, pvec->nr);
 		__pagevec_release(pvec);
 	}
+	mutex_unlock(&i915->drm.struct_mutex);
 
-	mutex_unlock(&dev_priv->drm.struct_mutex);
-
-	arch_phys_wc_del(ggtt->mtrr);
-	io_mapping_fini(&ggtt->iomap);
-
-	i915_gem_cleanup_stolen(dev_priv);
+	i915_gem_cleanup_stolen(i915);
 }
 
 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3582,11 +3595,6 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
 	return 0;
 }
 
-static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
-{
-	ggtt->vm.cleanup(&ggtt->vm);
-}
-
 static int ggtt_init_hw(struct i915_ggtt *ggtt)
 {
 	struct i915_address_space *vm = &ggtt->vm;
@@ -3608,7 +3616,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
 	if (!io_mapping_init_wc(&ggtt->iomap,
 				ggtt->gmadr.start,
 				ggtt->mappable_end)) {
-		ggtt_cleanup_hw(ggtt);
+		vm->cleanup(vm);
 		ret = -EIO;
 		goto out;
 	}
@@ -3653,7 +3661,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
 	return 0;
 
 out_gtt_cleanup:
-	ggtt_cleanup_hw(&dev_priv->ggtt);
+	dev_priv->ggtt.vm.cleanup(&dev_priv->ggtt.vm);
 	return ret;
 }
 
-- 
2.20.1

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[RFC 25/28] drm/i915: Compartmentalize i915_gem_init_ggtt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing on the theme of better logical organization of our code, make
the first step towards making the ggtt code better isolated from wider
struct drm_i915_private.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++++----------
 1 file changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 285a7a02c015..ea276ed9021a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2873,7 +2873,13 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
 		drm_mm_remove_node(&ggtt->uc_fw);
 }
 
-int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
+static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
+{
+	ggtt_release_guc_top(ggtt);
+	drm_mm_remove_node(&ggtt->error_capture);
+}
+
+static int init_ggtt(struct i915_ggtt *ggtt)
 {
 	/* Let GEM Manage all of the aperture.
 	 *
@@ -2884,7 +2890,6 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 * aperture.  One page should be enough to keep any prefetching inside
 	 * of the aperture.
 	 */
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	struct i915_address_space *vm = &ggtt->vm;
 	unsigned long hole_start, hole_end;
 	struct drm_mm_node *entry;
@@ -2897,7 +2902,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 * why.
 	 */
 	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
-			       intel_wopcm_guc_size(&dev_priv->wopcm));
+			       intel_wopcm_guc_size(&vm->i915->wopcm));
 
 	ret = intel_vgt_balloon(ggtt);
 	if (ret)
@@ -2917,8 +2922,10 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 * GGTT as it can comfortably hold GuC/HuC firmware images.
 	 */
 	ret = ggtt_reserve_guc_top(ggtt);
-	if (ret)
-		goto err_reserve;
+	if (ret) {
+		cleanup_init_ggtt(ggtt);
+		return ret;
+	}
 
 	/* Clear any non-preallocated blocks */
 	drm_mm_for_each_hole(entry, &vm->mm, hole_start, hole_end) {
@@ -2930,19 +2937,24 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	vm->clear_range(vm, vm->total - PAGE_SIZE, PAGE_SIZE);
 
-	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
-		ret = init_aliasing_ppgtt(dev_priv);
+	return 0;
+}
+
+int i915_gem_init_ggtt(struct drm_i915_private *i915)
+{
+	int ret;
+
+	ret = init_ggtt(&i915->ggtt);
+	if (ret)
+		return ret;
+
+	if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
+		ret = init_aliasing_ppgtt(i915);
 		if (ret)
-			goto err_appgtt;
+			cleanup_init_ggtt(&i915->ggtt);
 	}
 
 	return 0;
-
-err_appgtt:
-	ggtt_release_guc_top(ggtt);
-err_reserve:
-	drm_mm_remove_node(&ggtt->error_capture);
-	return ret;
 }
 
 static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
-- 
2.20.1

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[RFC 26/28] drm/i915: Store ggtt pointer in intel_gt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This will become useful in the following patch.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c      | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 99e30f8cfbe0..c909aae6e4b3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -18,11 +18,13 @@
 #include "intel_wakeref.h"
 
 struct drm_i915_private;
+struct i915_ggtt;
 struct intel_uncore;
 
 struct intel_gt {
 	struct drm_i915_private *i915;
 	struct intel_uncore *uncore;
+	struct i915_ggtt *ggtt;
 
 	struct i915_gt_timelines {
 		struct mutex mutex; /* protects list, tainted by GPU */
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ea276ed9021a..9aa25770081c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3618,6 +3618,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
 	i915_address_space_init(vm, VM_CLASS_GGTT);
 
 	vm->is_ggtt = true;
+	vm->gt->ggtt = ggtt;
 
 	/* Only VLV supports read-only GGTT mappings */
 	vm->has_read_only = IS_VALLEYVIEW(i915);
-- 
2.20.1

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[RFC 27/28] drm/i915: Compartmentalize ring buffer creation

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing on the theme of compartmentalizing the code better to make
future split between gt and display in global i915 clearer.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index b3bf47e8162f..0a1d952ad160 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1226,16 +1226,16 @@ void intel_ring_unpin(struct intel_ring *ring)
 	i915_timeline_unpin(ring->timeline);
 }
 
-static struct i915_vma *
-intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
+static struct i915_vma *create_ring_vma(struct intel_gt *gt, int size)
 {
-	struct i915_address_space *vm = &dev_priv->ggtt.vm;
+	struct i915_address_space *vm = &gt->ggtt->vm;
+	struct drm_i915_private *i915 = gt->i915;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 
-	obj = i915_gem_object_create_stolen(dev_priv, size);
+	obj = i915_gem_object_create_stolen(i915, size);
 	if (!obj)
-		obj = i915_gem_object_create_internal(dev_priv, size);
+		obj = i915_gem_object_create_internal(i915, size);
 	if (IS_ERR(obj))
 		return ERR_CAST(obj);
 
@@ -1262,13 +1262,14 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
 			 struct i915_timeline *timeline,
 			 int size)
 {
+	struct drm_i915_private *i915 = engine->i915;
 	struct intel_ring *ring;
 	struct i915_vma *vma;
 
 	GEM_BUG_ON(!is_power_of_2(size));
 	GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
 	GEM_BUG_ON(timeline == &engine->timeline);
-	lockdep_assert_held(&engine->i915->drm.struct_mutex);
+	lockdep_assert_held(&i915->drm.struct_mutex);
 
 	ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 	if (!ring)
@@ -1284,12 +1285,12 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
 	 * of the buffer.
 	 */
 	ring->effective_size = size;
-	if (IS_I830(engine->i915) || IS_I845G(engine->i915))
+	if (IS_I830(i915) || IS_I845G(i915))
 		ring->effective_size -= 2 * CACHELINE_BYTES;
 
 	intel_ring_update_space(ring);
 
-	vma = intel_ring_create_vma(engine->i915, size);
+	vma = create_ring_vma(engine->gt, size);
 	if (IS_ERR(vma)) {
 		kfree(ring);
 		return ERR_CAST(vma);
-- 
2.20.1

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[RFC 28/28] drm/i915: Make timelines gt centric

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Our timelines are stored inside intel_gt so we can convert the interface
to take exactly that and not i915.

At the same time re-order the params to our more typical layout and
replace the backpointer to the new containing structure.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  8 ++--
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  9 ++--
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c    |  2 +-
 drivers/gpu/drm/i915/gt/mock_engine.c         |  4 +-
 drivers/gpu/drm/i915/i915_timeline.c          | 43 +++++++++----------
 drivers/gpu/drm/i915/i915_timeline.h          |  7 ++-
 drivers/gpu/drm/i915/i915_timeline_types.h    |  2 +-
 .../gpu/drm/i915/selftests/i915_timeline.c    |  8 ++--
 .../gpu/drm/i915/selftests/mock_timeline.c    |  2 +-
 10 files changed, 42 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c86ca9f21532..c52869e58cb5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -530,7 +530,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags)
 	if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
 		struct i915_timeline *timeline;
 
-		timeline = i915_timeline_create(dev_priv, NULL);
+		timeline = i915_timeline_create(&dev_priv->gt, NULL);
 		if (IS_ERR(timeline)) {
 			context_close(ctx);
 			return ERR_CAST(timeline);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c2d87c50dd6f..9196434c9f3f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -618,8 +618,8 @@ static int intel_engine_setup_common(struct intel_engine_cs *engine)
 	if (err)
 		return err;
 
-	err = i915_timeline_init(engine->i915,
-				 &engine->timeline,
+	err = i915_timeline_init(&engine->timeline,
+				 engine->gt,
 				 engine->status_page.vma);
 	if (err)
 		goto err_hwsp;
@@ -745,8 +745,8 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
 	if (!frame)
 		return -ENOMEM;
 
-	if (i915_timeline_init(engine->i915,
-			       &frame->timeline,
+	if (i915_timeline_init(&frame->timeline,
+			       engine->gt,
 			       engine->status_page.vma))
 		goto out_frame;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b8f5592da18f..3713a66d2767 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2984,12 +2984,13 @@ populate_lr_context(struct intel_context *ce,
 	return ret;
 }
 
-static struct i915_timeline *get_timeline(struct i915_gem_context *ctx)
+static struct i915_timeline *
+get_timeline(struct i915_gem_context *ctx, struct intel_gt *gt)
 {
 	if (ctx->timeline)
 		return i915_timeline_get(ctx->timeline);
 	else
-		return i915_timeline_create(ctx->i915, NULL);
+		return i915_timeline_create(gt, NULL);
 }
 
 static int execlists_context_deferred_alloc(struct intel_context *ce,
@@ -3023,7 +3024,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ce,
 		goto error_deref_obj;
 	}
 
-	timeline = get_timeline(ce->gem_context);
+	timeline = get_timeline(ce->gem_context, engine->gt);
 	if (IS_ERR(timeline)) {
 		ret = PTR_ERR(timeline);
 		goto error_deref_obj;
@@ -3343,7 +3344,7 @@ intel_execlists_create_virtual(struct i915_gem_context *ctx,
 
 	snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
 
-	err = i915_timeline_init(ctx->i915, &ve->base.timeline, NULL);
+	err = i915_timeline_init(&ve->base.timeline, siblings[0]->gt, NULL);
 	if (err)
 		goto err_put;
 	i915_timeline_set_subclass(&ve->base.timeline, TIMELINE_VIRTUAL);
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 0a1d952ad160..ac60eb3437d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -2302,7 +2302,7 @@ int intel_ring_submission_init(struct intel_engine_cs *engine)
 	struct intel_ring *ring;
 	int err;
 
-	timeline = i915_timeline_create(engine->i915, engine->status_page.vma);
+	timeline = i915_timeline_create(engine->gt, engine->status_page.vma);
 	if (IS_ERR(timeline)) {
 		err = PTR_ERR(timeline);
 		goto err;
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index 6d7562769eb2..0ebe78ada05b 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -56,7 +56,7 @@ static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
 	if (!ring)
 		return NULL;
 
-	if (i915_timeline_init(engine->i915, &ring->timeline, NULL)) {
+	if (i915_timeline_init(&ring->timeline, engine->gt, NULL)) {
 		kfree(ring);
 		return NULL;
 	}
@@ -283,7 +283,7 @@ int mock_engine_init(struct intel_engine_cs *engine)
 	intel_engine_init_execlists(engine);
 	intel_engine_init__pm(engine);
 
-	if (i915_timeline_init(i915, &engine->timeline, NULL))
+	if (i915_timeline_init(&engine->timeline, engine->gt, NULL))
 		goto err_breadcrumbs;
 	i915_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);
 
diff --git a/drivers/gpu/drm/i915/i915_timeline.c b/drivers/gpu/drm/i915/i915_timeline.c
index 4f1b696be42a..9b62f14ccc07 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -4,6 +4,8 @@
  * Copyright © 2016-2018 Intel Corporation
  */
 
+#include "gt/intel_gt_types.h"
+
 #include "i915_drv.h"
 
 #include "i915_active.h"
@@ -14,7 +16,8 @@
 #define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit))
 
 struct i915_timeline_hwsp {
-	struct i915_gt_timelines *gt;
+	struct intel_gt *gt;
+	struct i915_gt_timelines *gt_timelines;
 	struct list_head free_link;
 	struct i915_vma *vma;
 	u64 free_bitmap;
@@ -28,14 +31,9 @@ struct i915_timeline_cacheline {
 #define CACHELINE_FREE CACHELINE_BITS
 };
 
-static inline struct drm_i915_private *
-hwsp_to_i915(struct i915_timeline_hwsp *hwsp)
-{
-	return container_of(hwsp->gt, struct drm_i915_private, gt.timelines);
-}
-
-static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
+static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 
@@ -45,7 +43,7 @@ static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
 
 	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
 
-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 	if (IS_ERR(vma))
 		i915_gem_object_put(obj);
 
@@ -55,8 +53,7 @@ static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
 static struct i915_vma *
 hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
 {
-	struct drm_i915_private *i915 = timeline->i915;
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct i915_gt_timelines *gt = &timeline->gt->timelines;
 	struct i915_timeline_hwsp *hwsp;
 
 	BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
@@ -75,16 +72,17 @@ hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
 		if (!hwsp)
 			return ERR_PTR(-ENOMEM);
 
-		vma = __hwsp_alloc(i915);
+		vma = __hwsp_alloc(timeline->gt);
 		if (IS_ERR(vma)) {
 			kfree(hwsp);
 			return vma;
 		}
 
 		vma->private = hwsp;
+		hwsp->gt = timeline->gt;
 		hwsp->vma = vma;
 		hwsp->free_bitmap = ~0ull;
-		hwsp->gt = gt;
+		hwsp->gt_timelines = gt;
 
 		spin_lock_irq(&gt->hwsp_lock);
 		list_add(&hwsp->free_link, &gt->hwsp_free_list);
@@ -104,7 +102,7 @@ hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
 
 static void __idle_hwsp_free(struct i915_timeline_hwsp *hwsp, int cacheline)
 {
-	struct i915_gt_timelines *gt = hwsp->gt;
+	struct i915_gt_timelines *gt = hwsp->gt_timelines;
 	unsigned long flags;
 
 	spin_lock_irqsave(&gt->hwsp_lock, flags);
@@ -170,7 +168,7 @@ cacheline_alloc(struct i915_timeline_hwsp *hwsp, unsigned int cacheline)
 	cl->hwsp = hwsp;
 	cl->vaddr = page_pack_bits(vaddr, cacheline);
 
-	i915_active_init(hwsp_to_i915(hwsp), &cl->active, __cacheline_retire);
+	i915_active_init(hwsp->gt->i915, &cl->active, __cacheline_retire);
 
 	return cl;
 }
@@ -196,8 +194,8 @@ static void cacheline_free(struct i915_timeline_cacheline *cl)
 		__idle_cacheline_free(cl);
 }
 
-int i915_timeline_init(struct drm_i915_private *i915,
-		       struct i915_timeline *timeline,
+int i915_timeline_init(struct i915_timeline *timeline,
+		       struct intel_gt *gt,
 		       struct i915_vma *hwsp)
 {
 	void *vaddr;
@@ -212,7 +210,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
 	 */
 	BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
 
-	timeline->i915 = i915;
+	timeline->gt = gt;
 	timeline->pin_count = 0;
 	timeline->has_initial_breadcrumb = !hwsp;
 	timeline->hwsp_cacheline = NULL;
@@ -283,7 +281,7 @@ void i915_timelines_init(struct drm_i915_private *i915)
 
 static void timeline_add_to_active(struct i915_timeline *tl)
 {
-	struct i915_gt_timelines *gt = &tl->i915->gt.timelines;
+	struct i915_gt_timelines *gt = &tl->gt->timelines;
 
 	mutex_lock(&gt->mutex);
 	list_add(&tl->link, &gt->active_list);
@@ -292,7 +290,7 @@ static void timeline_add_to_active(struct i915_timeline *tl)
 
 static void timeline_remove_from_active(struct i915_timeline *tl)
 {
-	struct i915_gt_timelines *gt = &tl->i915->gt.timelines;
+	struct i915_gt_timelines *gt = &tl->gt->timelines;
 
 	mutex_lock(&gt->mutex);
 	list_del(&tl->link);
@@ -348,8 +346,7 @@ void i915_timeline_fini(struct i915_timeline *timeline)
 }
 
 struct i915_timeline *
-i915_timeline_create(struct drm_i915_private *i915,
-		     struct i915_vma *global_hwsp)
+i915_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
 {
 	struct i915_timeline *timeline;
 	int err;
@@ -358,7 +355,7 @@ i915_timeline_create(struct drm_i915_private *i915,
 	if (!timeline)
 		return ERR_PTR(-ENOMEM);
 
-	err = i915_timeline_init(i915, timeline, global_hwsp);
+	err = i915_timeline_init(timeline, gt, global_hwsp);
 	if (err) {
 		kfree(timeline);
 		return ERR_PTR(err);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h b/drivers/gpu/drm/i915/i915_timeline.h
index 27668a1a69a3..8399e11e68b4 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -31,8 +31,8 @@
 #include "i915_syncmap.h"
 #include "i915_timeline_types.h"
 
-int i915_timeline_init(struct drm_i915_private *i915,
-		       struct i915_timeline *tl,
+int i915_timeline_init(struct i915_timeline *tl,
+		       struct intel_gt *gt,
 		       struct i915_vma *hwsp);
 void i915_timeline_fini(struct i915_timeline *tl);
 
@@ -56,8 +56,7 @@ i915_timeline_set_subclass(struct i915_timeline *timeline,
 }
 
 struct i915_timeline *
-i915_timeline_create(struct drm_i915_private *i915,
-		     struct i915_vma *global_hwsp);
+i915_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp);
 
 static inline struct i915_timeline *
 i915_timeline_get(struct i915_timeline *timeline)
diff --git a/drivers/gpu/drm/i915/i915_timeline_types.h b/drivers/gpu/drm/i915/i915_timeline_types.h
index 1688705f4a2b..041709087508 100644
--- a/drivers/gpu/drm/i915/i915_timeline_types.h
+++ b/drivers/gpu/drm/i915/i915_timeline_types.h
@@ -63,7 +63,7 @@ struct i915_timeline {
 	struct i915_syncmap *sync;
 
 	struct list_head link;
-	struct drm_i915_private *i915;
+	struct intel_gt *gt;
 
 	struct kref kref;
 };
diff --git a/drivers/gpu/drm/i915/selftests/i915_timeline.c b/drivers/gpu/drm/i915/selftests/i915_timeline.c
index acb2cc5136b7..57835127563b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/i915_timeline.c
@@ -66,7 +66,7 @@ static int __mock_hwsp_timeline(struct mock_hwsp_freelist *state,
 		unsigned long cacheline;
 		int err;
 
-		tl = i915_timeline_create(state->i915, NULL);
+		tl = i915_timeline_create(&state->i915->gt, NULL);
 		if (IS_ERR(tl))
 			return PTR_ERR(tl);
 
@@ -448,7 +448,7 @@ tl_write(struct i915_timeline *tl, struct intel_engine_cs *engine, u32 value)
 	struct i915_request *rq;
 	int err;
 
-	lockdep_assert_held(&tl->i915->drm.struct_mutex); /* lazy rq refs */
+	lockdep_assert_held(&tl->gt->i915->drm.struct_mutex); /* lazy rq refs */
 
 	err = i915_timeline_pin(tl);
 	if (err) {
@@ -478,7 +478,7 @@ checked_i915_timeline_create(struct drm_i915_private *i915)
 {
 	struct i915_timeline *tl;
 
-	tl = i915_timeline_create(i915, NULL);
+	tl = i915_timeline_create(&i915->gt, NULL);
 	if (IS_ERR(tl))
 		return tl;
 
@@ -660,7 +660,7 @@ static int live_hwsp_wrap(void *arg)
 	mutex_lock(&i915->drm.struct_mutex);
 	wakeref = intel_runtime_pm_get(i915);
 
-	tl = i915_timeline_create(i915, NULL);
+	tl = i915_timeline_create(&i915->gt, NULL);
 	if (IS_ERR(tl)) {
 		err = PTR_ERR(tl);
 		goto out_rpm;
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c b/drivers/gpu/drm/i915/selftests/mock_timeline.c
index e084476469ef..e1a256761d2c 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c
@@ -10,7 +10,7 @@
 
 void mock_timeline_init(struct i915_timeline *timeline, u64 context)
 {
-	timeline->i915 = NULL;
+	timeline->gt = NULL;
 	timeline->fence_context = context;
 
 	spin_lock_init(&timeline->lock);
-- 
2.20.1

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Re: [RFC 22/28] drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 16:18:36)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Having introduced struct intel_gt (named the anonymous structure in i915)
> we can start using it to compartmentalize our code better. It makes more
> sense logically to have the code internally like this and it will also
> help with future split between gt and display in i915.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_object.c    |  5 +--
>  .../drm/i915/gem/selftests/i915_gem_mman.c    |  3 +-
>  drivers/gpu/drm/i915/gt/intel_gt.c            | 41 +++++++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h            |  2 +
>  drivers/gpu/drm/i915/i915_drv.h               |  2 -
>  drivers/gpu/drm/i915/i915_gem.c               | 40 ------------------
>  drivers/gpu/drm/i915/i915_vma.c               |  3 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  2 +-
>  8 files changed, 50 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 36b76c6a0a9d..9ae7743348f2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -27,6 +27,7 @@
>  #include "i915_gem_context.h"
>  #include "i915_gem_object.h"
>  #include "i915_globals.h"
> +#include "gt/intel_gt.h"

g before i

>  #include "intel_frontbuffer.h"
>  
>  static struct i915_global_object {
> @@ -367,7 +368,6 @@ void
>  i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
>                                    unsigned int flush_domains)
>  {
> -       struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
>         struct i915_vma *vma;
>  
>         assert_object_held(obj);
> @@ -377,8 +377,6 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
>  
>         switch (obj->write_domain) {
>         case I915_GEM_DOMAIN_GTT:
> -               i915_gem_flush_ggtt_writes(dev_priv);
> -
>                 intel_fb_obj_flush(obj,
>                                    fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
>  
> @@ -386,6 +384,7 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
>                         if (vma->iomap)
>                                 continue;
>  
> +                       intel_gt_flush_ggtt_writes(vma->vm->gt);
>                         i915_vma_unset_ggtt_write(vma);
>                 }
>                 break;
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index b92809418729..b46d57967bfa 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -6,6 +6,7 @@
>  
>  #include <linux/prime_numbers.h>
>  
> +#include "gt/intel_gt.h"
>  #include "gt/intel_gt_pm.h"
>  #include "huge_gem_object.h"
>  #include "i915_selftest.h"
> @@ -143,7 +144,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
>                 if (offset >= obj->base.size)
>                         continue;
>  
> -               i915_gem_flush_ggtt_writes(to_i915(obj->base.dev));
> +               intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
>  
>                 p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
>                 cpu = kmap(p) + offset_in_page(offset);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index c6a67393ee72..7bf01365573a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -188,3 +188,44 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
>         else
>                 MISSING_CASE(INTEL_GEN(i915));
>  }
> +
> +void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
> +{
> +       struct drm_i915_private *i915 = gt->i915;
> +       intel_wakeref_t wakeref;
> +
> +       /*
> +        * No actual flushing is required for the GTT write domain for reads
> +        * from the GTT domain. Writes to it "immediately" go to main memory
> +        * as far as we know, so there's no chipset flush. It also doesn't
> +        * land in the GPU render cache.
> +        *
> +        * However, we do have to enforce the order so that all writes through
> +        * the GTT land before any writes to the device, such as updates to
> +        * the GATT itself.
> +        *
> +        * We also have to wait a bit for the writes to land from the GTT.
> +        * An uncached read (i.e. mmio) seems to be ideal for the round-trip
> +        * timing. This issue has only been observed when switching quickly
> +        * between GTT writes and CPU reads from inside the kernel on recent hw,
> +        * and it appears to only affect discrete GTT blocks (i.e. on LLC
> +        * system agents we cannot reproduce this behaviour, until Cannonlake
> +        * that was!).
> +        */
> +
> +       wmb();
> +
> +       if (INTEL_INFO(i915)->has_coherent_ggtt)
> +               return;
> +
> +       i915_gem_chipset_flush(i915);

Another gt candidate iirc. It's a magic page in the chipset to force it
to clear caches and pass a GOP.
-Chris
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Re: [RFC 23/28] drm/i915: Compartmentalize timeline_init/park/fini

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 16:18:47)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing on the theme of better logical organization of our code, make
> the first step towards making the timeline code better isolated from wider
> struct drm_i915_private.

Hmm, timelines blur the line with sched/

I haven't yet worked out where to put i915_request and friends. At the
moment, my sketch is that timelines is a consumer of intel_gt and not
sitting inside. i.e. they are as software construct over top of HW.
-Chris
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Re: [RFC 24/28] drm/i915: Compartmentalize i915_ggtt_cleanup_hw

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 16:19:00)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing on the theme of better logical organization of our code, make
> the first step towards making the ggtt code better isolated from wider
> struct drm_i915_private.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 54 +++++++++++++++++------------
>  1 file changed, 31 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d09a4d9b71da..285a7a02c015 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2832,6 +2832,8 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
>         struct i915_ggtt *ggtt = &i915->ggtt;
>         struct i915_ppgtt *ppgtt;
>  
> +       mutex_lock(&i915->drm.struct_mutex);

Do we still need to appease lockdep here? Hopefully not.

> +
>         ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
>         if (!ppgtt)
>                 return;
> @@ -2840,6 +2842,8 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
>  
>         ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
>         ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
> +
> +       mutex_unlock(&i915->drm.struct_mutex);
>  }
>  
>  static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
> @@ -2941,21 +2945,15 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>         return ret;
>  }
>  
> -/**
> - * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
> - * @dev_priv: i915 device
> - */
> -void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
> +static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
>  {
> -       struct i915_ggtt *ggtt = &dev_priv->ggtt;
>         struct i915_address_space *vm = &ggtt->vm;
> +       struct drm_i915_private *i915 = vm->i915;
>         struct i915_vma *vma, *vn;
> -       struct pagevec *pvec;
>  
>         vm->closed = true;
>  
> -       mutex_lock(&dev_priv->drm.struct_mutex);
> -       fini_aliasing_ppgtt(dev_priv);
> +       mutex_lock(&i915->drm.struct_mutex);

As the lock here is just for the i915_vma_unbind and not
fini_aliasing_ppgtt.

>         list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link)
>                 WARN_ON(i915_vma_unbind(vma));
> @@ -2972,18 +2970,33 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
>  
>         vm->cleanup(vm);
>  
> -       pvec = &dev_priv->mm.wc_stash.pvec;
> +       mutex_unlock(&i915->drm.struct_mutex);
> +
> +       arch_phys_wc_del(ggtt->mtrr);
> +       io_mapping_fini(&ggtt->iomap);
> +}
> +
> +/**
> + * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
> + * @dev_priv: i915 device
> + */
> +void i915_ggtt_cleanup_hw(struct drm_i915_private *i915)
> +{
> +       struct pagevec *pvec;
> +
> +       fini_aliasing_ppgtt(i915);
> +
> +       ggtt_cleanup_hw(&i915->ggtt);
> +
> +       mutex_lock(&i915->drm.struct_mutex);
> +       pvec = &i915->mm.wc_stash.pvec;
>         if (pvec->nr) {
>                 set_pages_array_wb(pvec->pages, pvec->nr);
>                 __pagevec_release(pvec);
>         }
> +       mutex_unlock(&i915->drm.struct_mutex);

The wc_stash doesn't use struct_mutex, so no lockdep appeasing required
here.

In general looks good, just too heavy handed on keeping struct_mutex
about.
-Chris
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Re: [RFC 25/28] drm/i915: Compartmentalize i915_gem_init_ggtt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 16:19:01)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing on the theme of better logical organization of our code, make
> the first step towards making the ggtt code better isolated from wider
> struct drm_i915_private.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++++----------
>  1 file changed, 26 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 285a7a02c015..ea276ed9021a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2873,7 +2873,13 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
>                 drm_mm_remove_node(&ggtt->uc_fw);
>  }
>  
> -int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
> +static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
> +{
> +       ggtt_release_guc_top(ggtt);
> +       drm_mm_remove_node(&ggtt->error_capture);
> +}
> +
> +static int init_ggtt(struct i915_ggtt *ggtt)
>  {
>         /* Let GEM Manage all of the aperture.
>          *
> @@ -2884,7 +2890,6 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>          * aperture.  One page should be enough to keep any prefetching inside
>          * of the aperture.
>          */
> -       struct i915_ggtt *ggtt = &dev_priv->ggtt;
>         struct i915_address_space *vm = &ggtt->vm;
>         unsigned long hole_start, hole_end;
>         struct drm_mm_node *entry;
> @@ -2897,7 +2902,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>          * why.
>          */
>         ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
> -                              intel_wopcm_guc_size(&dev_priv->wopcm));
> +                              intel_wopcm_guc_size(&vm->i915->wopcm));
>  
>         ret = intel_vgt_balloon(ggtt);
>         if (ret)
> @@ -2917,8 +2922,10 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>          * GGTT as it can comfortably hold GuC/HuC firmware images.
>          */
>         ret = ggtt_reserve_guc_top(ggtt);
> -       if (ret)
> -               goto err_reserve;
> +       if (ret) {
> +               cleanup_init_ggtt(ggtt);

Joonas would be turning in his grave, can you not hear the haunting call
of onions?

> +               return ret;
> +       }
>  
>         /* Clear any non-preallocated blocks */
>         drm_mm_for_each_hole(entry, &vm->mm, hole_start, hole_end) {
> @@ -2930,19 +2937,24 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>         /* And finally clear the reserved guard page */
>         vm->clear_range(vm, vm->total - PAGE_SIZE, PAGE_SIZE);
>  
> -       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
> -               ret = init_aliasing_ppgtt(dev_priv);
> +       return 0;
> +}
> +
> +int i915_gem_init_ggtt(struct drm_i915_private *i915)

Less with the i915_gem; this is not about gem/ i915->gem or the GEM API :)
-Chris
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Re: [RFC 26/28] drm/i915: Store ggtt pointer in intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 16:19:02)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> This will become useful in the following patch.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 ++
>  drivers/gpu/drm/i915/i915_gem_gtt.c      | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 99e30f8cfbe0..c909aae6e4b3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -18,11 +18,13 @@
>  #include "intel_wakeref.h"
>  
>  struct drm_i915_private;
> +struct i915_ggtt;
>  struct intel_uncore;
>  
>  struct intel_gt {
>         struct drm_i915_private *i915;
>         struct intel_uncore *uncore;
> +       struct i915_ggtt *ggtt;

But not moving i915->ggtt itself?

>         struct i915_gt_timelines {
>                 struct mutex mutex; /* protects list, tainted by GPU */
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ea276ed9021a..9aa25770081c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3618,6 +3618,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
>         i915_address_space_init(vm, VM_CLASS_GGTT);
>  
>         vm->is_ggtt = true;
> +       vm->gt->ggtt = ggtt;

This looks very much to be a layer violation.
-Chris
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Re: [RFC 21/28] drm/i915/gtt: Reduce source verbosity by caching repeated dereferences

[Tvrtko Ursulin]

On 13/06/2019 15:12, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 14:35:32)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> There is a lot of code in i915_gem_gtt.c which repeatadly dereferences
>> either ggtt or ppgtt in order to get to the vm. Cache those accesses in
>> local variables for better readability.
> 
> There isn't a dereference though, it's just using the base struct. Meh.
> 
> I don't really mind, but I chose to write it the other way, specifically
> using vm to keep it short.
> 
> At the end of the day, the compiler *should* eliminate the redundant
> local, so it is merely a matter of which readers prefer. I think I still
> have a slight preference to using ppgtt throughout rather than mixing
> ppgtt and vm for the same object.

Agreed. I'll drop it. It was a silly ho-hum moment of misguided optimism 
how it will save some line wraps and then it didn't even do that.

>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_gem_gtt.c | 254 +++++++++++++++-------------
>>   1 file changed, 134 insertions(+), 120 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 516ffc4a521a..d09a4d9b71da 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -1004,10 +1004,11 @@ gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
>>   {
>>          struct i915_page_directory *pd;
>>          const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
>> +       struct i915_address_space *vm = &ppgtt->vm;
>>          gen8_pte_t *vaddr;
>>          bool ret;
>>   
>> -       GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
>> +       GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(vm));
>>          pd = pdp->page_directory[idx->pdpe];
>>          vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
>>          do {
>> @@ -1038,7 +1039,7 @@ gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
>>                                          break;
>>                                  }
>>   
>> -                               GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
>> +                               GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(vm));
> 
> I don't see any code here. :-p

I don't get it, maybe for the better. :)

Regards,

Tvrtko
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Re: [RFC 27/28] drm/i915: Compartmentalize ring buffer creation

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 16:19:03)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing on the theme of compartmentalizing the code better to make
> future split between gt and display in global i915 clearer.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> index b3bf47e8162f..0a1d952ad160 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> @@ -1226,16 +1226,16 @@ void intel_ring_unpin(struct intel_ring *ring)
>         i915_timeline_unpin(ring->timeline);
>  }
>  
> -static struct i915_vma *
> -intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
> +static struct i915_vma *create_ring_vma(struct intel_gt *gt, int size)

Here, it probably makes more sense to be passing i915_ggtt (since this
is about the i915_vma itself).

>  {
> -       struct i915_address_space *vm = &dev_priv->ggtt.vm;
> +       struct i915_address_space *vm = &gt->ggtt->vm;
> +       struct drm_i915_private *i915 = gt->i915;
>         struct drm_i915_gem_object *obj;
>         struct i915_vma *vma;
>  
> -       obj = i915_gem_object_create_stolen(dev_priv, size);
> +       obj = i915_gem_object_create_stolen(i915, size);
>         if (!obj)
> -               obj = i915_gem_object_create_internal(dev_priv, size);
> +               obj = i915_gem_object_create_internal(i915, size);
>         if (IS_ERR(obj))
>                 return ERR_CAST(obj);
>  
> @@ -1262,13 +1262,14 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
>                          struct i915_timeline *timeline,
>                          int size)
>  {
> +       struct drm_i915_private *i915 = engine->i915;
>         struct intel_ring *ring;
>         struct i915_vma *vma;
>  
>         GEM_BUG_ON(!is_power_of_2(size));
>         GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
>         GEM_BUG_ON(timeline == &engine->timeline);
> -       lockdep_assert_held(&engine->i915->drm.struct_mutex);
> +       lockdep_assert_held(&i915->drm.struct_mutex);

Heresy.
-Chris
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Re: [RFC 28/28] drm/i915: Make timelines gt centric

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 16:19:04)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Our timelines are stored inside intel_gt so we can convert the interface
> to take exactly that and not i915.

Yeah, I'm just regretting the placement. The patch is ok in principle,
just haven't fleshed out an alternative layout for timelines yet.
-Chris
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Re: [RFC 25/28] drm/i915: Compartmentalize i915_gem_init_ggtt

[Tvrtko Ursulin]

On 13/06/2019 16:38, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 16:19:01)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Continuing on the theme of better logical organization of our code, make
>> the first step towards making the ggtt code better isolated from wider
>> struct drm_i915_private.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++++----------
>>   1 file changed, 26 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 285a7a02c015..ea276ed9021a 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2873,7 +2873,13 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
>>                  drm_mm_remove_node(&ggtt->uc_fw);
>>   }
>>   
>> -int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>> +static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
>> +{
>> +       ggtt_release_guc_top(ggtt);
>> +       drm_mm_remove_node(&ggtt->error_capture);
>> +}
>> +
>> +static int init_ggtt(struct i915_ggtt *ggtt)
>>   {
>>          /* Let GEM Manage all of the aperture.
>>           *
>> @@ -2884,7 +2890,6 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>>           * aperture.  One page should be enough to keep any prefetching inside
>>           * of the aperture.
>>           */
>> -       struct i915_ggtt *ggtt = &dev_priv->ggtt;
>>          struct i915_address_space *vm = &ggtt->vm;
>>          unsigned long hole_start, hole_end;
>>          struct drm_mm_node *entry;
>> @@ -2897,7 +2902,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>>           * why.
>>           */
>>          ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
>> -                              intel_wopcm_guc_size(&dev_priv->wopcm));
>> +                              intel_wopcm_guc_size(&vm->i915->wopcm));
>>   
>>          ret = intel_vgt_balloon(ggtt);
>>          if (ret)
>> @@ -2917,8 +2922,10 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>>           * GGTT as it can comfortably hold GuC/HuC firmware images.
>>           */
>>          ret = ggtt_reserve_guc_top(ggtt);
>> -       if (ret)
>> -               goto err_reserve;
>> +       if (ret) {
>> +               cleanup_init_ggtt(ggtt);
> 
> Joonas would be turning in his grave, can you not hear the haunting call
> of onions?

Wasn't happy with how that under-developed onion looked, but I am also 
not happy without it. :/

>> +               return ret;
>> +       }
>>   
>>          /* Clear any non-preallocated blocks */
>>          drm_mm_for_each_hole(entry, &vm->mm, hole_start, hole_end) {
>> @@ -2930,19 +2937,24 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>>          /* And finally clear the reserved guard page */
>>          vm->clear_range(vm, vm->total - PAGE_SIZE, PAGE_SIZE);
>>   
>> -       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
>> -               ret = init_aliasing_ppgtt(dev_priv);
>> +       return 0;
>> +}
>> +
>> +int i915_gem_init_ggtt(struct drm_i915_private *i915)
> 
> Less with the i915_gem; this is not about gem/ i915->gem or the GEM API :)

Sometimes I try to minimize the diff, and sometimes I create a big one 
for no reason. Go figure. :)

i915_init_ggtt I suppose?

Regards,

Tvrtko
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Re: [RFC 26/28] drm/i915: Store ggtt pointer in intel_gt

[Tvrtko Ursulin]

On 13/06/2019 16:42, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 16:19:02)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> This will become useful in the following patch.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 ++
>>   drivers/gpu/drm/i915/i915_gem_gtt.c      | 1 +
>>   2 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> index 99e30f8cfbe0..c909aae6e4b3 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> @@ -18,11 +18,13 @@
>>   #include "intel_wakeref.h"
>>   
>>   struct drm_i915_private;
>> +struct i915_ggtt;
>>   struct intel_uncore;
>>   
>>   struct intel_gt {
>>          struct drm_i915_private *i915;
>>          struct intel_uncore *uncore;
>> +       struct i915_ggtt *ggtt;
> 
> But not moving i915->ggtt itself?

Moving as removing? That looks like a huge job. I can try and asses 
exactly how big but I was hoping that I don't have to do everything in 
one go.

>>          struct i915_gt_timelines {
>>                  struct mutex mutex; /* protects list, tainted by GPU */
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index ea276ed9021a..9aa25770081c 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -3618,6 +3618,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
>>          i915_address_space_init(vm, VM_CLASS_GGTT);
>>   
>>          vm->is_ggtt = true;
>> +       vm->gt->ggtt = ggtt;
> 
> This looks very much to be a layer violation.

A bit yes. I think I can work around it with some refactoring.

Regards,

Tvrtko
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Re: [RFC 27/28] drm/i915: Compartmentalize ring buffer creation

[Tvrtko Ursulin]

On 13/06/2019 16:46, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 16:19:03)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Continuing on the theme of compartmentalizing the code better to make
>> future split between gt and display in global i915 clearer.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 17 +++++++++--------
>>   1 file changed, 9 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
>> index b3bf47e8162f..0a1d952ad160 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
>> @@ -1226,16 +1226,16 @@ void intel_ring_unpin(struct intel_ring *ring)
>>          i915_timeline_unpin(ring->timeline);
>>   }
>>   
>> -static struct i915_vma *
>> -intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
>> +static struct i915_vma *create_ring_vma(struct intel_gt *gt, int size)
> 
> Here, it probably makes more sense to be passing i915_ggtt (since this
> is about the i915_vma itself).

Yep, good point.

>>   {
>> -       struct i915_address_space *vm = &dev_priv->ggtt.vm;
>> +       struct i915_address_space *vm = &gt->ggtt->vm;
>> +       struct drm_i915_private *i915 = gt->i915;
>>          struct drm_i915_gem_object *obj;
>>          struct i915_vma *vma;
>>   
>> -       obj = i915_gem_object_create_stolen(dev_priv, size);
>> +       obj = i915_gem_object_create_stolen(i915, size);
>>          if (!obj)
>> -               obj = i915_gem_object_create_internal(dev_priv, size);
>> +               obj = i915_gem_object_create_internal(i915, size);
>>          if (IS_ERR(obj))
>>                  return ERR_CAST(obj);
>>   
>> @@ -1262,13 +1262,14 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
>>                           struct i915_timeline *timeline,
>>                           int size)
>>   {
>> +       struct drm_i915_private *i915 = engine->i915;
>>          struct intel_ring *ring;
>>          struct i915_vma *vma;
>>   
>>          GEM_BUG_ON(!is_power_of_2(size));
>>          GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
>>          GEM_BUG_ON(timeline == &engine->timeline);
>> -       lockdep_assert_held(&engine->i915->drm.struct_mutex);
>> +       lockdep_assert_held(&i915->drm.struct_mutex);
> 
> Heresy.

What why?

Regards,

Tvrtko
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Re: [RFC 13/28] drm/i915: Convert i915_gem_init_hw to intel_gt

[Tvrtko Ursulin]

On 13/06/2019 14:59, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 14:35:24)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> More removal of implicit dev_priv from using old mmio accessors.
>>
>> Actually the top level function remains but is split into a part which
>> writes to i915 and part which operates on intel_gt in order to initialize
>> the hardware.
>>
>> GuC and engines are the only odd ones out remaining.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_gem.c | 66 ++++++++++++++++++++-------------
>>   1 file changed, 40 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>> index e54cd30534dc..b6f450e782e7 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
>>          }
>>   }
>>   
>> -int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>> +static int init_hw(struct intel_gt *gt)
>>   {
>> +       struct drm_i915_private *i915 = gt->i915;
>> +       struct intel_uncore *uncore = gt->uncore;
>>          int ret;
>>   
>> -       dev_priv->gt.last_init_time = ktime_get();
>> +       gt->last_init_time = ktime_get();
>>   
>>          /* Double layer security blanket, see i915_gem_init() */
>> -       intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>> +       intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>>   
>> -       if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
>> -               I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>> +       if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
>> +               intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>>   
>> -       if (IS_HASWELL(dev_priv))
>> -               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
>> -                          LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>> +       if (IS_HASWELL(i915))
>> +               intel_uncore_write(uncore,
>> +                                  MI_PREDICATE_RESULT_2,
>> +                                  IS_HSW_GT3(i915) ?
>> +                                  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>>   
>>          /* Apply the GT workarounds... */
>> -       intel_gt_apply_workarounds(&dev_priv->gt);
>> +       intel_gt_apply_workarounds(gt);
> 
> Would it be worth moving the above mmio into workarounds? Whilst you are
> doing some spring cleaning :)

To GT workarounds? Are the above two workarounds? Do they have an 
official designation?

>>          /* ...and determine whether they are sticking. */
>> -       intel_gt_verify_workarounds(&dev_priv->gt, "init");
>> +       intel_gt_verify_workarounds(gt, "init");
>>   
>> -       intel_gt_init_swizzling(&dev_priv->gt);
>> +       intel_gt_init_swizzling(gt);
>>   
>>          /*
>>           * At least 830 can leave some of the unused rings
>> @@ -1263,48 +1267,58 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>>           * will prevent c3 entry. Makes sure all unused rings
>>           * are totally idle.
>>           */
>> -       init_unused_rings(&dev_priv->gt);
>> -
>> -       BUG_ON(!dev_priv->kernel_context);
>> -       ret = i915_terminally_wedged(dev_priv);
>> -       if (ret)
>> -               goto out;
>> +       init_unused_rings(gt);
>>   
>> -       ret = i915_ppgtt_init_hw(&dev_priv->gt);
>> +       ret = i915_ppgtt_init_hw(gt);
>>          if (ret) {
>>                  DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
>>                  goto out;
>>          }
>>   
>> -       ret = intel_wopcm_init_hw(&dev_priv->wopcm);
>> +       ret = intel_wopcm_init_hw(&i915->wopcm);
>>          if (ret) {
>>                  DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
>>                  goto out;
>>          }
>>   
>>          /* We can't enable contexts until all firmware is loaded */
>> -       ret = intel_uc_init_hw(dev_priv);
>> +       ret = intel_uc_init_hw(i915);
> 
> Sorting out the uc layering is an ongoing task. I think it probably
> means our init_hw needs splitting.

I think guc and huc could be made children of intel_gt so this could be 
changed to take gt. It's a lot of code which I am not sure has much yet 
to live so I opted not to touch it.

> 
>>          if (ret) {
>>                  DRM_ERROR("Enabling uc failed (%d)\n", ret);
>>                  goto out;
>>          }
>>   
>> -       intel_mocs_init_l3cc_table(&dev_priv->gt);
>> +       intel_mocs_init_l3cc_table(gt);
>>   
>>          /* Only when the HW is re-initialised, can we replay the requests */
>> -       ret = intel_engines_resume(dev_priv);
>> +       ret = intel_engines_resume(i915);
>>          if (ret)
>>                  goto cleanup_uc;
>>   
>> -       intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>> +       intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>>   
>> -       intel_engines_set_scheduler_caps(dev_priv);
>>          return 0;
>>   
>>   cleanup_uc:
>> -       intel_uc_fini_hw(dev_priv);
>> +       intel_uc_fini_hw(i915);
>>   out:
>> -       intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>> +       intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>> +
>> +       return ret;
>> +}
>> +
>> +int i915_gem_init_hw(struct drm_i915_private *i915)
> 
> Do we also start to recognise this as i915_init_hw()? This is the driver
> talking to the intel_gt and friends, not the driver setting up the GEM
> api.

Not sure. There are some GEM bits inside like wedged status and 
scheduler caps. So it sounds passable to leave it like it is for now.

Regards,

Tvrtko
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Re: [RFC 13/28] drm/i915: Convert i915_gem_init_hw to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 17:11:43)
> 
> On 13/06/2019 14:59, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-13 14:35:24)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> More removal of implicit dev_priv from using old mmio accessors.
> >>
> >> Actually the top level function remains but is split into a part which
> >> writes to i915 and part which operates on intel_gt in order to initialize
> >> the hardware.
> >>
> >> GuC and engines are the only odd ones out remaining.
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_gem.c | 66 ++++++++++++++++++++-------------
> >>   1 file changed, 40 insertions(+), 26 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> >> index e54cd30534dc..b6f450e782e7 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem.c
> >> +++ b/drivers/gpu/drm/i915/i915_gem.c
> >> @@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
> >>          }
> >>   }
> >>   
> >> -int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> >> +static int init_hw(struct intel_gt *gt)
> >>   {
> >> +       struct drm_i915_private *i915 = gt->i915;
> >> +       struct intel_uncore *uncore = gt->uncore;
> >>          int ret;
> >>   
> >> -       dev_priv->gt.last_init_time = ktime_get();
> >> +       gt->last_init_time = ktime_get();
> >>   
> >>          /* Double layer security blanket, see i915_gem_init() */
> >> -       intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> >> +       intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> >>   
> >> -       if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
> >> -               I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> >> +       if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
> >> +               intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
> >>   
> >> -       if (IS_HASWELL(dev_priv))
> >> -               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> >> -                          LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> >> +       if (IS_HASWELL(i915))
> >> +               intel_uncore_write(uncore,
> >> +                                  MI_PREDICATE_RESULT_2,
> >> +                                  IS_HSW_GT3(i915) ?
> >> +                                  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> >>   
> >>          /* Apply the GT workarounds... */
> >> -       intel_gt_apply_workarounds(&dev_priv->gt);
> >> +       intel_gt_apply_workarounds(gt);
> > 
> > Would it be worth moving the above mmio into workarounds? Whilst you are
> > doing some spring cleaning :)
> 
> To GT workarounds? Are the above two workarounds? Do they have an 
> official designation?

To intel_gt_workarounds_apply, I'm sure you can find something ;)

> >>          /* ...and determine whether they are sticking. */
> >> -       intel_gt_verify_workarounds(&dev_priv->gt, "init");
> >> +       intel_gt_verify_workarounds(gt, "init");
> >>   
> >> -       intel_gt_init_swizzling(&dev_priv->gt);
> >> +       intel_gt_init_swizzling(gt);
> >>   
> >>          /*
> >>           * At least 830 can leave some of the unused rings
> >> @@ -1263,48 +1267,58 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> >>           * will prevent c3 entry. Makes sure all unused rings
> >>           * are totally idle.
> >>           */
> >> -       init_unused_rings(&dev_priv->gt);
> >> -
> >> -       BUG_ON(!dev_priv->kernel_context);
> >> -       ret = i915_terminally_wedged(dev_priv);
> >> -       if (ret)
> >> -               goto out;
> >> +       init_unused_rings(gt);
> >>   
> >> -       ret = i915_ppgtt_init_hw(&dev_priv->gt);
> >> +       ret = i915_ppgtt_init_hw(gt);
> >>          if (ret) {
> >>                  DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
> >>                  goto out;
> >>          }
> >>   
> >> -       ret = intel_wopcm_init_hw(&dev_priv->wopcm);
> >> +       ret = intel_wopcm_init_hw(&i915->wopcm);
> >>          if (ret) {
> >>                  DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
> >>                  goto out;
> >>          }
> >>   
> >>          /* We can't enable contexts until all firmware is loaded */
> >> -       ret = intel_uc_init_hw(dev_priv);
> >> +       ret = intel_uc_init_hw(i915);
> > 
> > Sorting out the uc layering is an ongoing task. I think it probably
> > means our init_hw needs splitting.
> 
> I think guc and huc could be made children of intel_gt so this could be 
> changed to take gt. It's a lot of code which I am not sure has much yet 
> to live so I opted not to touch it.

I can go either way. There are a few hooks into e.g. i915_ggtt, but
mostly it is a different means of driving HW (by passing through to a
second driver of our HW, grumble) via a separate communication
channel. On the whole, I think it replaces gt/.

In passing, as we move i915_ggtt/i915_ppgtt beneath gt/, we should also
consider using the intel_ prefix. The goal is that these are the HW
interface for tracking the page tables with the i915_gem_context being
the API interface. (And if the GEM vm api grows more we should
introduce a i915_gem_vm/gtt wrapper around intel_ppgtt.)

> >>          if (ret) {
> >>                  DRM_ERROR("Enabling uc failed (%d)\n", ret);
> >>                  goto out;
> >>          }
> >>   
> >> -       intel_mocs_init_l3cc_table(&dev_priv->gt);
> >> +       intel_mocs_init_l3cc_table(gt);
> >>   
> >>          /* Only when the HW is re-initialised, can we replay the requests */
> >> -       ret = intel_engines_resume(dev_priv);
> >> +       ret = intel_engines_resume(i915);
> >>          if (ret)
> >>                  goto cleanup_uc;
> >>   
> >> -       intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> >> +       intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> >>   
> >> -       intel_engines_set_scheduler_caps(dev_priv);
> >>          return 0;
> >>   
> >>   cleanup_uc:
> >> -       intel_uc_fini_hw(dev_priv);
> >> +       intel_uc_fini_hw(i915);
> >>   out:
> >> -       intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> >> +       intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> >> +
> >> +       return ret;
> >> +}
> >> +
> >> +int i915_gem_init_hw(struct drm_i915_private *i915)
> > 
> > Do we also start to recognise this as i915_init_hw()? This is the driver
> > talking to the intel_gt and friends, not the driver setting up the GEM
> > api.
> 
> Not sure. There are some GEM bits inside like wedged status and 
> scheduler caps. So it sounds passable to leave it like it is for now.

wedged is mostly our response to HW, and is controlled by
gt/intel_reset.c.  But we also use to disable the GEM uAPI. However that
is just the API layer looking at the underlying HW state and saying "no can do".
Hopefully.

i915->gpu_error is definitely an interesting beast. I actually think it
doesn't belong inside i915->gt as it is a separate HW snapshot for
different API, but not actually a part of driving the HW.

The caps.sched are an interesting wart, we are summarising the gt
features and they change depending on how we mistreat gt (wedged).
-Chris
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Re: [RFC 27/28] drm/i915: Compartmentalize ring buffer creation

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-13 16:56:37)
> 
> On 13/06/2019 16:46, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-13 16:19:03)
> >> @@ -1262,13 +1262,14 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
> >>                           struct i915_timeline *timeline,
> >>                           int size)
> >>   {
> >> +       struct drm_i915_private *i915 = engine->i915;
> >>          struct intel_ring *ring;
> >>          struct i915_vma *vma;
> >>   
> >>          GEM_BUG_ON(!is_power_of_2(size));
> >>          GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
> >>          GEM_BUG_ON(timeline == &engine->timeline);
> >> -       lockdep_assert_held(&engine->i915->drm.struct_mutex);
> >> +       lockdep_assert_held(&i915->drm.struct_mutex);
> > 
> > Heresy.
> 
> What why?

I don't have this line in my kernel \o/
-Chris
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Re: [RFC 28/28] drm/i915: Make timelines gt centric

[Chris Wilson]

Quoting Chris Wilson (2019-06-13 16:47:15)
> Quoting Tvrtko Ursulin (2019-06-13 16:19:04)
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > Our timelines are stored inside intel_gt so we can convert the interface
> > to take exactly that and not i915.
> 
> Yeah, I'm just regretting the placement. The patch is ok in principle,
> just haven't fleshed out an alternative layout for timelines yet.

As we currently use timelines for intel_ring and friends, it should be
part of gt/ and s/i915_timeline/intel_timeline/ to match.
-Chris
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Re: [RFC 06/28] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Tvrtko Ursulin]

On 13/06/2019 14:49, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 14:35:17)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Start using the newly introduced struct intel_gt to fuse together correct
>> logical init flow with uncore for more removal of implicit dev_priv in
>> mmio access.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Looks fine, I might move it again later next to the fence registers, or
> at least pull this and the detection into its own intel_gt_swizzling.c
> 
> Hmm, now that I said that, does that seem like a reasonable thing to do
> right away, see i915_gem_fence_regs.c for the swizzle probe?

Is swizzling global for the memory controller or applicable only for 
fenced regions?

Regards,

Tvrtko
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Re: [RFC 06/28] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 10:06:41)
> 
> On 13/06/2019 14:49, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-13 14:35:17)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> Start using the newly introduced struct intel_gt to fuse together correct
> >> logical init flow with uncore for more removal of implicit dev_priv in
> >> mmio access.
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > Looks fine, I might move it again later next to the fence registers, or
> > at least pull this and the detection into its own intel_gt_swizzling.c
> > 
> > Hmm, now that I said that, does that seem like a reasonable thing to do
> > right away, see i915_gem_fence_regs.c for the swizzle probe?
> 
> Is swizzling global for the memory controller or applicable only for 
> fenced regions?

As far as my understanding goes, it used to be only for fenced regions
when the gpu was the gmch, but completely migrated to the memory
controller around snb (with the ring architecture, the GPU was just
another client). This coincides with swizzling becoming defunct as part
of tiling. To further muddy the pictures, all the time the memory
controller is interleaving across the channels. I am pretty certain
around gen3 this was explicitly controlled by the GPU for its pages, but
by gen5 this is transparent to the GPU. (See the issues with L-shaped
memory configurations where the magic was not hidden from the GPU.)

So, aiui, for our world view tiling and swizzling are complicit.
-Chris
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Re: [RFC 13/28] drm/i915: Convert i915_gem_init_hw to intel_gt

[Tvrtko Ursulin]

On 13/06/2019 17:30, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 17:11:43)
>>
>> On 13/06/2019 14:59, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2019-06-13 14:35:24)
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> More removal of implicit dev_priv from using old mmio accessors.
>>>>
>>>> Actually the top level function remains but is split into a part which
>>>> writes to i915 and part which operates on intel_gt in order to initialize
>>>> the hardware.
>>>>
>>>> GuC and engines are the only odd ones out remaining.
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_gem.c | 66 ++++++++++++++++++++-------------
>>>>    1 file changed, 40 insertions(+), 26 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>>>> index e54cd30534dc..b6f450e782e7 100644
>>>> --- a/drivers/gpu/drm/i915/i915_gem.c
>>>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>>>> @@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
>>>>           }
>>>>    }
>>>>    
>>>> -int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>>>> +static int init_hw(struct intel_gt *gt)
>>>>    {
>>>> +       struct drm_i915_private *i915 = gt->i915;
>>>> +       struct intel_uncore *uncore = gt->uncore;
>>>>           int ret;
>>>>    
>>>> -       dev_priv->gt.last_init_time = ktime_get();
>>>> +       gt->last_init_time = ktime_get();
>>>>    
>>>>           /* Double layer security blanket, see i915_gem_init() */
>>>> -       intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>>>> +       intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>>>>    
>>>> -       if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
>>>> -               I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>>>> +       if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
>>>> +               intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>>>>    
>>>> -       if (IS_HASWELL(dev_priv))
>>>> -               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
>>>> -                          LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>>>> +       if (IS_HASWELL(i915))
>>>> +               intel_uncore_write(uncore,
>>>> +                                  MI_PREDICATE_RESULT_2,
>>>> +                                  IS_HSW_GT3(i915) ?
>>>> +                                  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>>>>    
>>>>           /* Apply the GT workarounds... */
>>>> -       intel_gt_apply_workarounds(&dev_priv->gt);
>>>> +       intel_gt_apply_workarounds(gt);
>>>
>>> Would it be worth moving the above mmio into workarounds? Whilst you are
>>> doing some spring cleaning :)
>>
>> To GT workarounds? Are the above two workarounds? Do they have an
>> official designation?
> 
> To intel_gt_workarounds_apply, I'm sure you can find something ;)

Having looked up the docs for HSW_IDCR and MI_PREDICATE_RESULT_2, 
neither of the programming looks like workarounds but normal device init 
to me. As such I don't see how it would be appropriate to move them into 
workarounds.

> 
>>>>           /* ...and determine whether they are sticking. */
>>>> -       intel_gt_verify_workarounds(&dev_priv->gt, "init");
>>>> +       intel_gt_verify_workarounds(gt, "init");
>>>>    
>>>> -       intel_gt_init_swizzling(&dev_priv->gt);
>>>> +       intel_gt_init_swizzling(gt);
>>>>    
>>>>           /*
>>>>            * At least 830 can leave some of the unused rings
>>>> @@ -1263,48 +1267,58 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>>>>            * will prevent c3 entry. Makes sure all unused rings
>>>>            * are totally idle.
>>>>            */
>>>> -       init_unused_rings(&dev_priv->gt);
>>>> -
>>>> -       BUG_ON(!dev_priv->kernel_context);
>>>> -       ret = i915_terminally_wedged(dev_priv);
>>>> -       if (ret)
>>>> -               goto out;
>>>> +       init_unused_rings(gt);
>>>>    
>>>> -       ret = i915_ppgtt_init_hw(&dev_priv->gt);
>>>> +       ret = i915_ppgtt_init_hw(gt);
>>>>           if (ret) {
>>>>                   DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
>>>>                   goto out;
>>>>           }
>>>>    
>>>> -       ret = intel_wopcm_init_hw(&dev_priv->wopcm);
>>>> +       ret = intel_wopcm_init_hw(&i915->wopcm);
>>>>           if (ret) {
>>>>                   DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
>>>>                   goto out;
>>>>           }
>>>>    
>>>>           /* We can't enable contexts until all firmware is loaded */
>>>> -       ret = intel_uc_init_hw(dev_priv);
>>>> +       ret = intel_uc_init_hw(i915);
>>>
>>> Sorting out the uc layering is an ongoing task. I think it probably
>>> means our init_hw needs splitting.
>>
>> I think guc and huc could be made children of intel_gt so this could be
>> changed to take gt. It's a lot of code which I am not sure has much yet
>> to live so I opted not to touch it.
> 
> I can go either way. There are a few hooks into e.g. i915_ggtt, but
> mostly it is a different means of driving HW (by passing through to a
> second driver of our HW, grumble) via a separate communication
> channel. On the whole, I think it replaces gt/.
> 
> In passing, as we move i915_ggtt/i915_ppgtt beneath gt/, we should also
> consider using the intel_ prefix. The goal is that these are the HW
> interface for tracking the page tables with the i915_gem_context being
> the API interface. (And if the GEM vm api grows more we should
> introduce a i915_gem_vm/gtt wrapper around intel_ppgtt.)
> 
>>>>           if (ret) {
>>>>                   DRM_ERROR("Enabling uc failed (%d)\n", ret);
>>>>                   goto out;
>>>>           }
>>>>    
>>>> -       intel_mocs_init_l3cc_table(&dev_priv->gt);
>>>> +       intel_mocs_init_l3cc_table(gt);
>>>>    
>>>>           /* Only when the HW is re-initialised, can we replay the requests */
>>>> -       ret = intel_engines_resume(dev_priv);
>>>> +       ret = intel_engines_resume(i915);
>>>>           if (ret)
>>>>                   goto cleanup_uc;
>>>>    
>>>> -       intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>>>> +       intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>>>>    
>>>> -       intel_engines_set_scheduler_caps(dev_priv);
>>>>           return 0;
>>>>    
>>>>    cleanup_uc:
>>>> -       intel_uc_fini_hw(dev_priv);
>>>> +       intel_uc_fini_hw(i915);
>>>>    out:
>>>> -       intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>>>> +       intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>>>> +
>>>> +       return ret;
>>>> +}
>>>> +
>>>> +int i915_gem_init_hw(struct drm_i915_private *i915)
>>>
>>> Do we also start to recognise this as i915_init_hw()? This is the driver
>>> talking to the intel_gt and friends, not the driver setting up the GEM
>>> api.
>>
>> Not sure. There are some GEM bits inside like wedged status and
>> scheduler caps. So it sounds passable to leave it like it is for now.
> 
> wedged is mostly our response to HW, and is controlled by
> gt/intel_reset.c.  But we also use to disable the GEM uAPI. However that
> is just the API layer looking at the underlying HW state and saying "no can do".
> Hopefully.
> 
> i915->gpu_error is definitely an interesting beast. I actually think it
> doesn't belong inside i915->gt as it is a separate HW snapshot for
> different API, but not actually a part of driving the HW.
> 
> The caps.sched are an interesting wart, we are summarising the gt
> features and they change depending on how we mistreat gt (wedged).

I read this as leave as is for now.

Regards,

Tvrtko
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Re: [RFC 16/28] drm/i915: Compartmentalize i915_ggtt_probe_hw

[Tvrtko Ursulin]

On 13/06/2019 15:03, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 14:35:27)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Having made start to better code compartmentalization by introducing
>> struct intel_gt, continue the theme elsewhere in code by making functions
>> take parameters take what logically makes most sense for them instead of
>> the global struct drm_i915_private.
> 
> Is that a can of worms I see? :)
> 
> While you are here, care to pull in the gmch probe so we can drop the
> frankenstein approach.

What exactly do you mean? Pull in what from where to where?

Regards,

Tvrtko


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Re: [RFC 13/28] drm/i915: Convert i915_gem_init_hw to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 10:34:06)
> 
> On 13/06/2019 17:30, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-13 17:11:43)
> >>
> >> On 13/06/2019 14:59, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2019-06-13 14:35:24)
> >>>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> >>>> index e54cd30534dc..b6f450e782e7 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_gem.c
> >>>> +++ b/drivers/gpu/drm/i915/i915_gem.c
> >>>> @@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
> >>>>           }
> >>>>    }
> >>>>    
> >>>> -int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> >>>> +static int init_hw(struct intel_gt *gt)
> >>>>    {
> >>>> +       struct drm_i915_private *i915 = gt->i915;
> >>>> +       struct intel_uncore *uncore = gt->uncore;
> >>>>           int ret;
> >>>>    
> >>>> -       dev_priv->gt.last_init_time = ktime_get();
> >>>> +       gt->last_init_time = ktime_get();
> >>>>    
> >>>>           /* Double layer security blanket, see i915_gem_init() */
> >>>> -       intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> >>>> +       intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> >>>>    
> >>>> -       if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
> >>>> -               I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> >>>> +       if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
> >>>> +               intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
> >>>>    
> >>>> -       if (IS_HASWELL(dev_priv))
> >>>> -               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> >>>> -                          LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> >>>> +       if (IS_HASWELL(i915))
> >>>> +               intel_uncore_write(uncore,
> >>>> +                                  MI_PREDICATE_RESULT_2,
> >>>> +                                  IS_HSW_GT3(i915) ?
> >>>> +                                  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> >>>>    
> >>>>           /* Apply the GT workarounds... */
> >>>> -       intel_gt_apply_workarounds(&dev_priv->gt);
> >>>> +       intel_gt_apply_workarounds(gt);
> >>>
> >>> Would it be worth moving the above mmio into workarounds? Whilst you are
> >>> doing some spring cleaning :)
> >>
> >> To GT workarounds? Are the above two workarounds? Do they have an
> >> official designation?
> > 
> > To intel_gt_workarounds_apply, I'm sure you can find something ;)
> 
> Having looked up the docs for HSW_IDCR and MI_PREDICATE_RESULT_2, 
> neither of the programming looks like workarounds but normal device init 
> to me. As such I don't see how it would be appropriate to move them into 
> workarounds.

Where they are is definitely not where they should be. I'm sure I've
complained about this since they were put there. And normal device init ==
workarounds, does it not? It is just a list of registers that need to be
programmed to default values, where those default values were decided
upon after the fact.
-Chris
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Re: [RFC 06/28] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Tvrtko Ursulin]

On 14/06/2019 10:24, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-14 10:06:41)
>>
>> On 13/06/2019 14:49, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2019-06-13 14:35:17)
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> Start using the newly introduced struct intel_gt to fuse together correct
>>>> logical init flow with uncore for more removal of implicit dev_priv in
>>>> mmio access.
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> Looks fine, I might move it again later next to the fence registers, or
>>> at least pull this and the detection into its own intel_gt_swizzling.c
>>>
>>> Hmm, now that I said that, does that seem like a reasonable thing to do
>>> right away, see i915_gem_fence_regs.c for the swizzle probe?
>>
>> Is swizzling global for the memory controller or applicable only for
>> fenced regions?
> 
> As far as my understanding goes, it used to be only for fenced regions
> when the gpu was the gmch, but completely migrated to the memory
> controller around snb (with the ring architecture, the GPU was just
> another client). This coincides with swizzling becoming defunct as part
> of tiling. To further muddy the pictures, all the time the memory
> controller is interleaving across the channels. I am pretty certain
> around gen3 this was explicitly controlled by the GPU for its pages, but
> by gen5 this is transparent to the GPU. (See the issues with L-shaped
> memory configurations where the magic was not hidden from the GPU.)
> 
> So, aiui, for our world view tiling and swizzling are complicit.

Hmm.. looking at the code complicit but still seem separate. So I could 
be more easily convinced the swizzling code does not actually belong in 
i915_gem_fence_reg.c and we should maybe have intel_gt_swizzle.h|c.

However, since it's all already in this file I can move 
intel_gt_init_swizzling there as well.

Regards,

Tvrtko
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Re: [RFC 20/28] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings

[Tvrtko Ursulin]

On 13/06/2019 15:08, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 14:35:31)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Having made start to better code compartmentalization by introducing
>> struct intel_gt, continue the theme elsewhere in code by making functions
>> take parameters take what logically makes most sense for them instead of
>> the global struct drm_i915_private.
> 
> So I am debating whether this is better off as part of i915_ggtt and not
> i915_address_space.

In terms of what object is passed in?

They mostly operate on but, but end with ggtt->invalidate(ggtt). And 
while we could move that vfunc to vm (and have it NULL for !ggtt) would 
it make sense?

Regards,

Tvrtko
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Re: [RFC 06/28] drm/i915: Convert i915_gem_init_swizzling to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 10:42:11)
> 
> On 14/06/2019 10:24, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-14 10:06:41)
> >>
> >> On 13/06/2019 14:49, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2019-06-13 14:35:17)
> >>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>>
> >>>> Start using the newly introduced struct intel_gt to fuse together correct
> >>>> logical init flow with uncore for more removal of implicit dev_priv in
> >>>> mmio access.
> >>>>
> >>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>
> >>> Looks fine, I might move it again later next to the fence registers, or
> >>> at least pull this and the detection into its own intel_gt_swizzling.c
> >>>
> >>> Hmm, now that I said that, does that seem like a reasonable thing to do
> >>> right away, see i915_gem_fence_regs.c for the swizzle probe?
> >>
> >> Is swizzling global for the memory controller or applicable only for
> >> fenced regions?
> > 
> > As far as my understanding goes, it used to be only for fenced regions
> > when the gpu was the gmch, but completely migrated to the memory
> > controller around snb (with the ring architecture, the GPU was just
> > another client). This coincides with swizzling becoming defunct as part
> > of tiling. To further muddy the pictures, all the time the memory
> > controller is interleaving across the channels. I am pretty certain
> > around gen3 this was explicitly controlled by the GPU for its pages, but
> > by gen5 this is transparent to the GPU. (See the issues with L-shaped
> > memory configurations where the magic was not hidden from the GPU.)
> > 
> > So, aiui, for our world view tiling and swizzling are complicit.
> 
> Hmm.. looking at the code complicit but still seem separate. So I could 
> be more easily convinced the swizzling code does not actually belong in 
> i915_gem_fence_reg.c and we should maybe have intel_gt_swizzle.h|c.

gem_fence_reg -> gt/ as well I think, except for the i915_gem_object
bitmaps. We can put the bitmaps into gem/i915_gem_tiling?
-Chris
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Re: [RFC 16/28] drm/i915: Compartmentalize i915_ggtt_probe_hw

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 10:35:57)
> 
> On 13/06/2019 15:03, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-13 14:35:27)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> Having made start to better code compartmentalization by introducing
> >> struct intel_gt, continue the theme elsewhere in code by making functions
> >> take parameters take what logically makes most sense for them instead of
> >> the global struct drm_i915_private.
> > 
> > Is that a can of worms I see? :)
> > 
> > While you are here, care to pull in the gmch probe so we can drop the
> > frankenstein approach.
> 
> What exactly do you mean? Pull in what from where to where?

intel_gtt.ko is the other half of i915_gem_gtt.c
-Chris
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Re: [RFC 20/28] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 10:51:59)
> 
> On 13/06/2019 15:08, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-13 14:35:31)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> Having made start to better code compartmentalization by introducing
> >> struct intel_gt, continue the theme elsewhere in code by making functions
> >> take parameters take what logically makes most sense for them instead of
> >> the global struct drm_i915_private.
> > 
> > So I am debating whether this is better off as part of i915_ggtt and not
> > i915_address_space.
> 
> In terms of what object is passed in?

No, I was thinking placement of the intel_gt backpointer. Just trying to
assess whether i915_address_space is an abstract concept... But it needs
to be tied to a struct device for dma_mapping, so I think I am talking
rubbish.
-Chris
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Re: [RFC 24/28] drm/i915: Compartmentalize i915_ggtt_cleanup_hw

[Tvrtko Ursulin]

On 13/06/2019 16:36, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-13 16:19:00)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Continuing on the theme of better logical organization of our code, make
>> the first step towards making the ggtt code better isolated from wider
>> struct drm_i915_private.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_gem_gtt.c | 54 +++++++++++++++++------------
>>   1 file changed, 31 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index d09a4d9b71da..285a7a02c015 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2832,6 +2832,8 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
>>          struct i915_ggtt *ggtt = &i915->ggtt;
>>          struct i915_ppgtt *ppgtt;
>>   
>> +       mutex_lock(&i915->drm.struct_mutex);
> 
> Do we still need to appease lockdep here? Hopefully not.

Maybe not in your tree :) but in drm-tip AFAICS:

   fini_aliasing_ppgtt
     -> i915_vm_put
       -> i915_vm_release
         -> ppgtt_destroy_vma
          -> i915_vma_destroy

>> +
>>          ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
>>          if (!ppgtt)
>>                  return;
>> @@ -2840,6 +2842,8 @@ static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
>>   
>>          ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
>>          ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
>> +
>> +       mutex_unlock(&i915->drm.struct_mutex);
>>   }
>>   
>>   static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
>> @@ -2941,21 +2945,15 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>>          return ret;
>>   }
>>   
>> -/**
>> - * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
>> - * @dev_priv: i915 device
>> - */
>> -void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
>> +static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
>>   {
>> -       struct i915_ggtt *ggtt = &dev_priv->ggtt;
>>          struct i915_address_space *vm = &ggtt->vm;
>> +       struct drm_i915_private *i915 = vm->i915;
>>          struct i915_vma *vma, *vn;
>> -       struct pagevec *pvec;
>>   
>>          vm->closed = true;
>>   
>> -       mutex_lock(&dev_priv->drm.struct_mutex);
>> -       fini_aliasing_ppgtt(dev_priv);
>> +       mutex_lock(&i915->drm.struct_mutex);
> 
> As the lock here is just for the i915_vma_unbind and not
> fini_aliasing_ppgtt.
> 
>>          list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link)
>>                  WARN_ON(i915_vma_unbind(vma));
>> @@ -2972,18 +2970,33 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
>>   
>>          vm->cleanup(vm);
>>   
>> -       pvec = &dev_priv->mm.wc_stash.pvec;
>> +       mutex_unlock(&i915->drm.struct_mutex);
>> +
>> +       arch_phys_wc_del(ggtt->mtrr);
>> +       io_mapping_fini(&ggtt->iomap);
>> +}
>> +
>> +/**
>> + * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
>> + * @dev_priv: i915 device
>> + */
>> +void i915_ggtt_cleanup_hw(struct drm_i915_private *i915)
>> +{
>> +       struct pagevec *pvec;
>> +
>> +       fini_aliasing_ppgtt(i915);
>> +
>> +       ggtt_cleanup_hw(&i915->ggtt);
>> +
>> +       mutex_lock(&i915->drm.struct_mutex);
>> +       pvec = &i915->mm.wc_stash.pvec;
>>          if (pvec->nr) {
>>                  set_pages_array_wb(pvec->pages, pvec->nr);
>>                  __pagevec_release(pvec);
>>          }
>> +       mutex_unlock(&i915->drm.struct_mutex);
> 
> The wc_stash doesn't use struct_mutex, so no lockdep appeasing required
> here.

True, removed.

Regards,

Tvrtko
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Re: [RFC 13/28] drm/i915: Convert i915_gem_init_hw to intel_gt

[Tvrtko Ursulin]

On 14/06/2019 10:41, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-14 10:34:06)
>>
>> On 13/06/2019 17:30, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2019-06-13 17:11:43)
>>>>
>>>> On 13/06/2019 14:59, Chris Wilson wrote:
>>>>> Quoting Tvrtko Ursulin (2019-06-13 14:35:24)
>>>>>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>>>>>> index e54cd30534dc..b6f450e782e7 100644
>>>>>> --- a/drivers/gpu/drm/i915/i915_gem.c
>>>>>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>>>>>> @@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
>>>>>>            }
>>>>>>     }
>>>>>>     
>>>>>> -int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>>>>>> +static int init_hw(struct intel_gt *gt)
>>>>>>     {
>>>>>> +       struct drm_i915_private *i915 = gt->i915;
>>>>>> +       struct intel_uncore *uncore = gt->uncore;
>>>>>>            int ret;
>>>>>>     
>>>>>> -       dev_priv->gt.last_init_time = ktime_get();
>>>>>> +       gt->last_init_time = ktime_get();
>>>>>>     
>>>>>>            /* Double layer security blanket, see i915_gem_init() */
>>>>>> -       intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>>>>>> +       intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>>>>>>     
>>>>>> -       if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
>>>>>> -               I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>>>>>> +       if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
>>>>>> +               intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>>>>>>     
>>>>>> -       if (IS_HASWELL(dev_priv))
>>>>>> -               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
>>>>>> -                          LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>>>>>> +       if (IS_HASWELL(i915))
>>>>>> +               intel_uncore_write(uncore,
>>>>>> +                                  MI_PREDICATE_RESULT_2,
>>>>>> +                                  IS_HSW_GT3(i915) ?
>>>>>> +                                  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>>>>>>     
>>>>>>            /* Apply the GT workarounds... */
>>>>>> -       intel_gt_apply_workarounds(&dev_priv->gt);
>>>>>> +       intel_gt_apply_workarounds(gt);
>>>>>
>>>>> Would it be worth moving the above mmio into workarounds? Whilst you are
>>>>> doing some spring cleaning :)
>>>>
>>>> To GT workarounds? Are the above two workarounds? Do they have an
>>>> official designation?
>>>
>>> To intel_gt_workarounds_apply, I'm sure you can find something ;)
>>
>> Having looked up the docs for HSW_IDCR and MI_PREDICATE_RESULT_2,
>> neither of the programming looks like workarounds but normal device init
>> to me. As such I don't see how it would be appropriate to move them into
>> workarounds.
> 
> Where they are is definitely not where they should be. I'm sure I've
> complained about this since they were put there. And normal device init ==
> workarounds, does it not? It is just a list of registers that need to be
> programmed to default values, where those default values were decided
> upon after the fact.

Well we could argue.. :) I see stuff in intel_workarounds as having 
WaXXXX names, give or take. So I prefer to leave this here for now.

Regards,

Tvrtko
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Re: [RFC 16/28] drm/i915: Compartmentalize i915_ggtt_probe_hw

[Tvrtko Ursulin]

On 14/06/2019 11:23, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-14 10:35:57)
>>
>> On 13/06/2019 15:03, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2019-06-13 14:35:27)
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> Having made start to better code compartmentalization by introducing
>>>> struct intel_gt, continue the theme elsewhere in code by making functions
>>>> take parameters take what logically makes most sense for them instead of
>>>> the global struct drm_i915_private.
>>>
>>> Is that a can of worms I see? :)
>>>
>>> While you are here, care to pull in the gmch probe so we can drop the
>>> frankenstein approach.
>>
>> What exactly do you mean? Pull in what from where to where?
> 
> intel_gtt.ko is the other half of i915_gem_gtt.c

I'll leave this out of this series, at least for now.

Otherwise I've done all the other refactors and tweaks to higher or 
lower standard. I'll send a new RFC out just so we see where we are.

Regards,

Tvrtko

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Re: [RFC 13/28] drm/i915: Convert i915_gem_init_hw to intel_gt

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-14 16:00:28)
> 
> On 14/06/2019 10:41, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-06-14 10:34:06)
> >>
> >> On 13/06/2019 17:30, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2019-06-13 17:11:43)
> >>>>
> >>>> On 13/06/2019 14:59, Chris Wilson wrote:
> >>>>> Quoting Tvrtko Ursulin (2019-06-13 14:35:24)
> >>>>>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> >>>>>> index e54cd30534dc..b6f450e782e7 100644
> >>>>>> --- a/drivers/gpu/drm/i915/i915_gem.c
> >>>>>> +++ b/drivers/gpu/drm/i915/i915_gem.c
> >>>>>> @@ -1234,28 +1234,32 @@ static void init_unused_rings(struct intel_gt *gt)
> >>>>>>            }
> >>>>>>     }
> >>>>>>     
> >>>>>> -int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> >>>>>> +static int init_hw(struct intel_gt *gt)
> >>>>>>     {
> >>>>>> +       struct drm_i915_private *i915 = gt->i915;
> >>>>>> +       struct intel_uncore *uncore = gt->uncore;
> >>>>>>            int ret;
> >>>>>>     
> >>>>>> -       dev_priv->gt.last_init_time = ktime_get();
> >>>>>> +       gt->last_init_time = ktime_get();
> >>>>>>     
> >>>>>>            /* Double layer security blanket, see i915_gem_init() */
> >>>>>> -       intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> >>>>>> +       intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> >>>>>>     
> >>>>>> -       if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
> >>>>>> -               I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
> >>>>>> +       if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
> >>>>>> +               intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
> >>>>>>     
> >>>>>> -       if (IS_HASWELL(dev_priv))
> >>>>>> -               I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> >>>>>> -                          LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> >>>>>> +       if (IS_HASWELL(i915))
> >>>>>> +               intel_uncore_write(uncore,
> >>>>>> +                                  MI_PREDICATE_RESULT_2,
> >>>>>> +                                  IS_HSW_GT3(i915) ?
> >>>>>> +                                  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> >>>>>>     
> >>>>>>            /* Apply the GT workarounds... */
> >>>>>> -       intel_gt_apply_workarounds(&dev_priv->gt);
> >>>>>> +       intel_gt_apply_workarounds(gt);
> >>>>>
> >>>>> Would it be worth moving the above mmio into workarounds? Whilst you are
> >>>>> doing some spring cleaning :)
> >>>>
> >>>> To GT workarounds? Are the above two workarounds? Do they have an
> >>>> official designation?
> >>>
> >>> To intel_gt_workarounds_apply, I'm sure you can find something ;)
> >>
> >> Having looked up the docs for HSW_IDCR and MI_PREDICATE_RESULT_2,
> >> neither of the programming looks like workarounds but normal device init
> >> to me. As such I don't see how it would be appropriate to move them into
> >> workarounds.
> > 
> > Where they are is definitely not where they should be. I'm sure I've
> > complained about this since they were put there. And normal device init ==
> > workarounds, does it not? It is just a list of registers that need to be
> > programmed to default values, where those default values were decided
> > upon after the fact.
> 
> Well we could argue.. :) I see stuff in intel_workarounds as having 
> WaXXXX names, give or take. So I prefer to leave this here for now.

Give or take the fake Wa names made up to cover normal device init :-p
-Chris
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