From: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> To: Rob Herring <robh@kernel.org> Cc: Brendan Higgins <brendanhiggins@google.com>, Wolfram Sang <wsa@the-dreams.de>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Joel Stanley <joel@jms.id.au>, Mark Rutland <mark.rutland@arm.com>, Andrew Jeffery <andrew@aj.id.au>, Tao Ren <taoren@fb.com>, Cedric Le Goater <clg@kaod.org>, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org Subject: Re: [PATCH v4 1/4] dt-bindings: i2c: aspeed: add transfer mode support Date: Tue, 9 Mar 2021 09:02:51 -0800 [thread overview] Message-ID: <f6732348-d6c8-f49b-6123-afe542bb1f8c@linux.intel.com> (raw) In-Reply-To: <20210306203011.GA1152769@robh.at.kernel.org> Hi Rob, On 3/6/2021 12:30 PM, Rob Herring wrote: > On Wed, Feb 24, 2021 at 11:17:17AM -0800, Jae Hyun Yoo wrote: >> Append bindings to support transfer mode. >> >> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> >> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> >> --- >> Changes since v3: >> - None >> >> Changes since v2: >> - Moved SRAM resources back to default dtsi and added mode selection >> property. >> >> Changes since v1: >> - Removed buffer reg settings from default device tree and added the settings >> into here to show the predefined buffer range per each bus. >> >> .../devicetree/bindings/i2c/i2c-aspeed.txt | 37 +++++++++++++++---- >> 1 file changed, 30 insertions(+), 7 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt >> index b47f6ccb196a..242343177324 100644 >> --- a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt >> +++ b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt >> @@ -17,6 +17,20 @@ Optional Properties: >> - bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not >> specified >> - multi-master : states that there is another master active on this bus. >> +- aspeed,i2c-xfer-mode : should be "byte", "buf" or "dma" to select transfer >> + mode defaults to "byte" mode when not specified. >> + >> + I2C DMA mode on AST2500 has these restrictions: >> + - If one of these controllers is enabled >> + * UHCI host controller >> + * MCTP controller >> + I2C has to use buffer mode or byte mode instead >> + since these controllers run only in DMA mode and >> + I2C is sharing the same DMA H/W with them. >> + - If one of these controllers uses DMA mode, I2C >> + can't use DMA mode >> + * SD/eMMC >> + * Port80 snoop > > How does one decide between byte or buf mode? If a given system makes just one byte r/w transactions most of the time then byte mode will be a right setting. Otherwise, buf mode is more efficient because it doesn't generate a bunch of interrupts on every byte handling. >> >> Example: >> >> @@ -26,20 +40,29 @@ i2c { >> #size-cells = <1>; >> ranges = <0 0x1e78a000 0x1000>; >> >> - i2c_ic: interrupt-controller@0 { >> - #interrupt-cells = <1>; >> - compatible = "aspeed,ast2400-i2c-ic"; >> + i2c_gr: i2c-global-regs@0 { >> + compatible = "aspeed,ast2500-i2c-gr", "syscon"; >> reg = <0x0 0x40>; >> - interrupts = <12>; >> - interrupt-controller; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x0 0x0 0x40>; >> + >> + i2c_ic: interrupt-controller@0 { >> + #interrupt-cells = <1>; >> + compatible = "aspeed,ast2500-i2c-ic"; >> + reg = <0x0 0x4>; >> + interrupts = <12>; >> + interrupt-controller; >> + }; >> }; >> >> i2c0: i2c-bus@40 { >> #address-cells = <1>; >> #size-cells = <0>; >> #interrupt-cells = <1>; >> - reg = <0x40 0x40>; >> - compatible = "aspeed,ast2400-i2c-bus"; >> + reg = <0x40 0x40>, <0x200 0x10>; >> + compatible = "aspeed,ast2500-i2c-bus"; > > The example changes are all unrelated to adding the new property. Should > be a separate patch or just dropped. The example changes are not directly related to the new property but related to the transfer mode support in this patch set. 'i2c_gr' node is added to provide a way for accessing I2C global registers to enable I2C SRAM, and 'reg' is modified to add the SRAM resource range. Thanks, Jae >> clocks = <&syscon ASPEED_CLK_APB>; >> resets = <&syscon ASPEED_RESET_I2C>; >> bus-frequency = <100000>; >> -- >> 2.17.1 >>
WARNING: multiple messages have this Message-ID (diff)
From: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> To: Rob Herring <robh@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, linux-aspeed@lists.ozlabs.org, Wolfram Sang <wsa@the-dreams.de>, Andrew Jeffery <andrew@aj.id.au>, openbmc@lists.ozlabs.org, Brendan Higgins <brendanhiggins@google.com>, linux-i2c@vger.kernel.org, Tao Ren <taoren@fb.com>, Cedric Le Goater <clg@kaod.org> Subject: Re: [PATCH v4 1/4] dt-bindings: i2c: aspeed: add transfer mode support Date: Tue, 9 Mar 2021 09:02:51 -0800 [thread overview] Message-ID: <f6732348-d6c8-f49b-6123-afe542bb1f8c@linux.intel.com> (raw) In-Reply-To: <20210306203011.GA1152769@robh.at.kernel.org> Hi Rob, On 3/6/2021 12:30 PM, Rob Herring wrote: > On Wed, Feb 24, 2021 at 11:17:17AM -0800, Jae Hyun Yoo wrote: >> Append bindings to support transfer mode. >> >> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> >> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> >> --- >> Changes since v3: >> - None >> >> Changes since v2: >> - Moved SRAM resources back to default dtsi and added mode selection >> property. >> >> Changes since v1: >> - Removed buffer reg settings from default device tree and added the settings >> into here to show the predefined buffer range per each bus. >> >> .../devicetree/bindings/i2c/i2c-aspeed.txt | 37 +++++++++++++++---- >> 1 file changed, 30 insertions(+), 7 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt >> index b47f6ccb196a..242343177324 100644 >> --- a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt >> +++ b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt >> @@ -17,6 +17,20 @@ Optional Properties: >> - bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not >> specified >> - multi-master : states that there is another master active on this bus. >> +- aspeed,i2c-xfer-mode : should be "byte", "buf" or "dma" to select transfer >> + mode defaults to "byte" mode when not specified. >> + >> + I2C DMA mode on AST2500 has these restrictions: >> + - If one of these controllers is enabled >> + * UHCI host controller >> + * MCTP controller >> + I2C has to use buffer mode or byte mode instead >> + since these controllers run only in DMA mode and >> + I2C is sharing the same DMA H/W with them. >> + - If one of these controllers uses DMA mode, I2C >> + can't use DMA mode >> + * SD/eMMC >> + * Port80 snoop > > How does one decide between byte or buf mode? If a given system makes just one byte r/w transactions most of the time then byte mode will be a right setting. Otherwise, buf mode is more efficient because it doesn't generate a bunch of interrupts on every byte handling. >> >> Example: >> >> @@ -26,20 +40,29 @@ i2c { >> #size-cells = <1>; >> ranges = <0 0x1e78a000 0x1000>; >> >> - i2c_ic: interrupt-controller@0 { >> - #interrupt-cells = <1>; >> - compatible = "aspeed,ast2400-i2c-ic"; >> + i2c_gr: i2c-global-regs@0 { >> + compatible = "aspeed,ast2500-i2c-gr", "syscon"; >> reg = <0x0 0x40>; >> - interrupts = <12>; >> - interrupt-controller; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x0 0x0 0x40>; >> + >> + i2c_ic: interrupt-controller@0 { >> + #interrupt-cells = <1>; >> + compatible = "aspeed,ast2500-i2c-ic"; >> + reg = <0x0 0x4>; >> + interrupts = <12>; >> + interrupt-controller; >> + }; >> }; >> >> i2c0: i2c-bus@40 { >> #address-cells = <1>; >> #size-cells = <0>; >> #interrupt-cells = <1>; >> - reg = <0x40 0x40>; >> - compatible = "aspeed,ast2400-i2c-bus"; >> + reg = <0x40 0x40>, <0x200 0x10>; >> + compatible = "aspeed,ast2500-i2c-bus"; > > The example changes are all unrelated to adding the new property. Should > be a separate patch or just dropped. The example changes are not directly related to the new property but related to the transfer mode support in this patch set. 'i2c_gr' node is added to provide a way for accessing I2C global registers to enable I2C SRAM, and 'reg' is modified to add the SRAM resource range. Thanks, Jae >> clocks = <&syscon ASPEED_CLK_APB>; >> resets = <&syscon ASPEED_RESET_I2C>; >> bus-frequency = <100000>; >> -- >> 2.17.1 >>
next prev parent reply other threads:[~2021-03-09 17:03 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-24 19:17 [PATCH v4 0/4] i2c: aspeed: Add buffer and DMA modes support Jae Hyun Yoo 2021-02-24 19:17 ` Jae Hyun Yoo 2021-02-24 19:17 ` [PATCH v4 1/4] dt-bindings: i2c: aspeed: add transfer mode support Jae Hyun Yoo 2021-02-24 19:17 ` Jae Hyun Yoo 2021-03-06 20:30 ` Rob Herring 2021-03-06 20:30 ` Rob Herring 2021-03-09 17:02 ` Jae Hyun Yoo [this message] 2021-03-09 17:02 ` Jae Hyun Yoo 2021-03-10 2:15 ` Rob Herring 2021-03-10 2:15 ` Rob Herring 2021-03-10 15:55 ` Jae Hyun Yoo 2021-03-10 15:55 ` Jae Hyun Yoo 2021-04-08 17:50 ` Jae Hyun Yoo 2021-04-08 17:50 ` Jae Hyun Yoo 2021-04-13 19:50 ` Brendan Higgins 2021-04-13 19:50 ` Brendan Higgins 2021-10-01 17:05 ` Jae Hyun Yoo 2021-10-01 17:05 ` Jae Hyun Yoo 2021-02-24 19:17 ` [PATCH v4 2/4] ARM: dts: aspeed: modify I2C node to support buffer mode Jae Hyun Yoo 2021-02-24 19:17 ` Jae Hyun Yoo 2021-02-24 19:17 ` [PATCH v4 3/4] i2c: aspeed: add buffer mode transfer support Jae Hyun Yoo 2021-02-24 19:17 ` Jae Hyun Yoo 2021-04-13 21:24 ` Brendan Higgins 2021-04-13 21:24 ` Brendan Higgins 2021-02-24 19:17 ` [PATCH v4 4/4] i2c: aspeed: add DMA " Jae Hyun Yoo 2021-02-24 19:17 ` Jae Hyun Yoo 2021-04-13 21:32 ` Brendan Higgins 2021-04-13 21:32 ` Brendan Higgins 2021-04-14 15:08 ` Jae Hyun Yoo 2021-04-14 15:08 ` Jae Hyun Yoo 2021-05-19 18:38 ` Jae Hyun Yoo 2021-05-19 18:38 ` Jae Hyun Yoo 2021-09-30 2:44 ` [PATCH v4 0/4] i2c: aspeed: Add buffer and DMA modes support Zev Weiss 2021-09-30 2:44 ` Zev Weiss 2021-10-01 17:06 ` Jae Hyun Yoo 2021-10-01 17:06 ` Jae Hyun Yoo
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