* [PATCH v1 1/2] target/riscv: Remove some unused macros
@ 2021-10-18 4:32 Alistair Francis
2021-10-18 4:32 ` [PATCH v1 2/2] target/riscv: Organise the CPU properties Alistair Francis
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Alistair Francis @ 2021-10-18 4:32 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 8 --------
1 file changed, 8 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..3aa2512d13 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -427,14 +427,6 @@
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
-/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
-#define VM_1_09_MBARE 0
-#define VM_1_09_MBB 1
-#define VM_1_09_MBBID 2
-#define VM_1_09_SV32 8
-#define VM_1_09_SV39 9
-#define VM_1_09_SV48 10
-
/* VM modes (satp.mode) privileged ISA 1.10 */
#define VM_1_10_MBARE 0
#define VM_1_10_SV32 1
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v1 2/2] target/riscv: Organise the CPU properties
2021-10-18 4:32 [PATCH v1 1/2] target/riscv: Remove some unused macros Alistair Francis
@ 2021-10-18 4:32 ` Alistair Francis
2021-10-18 9:12 ` Frank Chang
2021-10-19 2:28 ` Bin Meng
2021-10-18 9:11 ` Frank Chang
2021-10-18 9:30 ` Philippe Mathieu-Daudé
2 siblings, 2 replies; 14+ messages in thread
From: Alistair Francis @ 2021-10-18 4:32 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e..837bea3272 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -581,6 +581,7 @@ static void riscv_cpu_init(Object *obj)
}
static Property riscv_cpu_properties[] = {
+ /* Defaults for standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
@@ -591,22 +592,24 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
- /* This is experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+ DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+ DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+
+ DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+
+ /* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
- DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
- DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
- DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
- DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
- DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
2021-10-18 4:32 [PATCH v1 1/2] target/riscv: Remove some unused macros Alistair Francis
@ 2021-10-18 9:11 ` Frank Chang
2021-10-18 9:11 ` Frank Chang
2021-10-18 9:30 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 14+ messages in thread
From: Frank Chang @ 2021-10-18 9:11 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Alistair Francis, bmeng.cn
[-- Attachment #1: Type: text/plain, Size: 1077 bytes --]
Alistair Francis <alistair.francis@opensource.wdc.com> 於 2021年10月18日 週一
下午12:38寫道：
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu_bits.h | 8 --------
> 1 file changed, 8 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..3aa2512d13 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -427,14 +427,6 @@
> #define SATP64_ASID 0x0FFFF00000000000ULL
> #define SATP64_PPN 0x00000FFFFFFFFFFFULL
>
> -/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
> -#define VM_1_09_MBARE 0
> -#define VM_1_09_MBB 1
> -#define VM_1_09_MBBID 2
> -#define VM_1_09_SV32 8
> -#define VM_1_09_SV39 9
> -#define VM_1_09_SV48 10
> -
> /* VM modes (satp.mode) privileged ISA 1.10 */
> #define VM_1_10_MBARE 0
> #define VM_1_10_SV32 1
> --
> 2.31.1
>
>
>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
@ 2021-10-18 9:11 ` Frank Chang
0 siblings, 0 replies; 14+ messages in thread
From: Frank Chang @ 2021-10-18 9:11 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, bmeng.cn,
Palmer Dabbelt, Alistair Francis, Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 1077 bytes --]
Alistair Francis <alistair.francis@opensource.wdc.com> 於 2021年10月18日 週一
下午12:38寫道：
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu_bits.h | 8 --------
> 1 file changed, 8 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..3aa2512d13 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -427,14 +427,6 @@
> #define SATP64_ASID 0x0FFFF00000000000ULL
> #define SATP64_PPN 0x00000FFFFFFFFFFFULL
>
> -/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
> -#define VM_1_09_MBARE 0
> -#define VM_1_09_MBB 1
> -#define VM_1_09_MBBID 2
> -#define VM_1_09_SV32 8
> -#define VM_1_09_SV39 9
> -#define VM_1_09_SV48 10
> -
> /* VM modes (satp.mode) privileged ISA 1.10 */
> #define VM_1_10_MBARE 0
> #define VM_1_10_SV32 1
> --
> 2.31.1
>
>
>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 2/2] target/riscv: Organise the CPU properties
2021-10-18 4:32 ` [PATCH v1 2/2] target/riscv: Organise the CPU properties Alistair Francis
@ 2021-10-18 9:12 ` Frank Chang
2021-10-19 2:28 ` Bin Meng
1 sibling, 0 replies; 14+ messages in thread
From: Frank Chang @ 2021-10-18 9:12 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Alistair Francis, bmeng.cn
[-- Attachment #1: Type: text/plain, Size: 2704 bytes --]
Alistair Francis <alistair.francis@opensource.wdc.com> 於 2021年10月18日 週一
下午12:38寫道：
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1d69d1887e..837bea3272 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -581,6 +581,7 @@ static void riscv_cpu_init(Object *obj)
> }
>
> static Property riscv_cpu_properties[] = {
> + /* Defaults for standard extensions */
> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
> @@ -591,22 +592,24 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
> DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> - /* This is experimental so mark with 'x-' */
> + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> +
> + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> +
> + /* These are experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
> DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
> DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
> DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>
> --
> 2.31.1
>
>
>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 2/2] target/riscv: Organise the CPU properties
@ 2021-10-18 9:12 ` Frank Chang
0 siblings, 0 replies; 14+ messages in thread
From: Frank Chang @ 2021-10-18 9:12 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, bmeng.cn,
Palmer Dabbelt, Alistair Francis, Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 2704 bytes --]
Alistair Francis <alistair.francis@opensource.wdc.com> 於 2021年10月18日 週一
下午12:38寫道：
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1d69d1887e..837bea3272 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -581,6 +581,7 @@ static void riscv_cpu_init(Object *obj)
> }
>
> static Property riscv_cpu_properties[] = {
> + /* Defaults for standard extensions */
> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
> @@ -591,22 +592,24 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
> DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> - /* This is experimental so mark with 'x-' */
> + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> +
> + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> +
> + /* These are experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
> DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
> DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
> DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>
> --
> 2.31.1
>
>
>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
2021-10-18 4:32 [PATCH v1 1/2] target/riscv: Remove some unused macros Alistair Francis
@ 2021-10-18 9:30 ` Philippe Mathieu-Daudé
2021-10-18 9:11 ` Frank Chang
2021-10-18 9:30 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-18 9:30 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: alistair.francis, bmeng.cn, palmer, alistair23
On 10/18/21 06:32, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
Possible commit description:
Since commit 1a9540d1f1a ("target/riscv: Drop support for ISA
spec version 1.09.1") these definitions are unused, remove them.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu_bits.h | 8 --------
> 1 file changed, 8 deletions(-)
BTW I strongly suggest you to use git-publish for your
series / pull requests:
https://github.com/stefanha/git-publish
Regards,
Phil.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
@ 2021-10-18 9:30 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-18 9:30 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: bmeng.cn, palmer, alistair.francis, alistair23
On 10/18/21 06:32, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
Possible commit description:
Since commit 1a9540d1f1a ("target/riscv: Drop support for ISA
spec version 1.09.1") these definitions are unused, remove them.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu_bits.h | 8 --------
> 1 file changed, 8 deletions(-)
BTW I strongly suggest you to use git-publish for your
series / pull requests:
https://github.com/stefanha/git-publish
Regards,
Phil.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
2021-10-18 9:30 ` Philippe Mathieu-Daudé
@ 2021-10-19 0:36 ` Alistair Francis
-1 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2021-10-19 0:36 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng
On Mon, Oct 18, 2021 at 7:30 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 10/18/21 06:32, Alistair Francis wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
>
> Possible commit description:
>
> Since commit 1a9540d1f1a ("target/riscv: Drop support for ISA
> spec version 1.09.1") these definitions are unused, remove them.
Thanks, added.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/cpu_bits.h | 8 --------
> > 1 file changed, 8 deletions(-)
>
> BTW I strongly suggest you to use git-publish for your
> series / pull requests:
>
> https://github.com/stefanha/git-publish
Cool! I'll check it out.
Alistair
>
> Regards,
>
> Phil.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
@ 2021-10-19 0:36 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2021-10-19 0:36 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng, Palmer Dabbelt, Alistair Francis
On Mon, Oct 18, 2021 at 7:30 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 10/18/21 06:32, Alistair Francis wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
>
> Possible commit description:
>
> Since commit 1a9540d1f1a ("target/riscv: Drop support for ISA
> spec version 1.09.1") these definitions are unused, remove them.
Thanks, added.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/cpu_bits.h | 8 --------
> > 1 file changed, 8 deletions(-)
>
> BTW I strongly suggest you to use git-publish for your
> series / pull requests:
>
> https://github.com/stefanha/git-publish
Cool! I'll check it out.
Alistair
>
> Regards,
>
> Phil.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
2021-10-18 9:30 ` Philippe Mathieu-Daudé
@ 2021-10-19 2:26 ` Bin Meng
-1 siblings, 0 replies; 14+ messages in thread
From: Bin Meng @ 2021-10-19 2:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis,
Alistair Francis, Palmer Dabbelt
On Mon, Oct 18, 2021 at 5:30 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 10/18/21 06:32, Alistair Francis wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
>
> Possible commit description:
>
> Since commit 1a9540d1f1a ("target/riscv: Drop support for ISA
> spec version 1.09.1") these definitions are unused, remove them.
I believe the commit tag should come in the same line otherwise it may
break any script that extracts such from the commit message.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/cpu_bits.h | 8 --------
> > 1 file changed, 8 deletions(-)
>
> BTW I strongly suggest you to use git-publish for your
> series / pull requests:
>
> https://github.com/stefanha/git-publish
>
Regards,
Bin
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 1/2] target/riscv: Remove some unused macros
@ 2021-10-19 2:26 ` Bin Meng
0 siblings, 0 replies; 14+ messages in thread
From: Bin Meng @ 2021-10-19 2:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Palmer Dabbelt, Alistair Francis,
Alistair Francis
On Mon, Oct 18, 2021 at 5:30 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 10/18/21 06:32, Alistair Francis wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
>
> Possible commit description:
>
> Since commit 1a9540d1f1a ("target/riscv: Drop support for ISA
> spec version 1.09.1") these definitions are unused, remove them.
I believe the commit tag should come in the same line otherwise it may
break any script that extracts such from the commit message.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/cpu_bits.h | 8 --------
> > 1 file changed, 8 deletions(-)
>
> BTW I strongly suggest you to use git-publish for your
> series / pull requests:
>
> https://github.com/stefanha/git-publish
>
Regards,
Bin
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 2/2] target/riscv: Organise the CPU properties
2021-10-18 4:32 ` [PATCH v1 2/2] target/riscv: Organise the CPU properties Alistair Francis
@ 2021-10-19 2:28 ` Bin Meng
2021-10-19 2:28 ` Bin Meng
1 sibling, 0 replies; 14+ messages in thread
From: Bin Meng @ 2021-10-19 2:28 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 18, 2021 at 12:32 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
Possible commit description:
Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v1 2/2] target/riscv: Organise the CPU properties
@ 2021-10-19 2:28 ` Bin Meng
0 siblings, 0 replies; 14+ messages in thread
From: Bin Meng @ 2021-10-19 2:28 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Alistair Francis
On Mon, Oct 18, 2021 at 12:32 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
Possible commit description:
Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-10-19 2:29 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-18 4:32 [PATCH v1 1/2] target/riscv: Remove some unused macros Alistair Francis
2021-10-18 4:32 ` [PATCH v1 2/2] target/riscv: Organise the CPU properties Alistair Francis
2021-10-18 9:12 ` Frank Chang
2021-10-18 9:12 ` Frank Chang
2021-10-19 2:28 ` Bin Meng
2021-10-19 2:28 ` Bin Meng
2021-10-18 9:11 ` [PATCH v1 1/2] target/riscv: Remove some unused macros Frank Chang
2021-10-18 9:11 ` Frank Chang
2021-10-18 9:30 ` Philippe Mathieu-Daudé
2021-10-18 9:30 ` Philippe Mathieu-Daudé
2021-10-19 0:36 ` Alistair Francis
2021-10-19 0:36 ` Alistair Francis
2021-10-19 2:26 ` Bin Meng
2021-10-19 2:26 ` Bin Meng
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