From: James Morse <james.morse@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
Mark Rutland <mark.rutland@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: Re: [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs
Date: Thu, 24 Oct 2019 17:10:08 +0100 [thread overview]
Message-ID: <f7b0fa68-7e21-26fb-96f3-9c471e6cbe54@arm.com> (raw)
In-Reply-To: <20191019095521.31722-4-maz@kernel.org>
Hi Marc,
On 19/10/2019 10:55, Marc Zyngier wrote:
> When erratum 1319367 is being worked around, special care must
> be taken not to allow the page table walker to populate TLBs
> while we have the stage-2 translation enabled (which would otherwise
> result in a bizare mix of the host S1 and the guest S2).
>
> We enforce this by setting TCR_EL1.EPD{0,1} before restoring the S2
> configuration, and clear the same bits after having disabled S2.
Reviewed-by: James Morse <james.morse@arm.com>
Thanks,
James
WARNING: multiple messages have this Message-ID (diff)
From: James Morse <james.morse@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvm@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs
Date: Thu, 24 Oct 2019 17:10:08 +0100 [thread overview]
Message-ID: <f7b0fa68-7e21-26fb-96f3-9c471e6cbe54@arm.com> (raw)
In-Reply-To: <20191019095521.31722-4-maz@kernel.org>
Hi Marc,
On 19/10/2019 10:55, Marc Zyngier wrote:
> When erratum 1319367 is being worked around, special care must
> be taken not to allow the page table walker to populate TLBs
> while we have the stage-2 translation enabled (which would otherwise
> result in a bizare mix of the host S1 and the guest S2).
>
> We enforce this by setting TCR_EL1.EPD{0,1} before restoring the S2
> configuration, and clear the same bits after having disabled S2.
Reviewed-by: James Morse <james.morse@arm.com>
Thanks,
James
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: James Morse <james.morse@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
kvm@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs
Date: Thu, 24 Oct 2019 17:10:08 +0100 [thread overview]
Message-ID: <f7b0fa68-7e21-26fb-96f3-9c471e6cbe54@arm.com> (raw)
In-Reply-To: <20191019095521.31722-4-maz@kernel.org>
Hi Marc,
On 19/10/2019 10:55, Marc Zyngier wrote:
> When erratum 1319367 is being worked around, special care must
> be taken not to allow the page table walker to populate TLBs
> while we have the stage-2 translation enabled (which would otherwise
> result in a bizare mix of the host S1 and the guest S2).
>
> We enforce this by setting TCR_EL1.EPD{0,1} before restoring the S2
> configuration, and clear the same bits after having disabled S2.
Reviewed-by: James Morse <james.morse@arm.com>
Thanks,
James
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-10-24 16:10 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-19 9:55 [PATCH v2 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` [PATCH v2 1/5] arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` [PATCH v2 2/5] arm64: KVM: Reorder system register restoration and stage-2 activation Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-24 16:09 ` James Morse
2019-10-24 16:09 ` James Morse
2019-10-24 16:09 ` James Morse
2019-10-19 9:55 ` [PATCH v2 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-24 16:10 ` James Morse [this message]
2019-10-24 16:10 ` James Morse
2019-10-24 16:10 ` James Morse
2019-10-19 9:55 ` [PATCH v2 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-24 16:10 ` James Morse
2019-10-24 16:10 ` James Morse
2019-10-24 16:10 ` James Morse
2019-10-26 10:20 ` Marc Zyngier
2019-10-26 10:20 ` Marc Zyngier
2019-10-26 10:20 ` Marc Zyngier
2019-10-28 10:32 ` Catalin Marinas
2019-10-28 10:32 ` Catalin Marinas
2019-10-28 10:32 ` Catalin Marinas
2019-10-28 10:49 ` Marc Zyngier
2019-10-28 10:49 ` Marc Zyngier
2019-10-28 10:49 ` Marc Zyngier
2019-10-28 11:06 ` Catalin Marinas
2019-10-28 11:06 ` Catalin Marinas
2019-10-28 11:06 ` Catalin Marinas
2019-10-19 9:55 ` [PATCH v2 5/5] arm64: Enable and document ARM errata 1319367 and 1319537 Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
2019-10-19 9:55 ` Marc Zyngier
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