* [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv
@ 2018-10-30 12:55 Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 01/29] tools: .gitignore: add prelink-riscv Lukas Auer
` (28 more replies)
0 siblings, 29 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
This patch series includes general fixes and cleanup for RISC-V. It also
adds support for booting Linux on qemu-riscv. At the moment, only
single-core systems are supported. Support for multi-core systems will
be added with a future patch series.
To boot Linux on qemu-riscv, Linux must be compiled into BBL as a
payload. BBL must be included in a FIT image and supplied to QEMU with
the -kernel parameter. Its location in memory is embedded in the device
tree, which QEMU passes to u-boot.
To test this, QEMU and riscv-pk (BBL) must be modified. QEMU is modified
to add support for loading binary files (FIT images in this case) in
addition to ELF files. riscv-pk must be modified to adjust the link
address. A pull request for QEMU, which implements this, is available at
[1]. A modified version of riscv-pk is available at [2].
This series applies on top of u-boot-dm/next.
[1]: https://github.com/riscv/riscv-qemu/pull/175
[2]: https://github.com/lukasauer/riscv-pk/tree/riscv-u-boot
Changes in v2:
- Replace the description of RISCV_ISA_C with that of the Linux kernel,
as suggested by Bin Meng
- Change ISA string construction, as suggested by Bin Meng
- Change ISA string construction, as suggested by Bin Meng
- Remove 0-padding in the format string to avoid printing 16 digits on
RV32I systems
- Clarify reasoning behind patch in commit message
- New patch to replace patch "riscv: remove CONFIG_INIT_CRITICAL"
- Drop removal of code that stores the contents of a2; this broke the
board ax25-ae350. The code will be removed again in a future patch.
- Rebase onto u-boot-dm/next
- New patch
- Rebase onto u-boot-dm/next
- Move prototype location to match the location of the function in
ofnode.c
- Rebase onto u-boot-dm/next
- Boot Linux with the device tree provided by the prior boot stage
- New patch
Bin Meng (1):
Drop CONFIG_INIT_CRITICAL
Lukas Auer (28):
tools: .gitignore: add prelink-riscv
dts: riscv: update makefile to also clean the RISC-V dts directory
riscv: rename CPU_RISCV_32/64 to match architecture names
ARCH_RV32I/64I
riscv: select CONFIG_PHYS_64BIT on RV64I systems
riscv: add Kconfig entries for the C and A ISA extensions
riscv: set -march and -mabi based on the Kconfig configuration
riscv: add Kconfig entries for the code model
riscv: enable -fdata-sections
riscv: fix use of incorrectly sized variables
riscv: make use of the barrier functions from Linux
riscv: do not reimplement generic io functions
riscv: complete the list of exception codes
riscv: treat undefined exception codes as reserved
riscv: hang on unhandled exceptions
riscv: implement the invalidate_icache_* functions
riscv: invalidate the instruction cache before jumping to Linux
riscv: fix inconsistent use of spaces and tabs in start.S
riscv: align mtvec on a 4-byte boundary
riscv: remove unused labels in start.S
riscv: do not blindly modify the mstatus CSR
riscv: save hart ID and device tree passed by prior boot stage
riscv: qemu: use device tree passed by prior boot stage
riscv: store device tree passed by prior boot stage in environment
riscv: qemu: support booting Linux
riscv: align bootm implementation with that of other architectures
dm: core: add missing prototype for ofnode_read_u64
riscv: qemu: detect and boot the kernel passed by QEMU
riscv: qemu: clear kernel-start/-end in device tree as workaround for
BBL
arch/Kconfig | 1 +
arch/nds32/cpu/n1213/start.S | 51 ----
arch/riscv/Kconfig | 47 +++-
arch/riscv/Makefile | 27 ++
arch/riscv/config.mk | 7 +-
arch/riscv/cpu/cpu.c | 13 +
arch/riscv/cpu/start.S | 342 ++++++++++++------------
arch/riscv/include/asm/barrier.h | 67 +++++
arch/riscv/include/asm/io.h | 48 +---
arch/riscv/include/asm/posix_types.h | 6 +-
arch/riscv/include/asm/types.h | 4 +
arch/riscv/include/asm/u-boot-riscv.h | 1 +
arch/riscv/lib/bootm.c | 98 +++++--
arch/riscv/lib/cache.c | 10 +
arch/riscv/lib/interrupts.c | 31 ++-
arch/riscv/lib/setjmp.S | 2 +-
board/armltd/integrator/README | 4 +-
board/emulation/qemu-riscv/Kconfig | 2 +
board/emulation/qemu-riscv/qemu-riscv.c | 73 ++++-
configs/ax25-ae350_defconfig | 2 +-
configs/qemu-riscv32_defconfig | 4 +-
configs/qemu-riscv64_defconfig | 6 +-
dts/Makefile | 2 +-
include/common.h | 5 -
include/config_distro_bootcmd.h | 8 +-
include/configs/qemu-riscv.h | 14 +
include/dm/ofnode.h | 10 +
scripts/config_whitelist.txt | 1 -
tools/.gitignore | 1 +
29 files changed, 543 insertions(+), 344 deletions(-)
create mode 100644 arch/riscv/include/asm/barrier.h
--
2.17.2
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 01/29] tools: .gitignore: add prelink-riscv
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 02/29] dts: riscv: update makefile to also clean the RISC-V dts directory Lukas Auer
` (27 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Ignore tools/prelink-riscv.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
tools/.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/.gitignore b/tools/.gitignore
index c8cdaef90c..e5ede22842 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -24,6 +24,7 @@
/mksunxiboot
/mxsboot
/ncb
+/prelink-riscv
/proftool
/relocate-rela
/sunxi-spl-image-builder
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 02/29] dts: riscv: update makefile to also clean the RISC-V dts directory
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 01/29] tools: .gitignore: add prelink-riscv Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 03/29] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I Lukas Auer
` (26 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
dts/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dts/Makefile b/dts/Makefile
index 9a9a3d5c98..cd6e9a968e 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -61,4 +61,4 @@ dtbs: $(obj)/dt.dtb $(obj)/dt-spl.dtb
clean-files := dt.dtb.S dt-spl.dtb.S
# Let clean descend into dts directories
-subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts
+subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts ../arch/riscv/dts
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 03/29] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 01/29] tools: .gitignore: add prelink-riscv Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 02/29] dts: riscv: update makefile to also clean the RISC-V dts directory Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 04/29] riscv: select CONFIG_PHYS_64BIT on RV64I systems Lukas Auer
` (25 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/Kconfig | 16 ++++++++--------
arch/riscv/lib/setjmp.S | 2 +-
configs/ax25-ae350_defconfig | 2 +-
configs/qemu-riscv64_defconfig | 2 +-
include/config_distro_bootcmd.h | 8 ++++----
5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 168ca3de7c..7c76b4d664 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,20 +20,20 @@ source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
choice
- prompt "CPU selection"
- default CPU_RISCV_32
+ prompt "Base ISA"
+ default ARCH_RV32I
-config CPU_RISCV_32
- bool "RISC-V 32-bit"
+config ARCH_RV32I
+ bool "RV32I"
select 32BIT
help
- Choose this option to build an U-Boot for RISCV32 architecture.
+ Choose this option to target the RV32I base integer instruction set.
-config CPU_RISCV_64
- bool "RISC-V 64-bit"
+config ARCH_RV64I
+ bool "RV64I"
select 64BIT
help
- Choose this option to build an U-Boot for RISCV64 architecture.
+ Choose this option to target the RV64I base integer instruction set.
endchoice
diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S
index 8f5a6a23aa..72bc9241f6 100644
--- a/arch/riscv/lib/setjmp.S
+++ b/arch/riscv/lib/setjmp.S
@@ -6,7 +6,7 @@
#include <config.h>
#include <linux/linkage.h>
-#ifdef CONFIG_CPU_RISCV_64
+#ifdef CONFIG_ARCH_RV64I
#define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
#define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
#else
diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig
index d7c4f40e58..cad82c4213 100644
--- a/configs/ax25-ae350_defconfig
+++ b/configs/ax25-ae350_defconfig
@@ -1,7 +1,7 @@
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_AX25_AE350=y
-CONFIG_CPU_RISCV_64=y
+CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index d6c1a5d646..60b647efe8 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -1,6 +1,6 @@
CONFIG_RISCV=y
CONFIG_TARGET_QEMU_VIRT=y
-CONFIG_CPU_RISCV_64=y
+CONFIG_ARCH_RV64I=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 373fee78a9..54186efe7b 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -99,9 +99,9 @@
#define BOOTEFI_NAME "bootia32.efi"
#elif defined(CONFIG_X86_RUN_64BIT)
#define BOOTEFI_NAME "bootx64.efi"
-#elif defined(CONFIG_CPU_RISCV_32)
+#elif defined(CONFIG_ARCH_RV32I)
#define BOOTEFI_NAME "bootriscv32.efi"
-#elif defined(CONFIG_CPU_RISCV_64)
+#elif defined(CONFIG_ARCH_RV64I)
#define BOOTEFI_NAME "bootriscv64.efi"
#endif
#endif
@@ -257,10 +257,10 @@
#elif defined(__i386__)
#define BOOTENV_EFI_PXE_ARCH "0x6"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00006:UNDI:003000"
-#elif defined(CONFIG_CPU_RISCV_32) || ((defined(__riscv) && __riscv_xlen == 32))
+#elif defined(CONFIG_ARCH_RV32I) || ((defined(__riscv) && __riscv_xlen == 32))
#define BOOTENV_EFI_PXE_ARCH "0x19"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000"
-#elif defined(CONFIG_CPU_RISCV_64) || ((defined(__riscv) && __riscv_xlen == 64))
+#elif defined(CONFIG_ARCH_RV64I) || ((defined(__riscv) && __riscv_xlen == 64))
#define BOOTENV_EFI_PXE_ARCH "0x1b"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000"
#elif defined(CONFIG_SANDBOX)
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 04/29] riscv: select CONFIG_PHYS_64BIT on RV64I systems
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (2 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 03/29] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 05/29] riscv: add Kconfig entries for the C and A ISA extensions Lukas Auer
` (24 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7c76b4d664..b81e0d990a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -32,6 +32,7 @@ config ARCH_RV32I
config ARCH_RV64I
bool "RV64I"
select 64BIT
+ select PHYS_64BIT
help
Choose this option to target the RV64I base integer instruction set.
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 05/29] riscv: add Kconfig entries for the C and A ISA extensions
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (3 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 04/29] riscv: select CONFIG_PHYS_64BIT on RV64I systems Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-31 2:13 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 06/29] riscv: set -march and -mabi based on the Kconfig configuration Lukas Auer
` (23 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Add Kconfig entries for the C (compressed instructions) and A (atomic
instructions) ISA extensions. Only the C ISA extension is selectable.
This matches the configuration in Linux.
The Kconfig entries are not used yet. A follow-up patch will select the
appropriate compiler flags based on the Kconfig configuration.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- Replace the description of RISCV_ISA_C with that of the Linux kernel,
as suggested by Bin Meng
arch/riscv/Kconfig | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b81e0d990a..0de77a75d7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -38,6 +38,17 @@ config ARCH_RV64I
endchoice
+config RISCV_ISA_C
+ bool "Emit compressed instructions"
+ default y
+ help
+ Adds "C" to the ISA subsets that the toolchain is allowed to emit
+ when building U-Boot, which results in compressed instructions in the
+ U-Boot binary.
+
+config RISCV_ISA_A
+ def_bool y
+
config 32BIT
bool
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 06/29] riscv: set -march and -mabi based on the Kconfig configuration
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (4 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 05/29] riscv: add Kconfig entries for the C and A ISA extensions Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-31 2:13 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model Lukas Auer
` (22 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Use the new Kconfig entries to construct the ISA string for the -march
compiler flag. The -mabi compiler flag is selected based on the base
integer instruction set.
With this change, the C (compressed instructions) ISA extension is now
enabled for all boards with CONFIG_RISCV_ISA_C set. Buildman reports a
decrease in binary size of 71590 bytes.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- Change ISA string construction, as suggested by Bin Meng
arch/riscv/Makefile | 20 ++++++++++++++++++++
arch/riscv/config.mk | 4 ----
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 8fb6a889d8..55d7c6550e 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -3,6 +3,26 @@
# Copyright (C) 2017 Andes Technology Corporation.
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ifeq ($(CONFIG_ARCH_RV64I),y)
+ ARCH_BASE = rv64im
+ ABI = lp64
+endif
+ifeq ($(CONFIG_ARCH_RV32I),y)
+ ARCH_BASE = rv32im
+ ABI = ilp32
+endif
+ifeq ($(CONFIG_RISCV_ISA_A),y)
+ ARCH_A = a
+endif
+ifeq ($(CONFIG_RISCV_ISA_C),y)
+ ARCH_C = c
+endif
+
+ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI)
+
+PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
+CFLAGS_EFI += $(ARCH_FLAGS)
+
head-y := arch/riscv/cpu/start.o
libs-y += arch/riscv/cpu/
diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index ed9eb0c24c..9088b9ef2c 100644
--- a/arch/riscv/config.mk
+++ b/arch/riscv/config.mk
@@ -14,16 +14,12 @@
64bit-emul := elf64lriscv
ifdef CONFIG_32BIT
-PLATFORM_CPPFLAGS += -march=rv32ima -mabi=ilp32
PLATFORM_LDFLAGS += -m $(32bit-emul)
-CFLAGS_EFI += -march=rv32ima -mabi=ilp32
EFI_LDS := elf_riscv32_efi.lds
endif
ifdef CONFIG_64BIT
-PLATFORM_CPPFLAGS += -march=rv64ima -mabi=lp64
PLATFORM_LDFLAGS += -m $(64bit-emul)
-CFLAGS_EFI += -march=rv64ima -mabi=lp64
EFI_LDS := elf_riscv64_efi.lds
endif
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (5 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 06/29] riscv: set -march and -mabi based on the Kconfig configuration Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-31 2:13 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 08/29] riscv: enable -fdata-sections Lukas Auer
` (21 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
RISC-V has two code models, medium low (medlow) and medium any (medany).
Medlow limits addressable memory to a single 2 GiB range between the
absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
to any single 2 GiB address range.
By default, medlow is selected on 32-bit systems and medany on 64-bit
systems. This matches the configuration in Linux.
The -mcmodel compiler flag is selected according to the Kconfig
configuration.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- Change ISA string construction, as suggested by Bin Meng
arch/riscv/Kconfig | 19 +++++++++++++++++++
arch/riscv/Makefile | 9 ++++++++-
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0de77a75d7..371921b412 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -38,6 +38,25 @@ config ARCH_RV64I
endchoice
+choice
+ prompt "Code Model"
+ default CMODEL_MEDLOW if 32BIT
+ default CMODEL_MEDANY if 64BIT
+
+config CMODEL_MEDLOW
+ bool "medium low code model"
+ help
+ U-Boot and its statically defined symbols must lie within a single 2 GiB
+ address range and must lie between absolute addresses -2 GiB and +2 GiB.
+
+config CMODEL_MEDANY
+ bool "medium any code model"
+ help
+ U-Boot and its statically defined symbols must be within any single 2 GiB
+ address range.
+
+endchoice
+
config RISCV_ISA_C
bool "Emit compressed instructions"
default y
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 55d7c6550e..0b80eb8d86 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -17,8 +17,15 @@ endif
ifeq ($(CONFIG_RISCV_ISA_C),y)
ARCH_C = c
endif
+ifeq ($(CONFIG_CMODEL_MEDLOW),y)
+ CMODEL = medlow
+endif
+ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ CMODEL = medany
+endif
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI)
+ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+ -mcmodel=$(CMODEL)
PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
CFLAGS_EFI += $(ARCH_FLAGS)
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 08/29] riscv: enable -fdata-sections
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (6 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 09/29] riscv: fix use of incorrectly sized variables Lukas Auer
` (20 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Enable the -fdata-sections compiler option for RISC-V. Buildman reports
the binary size decrease from this as 8365.3 bytes.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/config.mk | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index 9088b9ef2c..b9487097f6 100644
--- a/arch/riscv/config.mk
+++ b/arch/riscv/config.mk
@@ -27,7 +27,8 @@ CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
-T $(srctree)/examples/standalone/riscv.lds
PLATFORM_CPPFLAGS += -ffixed-gp -fpic
-PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections
+PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \
+ -fdata-sections
LDFLAGS_u-boot += --gc-sections -static -pie
EFI_CRT0 := crt0_riscv_efi.o
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 09/29] riscv: fix use of incorrectly sized variables
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (7 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 08/29] riscv: enable -fdata-sections Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-31 2:13 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 10/29] riscv: make use of the barrier functions from Linux Lukas Auer
` (19 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
several places. Fix this.
In addition, BITS_PER_LONG is set to 64 on RV64I systems.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- Remove 0-padding in the format string to avoid printing 16 digits on
RV32I systems
arch/riscv/include/asm/io.h | 6 +++---
arch/riscv/include/asm/posix_types.h | 6 +++---
arch/riscv/include/asm/types.h | 4 ++++
arch/riscv/lib/interrupts.c | 10 +++++-----
4 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index f4a76d8720..472814a13e 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -74,12 +74,12 @@ static inline phys_addr_t virt_to_phys(void *vaddr)
#define __arch_getb(a) (*(unsigned char *)(a))
#define __arch_getw(a) (*(unsigned short *)(a))
#define __arch_getl(a) (*(unsigned int *)(a))
-#define __arch_getq(a) (*(unsigned long *)(a))
+#define __arch_getq(a) (*(unsigned long long *)(a))
#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
-#define __arch_putq(v, a) (*(unsigned long *)(a) = (v))
+#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
@@ -152,7 +152,7 @@ static inline u32 readl(const volatile void __iomem *addr)
static inline u64 readq(const volatile void __iomem *addr)
{
- u32 val;
+ u64 val;
val = __arch_getq(addr);
__iormb();
diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h
index 7438dbeb03..0fc052082a 100644
--- a/arch/riscv/include/asm/posix_types.h
+++ b/arch/riscv/include/asm/posix_types.h
@@ -37,10 +37,10 @@ typedef unsigned short __kernel_gid_t;
#ifdef __GNUC__
typedef __SIZE_TYPE__ __kernel_size_t;
#else
-typedef unsigned int __kernel_size_t;
+typedef unsigned long __kernel_size_t;
#endif
-typedef int __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
index bd8627196d..403cf9a48f 100644
--- a/arch/riscv/include/asm/types.h
+++ b/arch/riscv/include/asm/types.h
@@ -21,7 +21,11 @@ typedef unsigned short umode_t;
*/
#ifdef __KERNEL__
+#ifdef CONFIG_ARCH_RV64I
+#define BITS_PER_LONG 64
+#else
#define BITS_PER_LONG 32
+#endif
#include <stddef.h>
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 0a0995a7af..62a16b4da9 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -12,7 +12,7 @@
#include <asm/system.h>
#include <asm/encoding.h>
-static void _exit_trap(int code, uint epc, struct pt_regs *regs);
+static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs);
int interrupt_init(void)
{
@@ -34,9 +34,9 @@ int disable_interrupts(void)
return 0;
}
-uint handle_trap(uint mcause, uint epc, struct pt_regs *regs)
+ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs)
{
- uint is_int;
+ ulong is_int;
is_int = (mcause & MCAUSE_INT);
if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
@@ -60,7 +60,7 @@ __attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
{
}
-static void _exit_trap(int code, uint epc, struct pt_regs *regs)
+static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
{
static const char * const exception_code[] = {
"Instruction address misaligned",
@@ -70,6 +70,6 @@ static void _exit_trap(int code, uint epc, struct pt_regs *regs)
"Load address misaligned"
};
- printf("exception code: %d , %s , epc %08x , ra %08lx\n",
+ printf("exception code: %ld , %s , epc %lx , ra %lx\n",
code, exception_code[code], epc, regs->ra);
}
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 10/29] riscv: make use of the barrier functions from Linux
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (8 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 09/29] riscv: fix use of incorrectly sized variables Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 11/29] riscv: do not reimplement generic io functions Lukas Auer
` (18 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Replace the barrier functions in arch/riscv/include/asm/io.h with those
defined in barrier.h, which is imported from Linux. This version is
modified to remove the include statement of asm-generic/barrier.h, which
is not available in U-Boot or required.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/include/asm/barrier.h | 67 ++++++++++++++++++++++++++++++++
arch/riscv/include/asm/io.h | 11 ++----
2 files changed, 71 insertions(+), 7 deletions(-)
create mode 100644 arch/riscv/include/asm/barrier.h
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
new file mode 100644
index 0000000000..a3f60a8458
--- /dev/null
+++ b/arch/riscv/include/asm/barrier.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Copyright (C) 2013 Regents of the University of California
+ * Copyright (C) 2017 SiFive
+ *
+ * Taken from Linux arch/riscv/include/asm/barrier.h, which is based on
+ * arch/arm/include/asm/barrier.h
+ */
+
+#ifndef _ASM_RISCV_BARRIER_H
+#define _ASM_RISCV_BARRIER_H
+
+#ifndef __ASSEMBLY__
+
+#define nop() __asm__ __volatile__ ("nop")
+
+#define RISCV_FENCE(p, s) \
+ __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
+
+/* These barriers need to enforce ordering on both devices or memory. */
+#define mb() RISCV_FENCE(iorw,iorw)
+#define rmb() RISCV_FENCE(ir,ir)
+#define wmb() RISCV_FENCE(ow,ow)
+
+/* These barriers do not need to enforce ordering on devices, just memory. */
+#define __smp_mb() RISCV_FENCE(rw,rw)
+#define __smp_rmb() RISCV_FENCE(r,r)
+#define __smp_wmb() RISCV_FENCE(w,w)
+
+#define __smp_store_release(p, v) \
+do { \
+ compiletime_assert_atomic_type(*p); \
+ RISCV_FENCE(rw,w); \
+ WRITE_ONCE(*p, v); \
+} while (0)
+
+#define __smp_load_acquire(p) \
+({ \
+ typeof(*p) ___p1 = READ_ONCE(*p); \
+ compiletime_assert_atomic_type(*p); \
+ RISCV_FENCE(r,rw); \
+ ___p1; \
+})
+
+/*
+ * This is a very specific barrier: it's currently only used in two places in
+ * the kernel, both in the scheduler. See include/linux/spinlock.h for the two
+ * orderings it guarantees, but the "critical section is RCsc" guarantee
+ * mandates a barrier on RISC-V. The sequence looks like:
+ *
+ * lr.aq lock
+ * sc lock <= LOCKED
+ * smp_mb__after_spinlock()
+ * // critical section
+ * lr lock
+ * sc.rl lock <= UNLOCKED
+ *
+ * The AQ/RL pair provides a RCpc critical section, but there's not really any
+ * way we can take advantage of that here because the ordering is only enforced
+ * on that one lock. Thus, we're just doing a full fence.
+ */
+#define smp_mb__after_spinlock() RISCV_FENCE(rw,rw)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_BARRIER_H */
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 472814a13e..d01ed5bc9f 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -10,6 +10,7 @@
#ifdef __KERNEL__
#include <linux/types.h>
+#include <asm/barrier.h>
#include <asm/byteorder.h>
static inline void sync(void)
@@ -91,13 +92,9 @@ static inline phys_addr_t virt_to_phys(void *vaddr)
#define __raw_readl(a) __arch_getl(a)
#define __raw_readq(a) __arch_getq(a)
-/*
- * TODO: The kernel offers some more advanced versions of barriers, it might
- * have some advantages to use them instead of the simple one here.
- */
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
-#define __iormb() dmb()
-#define __iowmb() dmb()
+#define dmb() mb()
+#define __iormb() rmb()
+#define __iowmb() wmb()
static inline void writeb(u8 val, volatile void __iomem *addr)
{
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 11/29] riscv: do not reimplement generic io functions
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (9 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 10/29] riscv: make use of the barrier functions from Linux Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 12/29] riscv: complete the list of exception codes Lukas Auer
` (17 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
RISC-V U-Boot reimplements the generic io functions from
asm-generic/io.h. Remove the redundant implementation and include the
generic io.h instead.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/include/asm/io.h | 31 +++----------------------------
1 file changed, 3 insertions(+), 28 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index d01ed5bc9f..acf5a96449 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -17,16 +17,6 @@ static inline void sync(void)
{
}
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE (0)
-#define MAP_WRCOMBINE (0)
-#define MAP_WRBACK (0)
-#define MAP_WRTHROUGH (0)
-
#ifdef CONFIG_ARCH_MAP_SYSMEM
static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
{
@@ -49,24 +39,6 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
}
#endif
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
- return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-}
-
-static inline phys_addr_t virt_to_phys(void *vaddr)
-{
- return (phys_addr_t)(vaddr);
-}
-
/*
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
@@ -484,4 +456,7 @@ out:
#endif /* __mem_isa */
#endif /* __KERNEL__ */
+
+#include <asm-generic/io.h>
+
#endif /* __ASM_RISCV_IO_H */
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 12/29] riscv: complete the list of exception codes
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (10 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 11/29] riscv: do not reimplement generic io functions Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 13/29] riscv: treat undefined exception codes as reserved Lukas Auer
` (16 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/lib/interrupts.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 62a16b4da9..6a12818c2b 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -67,7 +67,18 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
"Instruction access fault",
"Illegal instruction",
"Breakpoint",
- "Load address misaligned"
+ "Load address misaligned",
+ "Load access fault",
+ "Store/AMO address misaligned",
+ "Store/AMO access fault",
+ "Environment call from U-mode",
+ "Environment call from S-mode",
+ "Reserved",
+ "Environment call from M-mode",
+ "Instruction page fault",
+ "Load page fault",
+ "Reserved",
+ "Store/AMO page fault",
};
printf("exception code: %ld , %s , epc %lx , ra %lx\n",
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 13/29] riscv: treat undefined exception codes as reserved
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (11 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 12/29] riscv: complete the list of exception codes Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 14/29] riscv: hang on unhandled exceptions Lukas Auer
` (15 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Undefined exception codes currently lead to an out-of-bounds array
access. Prevent this by treating undefined exception codes as
"reserved".
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/lib/interrupts.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 6a12818c2b..d0d8de500e 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -81,6 +81,10 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
"Store/AMO page fault",
};
- printf("exception code: %ld , %s , epc %lx , ra %lx\n",
- code, exception_code[code], epc, regs->ra);
+ if (code < ARRAY_SIZE(exception_code)) {
+ printf("exception code: %ld , %s , epc %lx , ra %lx\n",
+ code, exception_code[code], epc, regs->ra);
+ } else {
+ printf("Reserved\n");
+ }
}
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 14/29] riscv: hang on unhandled exceptions
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (12 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 13/29] riscv: treat undefined exception codes as reserved Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 15/29] riscv: implement the invalidate_icache_* functions Lukas Auer
` (14 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Hang on unhandled exceptions to prevent execution in a faulty state.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/lib/interrupts.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index d0d8de500e..903a1c4cd5 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -87,4 +87,6 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
} else {
printf("Reserved\n");
}
+
+ hang();
}
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 15/29] riscv: implement the invalidate_icache_* functions
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (13 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 14/29] riscv: hang on unhandled exceptions Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 16/29] riscv: invalidate the instruction cache before jumping to Linux Lukas Auer
` (13 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Implement the functions invalidate_icache_range() and
invalidate_icache_all().
RISC-V does not have instructions for explicit cache-control. The
functions in this patch are implemented with the memory ordering
instruction for synchronizing the instruction and data streams. This may
be implemented as a cache flush or invalidate on simple processors,
others may only invalidate the relevant cache lines.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/lib/cache.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index 1d67c49c2c..d642a38a07 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -12,6 +12,16 @@ void flush_dcache_range(unsigned long start, unsigned long end)
void invalidate_icache_range(unsigned long start, unsigned long end)
{
+ /*
+ * RISC-V does not have an instruction for invalidating parts of the
+ * instruction cache. Invalidate all of it instead.
+ */
+ invalidate_icache_all();
+}
+
+void invalidate_icache_all(void)
+{
+ asm volatile ("fence.i" ::: "memory");
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 16/29] riscv: invalidate the instruction cache before jumping to Linux
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (14 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 15/29] riscv: implement the invalidate_icache_* functions Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-31 2:14 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A3ECAA@ATCPCS16.andestech.com>
2018-10-30 12:55 ` [U-Boot] [PATCH v2 17/29] riscv: fix inconsistent use of spaces and tabs in start.S Lukas Auer
` (12 subsequent siblings)
28 siblings, 2 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
RISC-V does not guarantee that stores to instruction memory are visible
to instruction fetches (i.e. incoherent instruction caches). Invalidate
the instruction cache to ensure the kernel function pointer points to
the correct memory location.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- Clarify reasoning behind patch in commit message
arch/riscv/lib/bootm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 2b5ccce933..c1cf618806 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -40,6 +40,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
return 1;
kernel = (void (*)(ulong, void *))images->ep;
+ invalidate_icache_all();
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 17/29] riscv: fix inconsistent use of spaces and tabs in start.S
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (15 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 16/29] riscv: invalidate the instruction cache before jumping to Linux Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 18/29] riscv: align mtvec on a 4-byte boundary Lukas Auer
` (11 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
start.S uses both tabs and spaces after instructions. Fix this by only
using tabs after instructions.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/cpu/start.S | 322 ++++++++++++++++++++---------------------
1 file changed, 161 insertions(+), 161 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 7cd7755190..bd5904500c 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -16,56 +16,56 @@
#include <asm/encoding.h>
#ifdef CONFIG_32BIT
-#define LREG lw
-#define SREG sw
-#define REGBYTES 4
+#define LREG lw
+#define SREG sw
+#define REGBYTES 4
#define RELOC_TYPE R_RISCV_32
#define SYM_INDEX 0x8
#define SYM_SIZE 0x10
#else
-#define LREG ld
-#define SREG sd
-#define REGBYTES 8
+#define LREG ld
+#define SREG sd
+#define REGBYTES 8
#define RELOC_TYPE R_RISCV_64
#define SYM_INDEX 0x20
#define SYM_SIZE 0x18
#endif
-.section .text
+.section .text
.globl _start
_start:
- j handle_reset
+ j handle_reset
nmi_vector:
- j nmi_vector
+ j nmi_vector
trap_vector:
- j trap_entry
+ j trap_entry
.global trap_entry
handle_reset:
- li t0, CONFIG_SYS_SDRAM_BASE
- SREG a2, 0(t0)
- la t0, trap_entry
- csrw mtvec, t0
- csrwi mstatus, 0
- csrwi mie, 0
+ li t0, CONFIG_SYS_SDRAM_BASE
+ SREG a2, 0(t0)
+ la t0, trap_entry
+ csrw mtvec, t0
+ csrwi mstatus, 0
+ csrwi mie, 0
/*
* Do CPU critical regs init only at reboot,
* not when booting from ram
*/
#ifdef CONFIG_INIT_CRITICAL
- jal cpu_init_crit /* Do CPU critical regs init */
+ jal cpu_init_crit /* Do CPU critical regs init */
#endif
/*
* Set stackpointer in internal/ex RAM to call board_init_f
*/
call_board_init_f:
- li t0, -16
- li t1, CONFIG_SYS_INIT_SP_ADDR
- and sp, t1, t0 /* force 16 byte alignment */
+ li t0, -16
+ li t1, CONFIG_SYS_INIT_SP_ADDR
+ and sp, t1, t0 /* force 16 byte alignment */
#ifdef CONFIG_DEBUG_UART
jal debug_uart_init
@@ -77,9 +77,9 @@ call_board_init_f_0:
mv sp, a0
jal board_init_f_init_reserve
- mv a0, zero /* a0 <-- boot_flags = 0 */
- la t5, board_init_f
- jr t5 /* jump to board_init_f() */
+ mv a0, zero /* a0 <-- boot_flags = 0 */
+ la t5, board_init_f
+ jr t5 /* jump to board_init_f() */
/*
* void relocate_code (addr_sp, gd, addr_moni)
@@ -90,200 +90,200 @@ call_board_init_f_0:
*/
.globl relocate_code
relocate_code:
- mv s2, a0 /* save addr_sp */
- mv s3, a1 /* save addr of gd */
- mv s4, a2 /* save addr of destination */
+ mv s2, a0 /* save addr_sp */
+ mv s3, a1 /* save addr of gd */
+ mv s4, a2 /* save addr of destination */
/*
*Set up the stack
*/
stack_setup:
- mv sp, s2
- la t0, _start
- sub t6, s4, t0 /* t6 <- relocation offset */
- beq t0, s4, clear_bss /* skip relocation */
+ mv sp, s2
+ la t0, _start
+ sub t6, s4, t0 /* t6 <- relocation offset */
+ beq t0, s4, clear_bss /* skip relocation */
- mv t1, s4 /* t1 <- scratch for copy_loop */
- la t3, __bss_start
- sub t3, t3, t0 /* t3 <- __bss_start_ofs */
- add t2, t0, t3 /* t2 <- source end address */
+ mv t1, s4 /* t1 <- scratch for copy_loop */
+ la t3, __bss_start
+ sub t3, t3, t0 /* t3 <- __bss_start_ofs */
+ add t2, t0, t3 /* t2 <- source end address */
copy_loop:
- LREG t5, 0(t0)
- addi t0, t0, REGBYTES
- SREG t5, 0(t1)
- addi t1, t1, REGBYTES
- blt t0, t2, copy_loop
+ LREG t5, 0(t0)
+ addi t0, t0, REGBYTES
+ SREG t5, 0(t1)
+ addi t1, t1, REGBYTES
+ blt t0, t2, copy_loop
/*
* Update dynamic relocations after board_init_f
*/
fix_rela_dyn:
- la t1, __rel_dyn_start
- la t2, __rel_dyn_end
- beq t1, t2, clear_bss
- add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
- add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
+ la t1, __rel_dyn_start
+ la t2, __rel_dyn_end
+ beq t1, t2, clear_bss
+ add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
+ add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
/*
* skip first reserved entry: address, type, addend
*/
- bne t1, t2, 7f
+ bne t1, t2, 7f
6:
- LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
- li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
- bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
- LREG t3, -(REGBYTES*3)(t1)
- LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
- add t5, t5, t6 /* t5 <-- location to fix up in RAM */
- add t3, t3, t6 /* t3 <-- location to fix up in RAM */
- SREG t5, 0(t3)
+ LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
+ li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
+ bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
+ LREG t3, -(REGBYTES*3)(t1)
+ LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
+ add t5, t5, t6 /* t5 <-- location to fix up in RAM */
+ add t3, t3, t6 /* t3 <-- location to fix up in RAM */
+ SREG t5, 0(t3)
7:
- addi t1, t1, (REGBYTES*3)
- ble t1, t2, 6b
+ addi t1, t1, (REGBYTES*3)
+ ble t1, t2, 6b
8:
- la t4, __dyn_sym_start
- add t4, t4, t6
+ la t4, __dyn_sym_start
+ add t4, t4, t6
9:
- LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
- srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
- andi t5, t5, 0xFF /* t5 <--- relocation type */
- li t3, RELOC_TYPE
- bne t5, t3, 10f /* skip non-addned entries */
+ LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
+ srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
+ andi t5, t5, 0xFF /* t5 <--- relocation type */
+ li t3, RELOC_TYPE
+ bne t5, t3, 10f /* skip non-addned entries */
- LREG t3, -(REGBYTES*3)(t1)
- li t5, SYM_SIZE
- mul t0, t0, t5
- add s1, t4, t0
- LREG t5, REGBYTES(s1)
- add t5, t5, t6 /* t5 <-- location to fix up in RAM */
- add t3, t3, t6 /* t3 <-- location to fix up in RAM */
- SREG t5, 0(t3)
+ LREG t3, -(REGBYTES*3)(t1)
+ li t5, SYM_SIZE
+ mul t0, t0, t5
+ add s1, t4, t0
+ LREG t5, REGBYTES(s1)
+ add t5, t5, t6 /* t5 <-- location to fix up in RAM */
+ add t3, t3, t6 /* t3 <-- location to fix up in RAM */
+ SREG t5, 0(t3)
10:
- addi t1, t1, (REGBYTES*3)
- ble t1, t2, 9b
+ addi t1, t1, (REGBYTES*3)
+ ble t1, t2, 9b
/*
* trap update
*/
- la t0, trap_entry
- add t0, t0, t6
- csrw mtvec, t0
+ la t0, trap_entry
+ add t0, t0, t6
+ csrw mtvec, t0
clear_bss:
- la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
- add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
- la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
- add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
- li t2, 0x00000000 /* clear */
- beq t0, t1, call_board_init_r
+ la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
+ add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
+ la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
+ add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
+ li t2, 0x00000000 /* clear */
+ beq t0, t1, call_board_init_r
clbss_l:
- SREG t2, 0(t0) /* clear loop... */
- addi t0, t0, REGBYTES
- bne t0, t1, clbss_l
+ SREG t2, 0(t0) /* clear loop... */
+ addi t0, t0, REGBYTES
+ bne t0, t1, clbss_l
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
call_board_init_r:
- la t0, board_init_r
- mv t4, t0 /* offset of board_init_r() */
- add t4, t4, t6 /* real address of board_init_r() */
+ la t0, board_init_r
+ mv t4, t0 /* offset of board_init_r() */
+ add t4, t4, t6 /* real address of board_init_r() */
/*
* setup parameters for board_init_r
*/
- mv a0, s3 /* gd_t */
- mv a1, s4 /* dest_addr */
+ mv a0, s3 /* gd_t */
+ mv a1, s4 /* dest_addr */
/*
* jump to it ...
*/
- jr t4 /* jump to board_init_r() */
+ jr t4 /* jump to board_init_r() */
/*
* trap entry
*/
trap_entry:
- addi sp, sp, -32*REGBYTES
- SREG x1, 1*REGBYTES(sp)
- SREG x2, 2*REGBYTES(sp)
- SREG x3, 3*REGBYTES(sp)
- SREG x4, 4*REGBYTES(sp)
- SREG x5, 5*REGBYTES(sp)
- SREG x6, 6*REGBYTES(sp)
- SREG x7, 7*REGBYTES(sp)
- SREG x8, 8*REGBYTES(sp)
- SREG x9, 9*REGBYTES(sp)
- SREG x10, 10*REGBYTES(sp)
- SREG x11, 11*REGBYTES(sp)
- SREG x12, 12*REGBYTES(sp)
- SREG x13, 13*REGBYTES(sp)
- SREG x14, 14*REGBYTES(sp)
- SREG x15, 15*REGBYTES(sp)
- SREG x16, 16*REGBYTES(sp)
- SREG x17, 17*REGBYTES(sp)
- SREG x18, 18*REGBYTES(sp)
- SREG x19, 19*REGBYTES(sp)
- SREG x20, 20*REGBYTES(sp)
- SREG x21, 21*REGBYTES(sp)
- SREG x22, 22*REGBYTES(sp)
- SREG x23, 23*REGBYTES(sp)
- SREG x24, 24*REGBYTES(sp)
- SREG x25, 25*REGBYTES(sp)
- SREG x26, 26*REGBYTES(sp)
- SREG x27, 27*REGBYTES(sp)
- SREG x28, 28*REGBYTES(sp)
- SREG x29, 29*REGBYTES(sp)
- SREG x30, 30*REGBYTES(sp)
- SREG x31, 31*REGBYTES(sp)
- csrr a0, mcause
- csrr a1, mepc
- mv a2, sp
- jal handle_trap
- csrw mepc, a0
+ addi sp, sp, -32*REGBYTES
+ SREG x1, 1*REGBYTES(sp)
+ SREG x2, 2*REGBYTES(sp)
+ SREG x3, 3*REGBYTES(sp)
+ SREG x4, 4*REGBYTES(sp)
+ SREG x5, 5*REGBYTES(sp)
+ SREG x6, 6*REGBYTES(sp)
+ SREG x7, 7*REGBYTES(sp)
+ SREG x8, 8*REGBYTES(sp)
+ SREG x9, 9*REGBYTES(sp)
+ SREG x10, 10*REGBYTES(sp)
+ SREG x11, 11*REGBYTES(sp)
+ SREG x12, 12*REGBYTES(sp)
+ SREG x13, 13*REGBYTES(sp)
+ SREG x14, 14*REGBYTES(sp)
+ SREG x15, 15*REGBYTES(sp)
+ SREG x16, 16*REGBYTES(sp)
+ SREG x17, 17*REGBYTES(sp)
+ SREG x18, 18*REGBYTES(sp)
+ SREG x19, 19*REGBYTES(sp)
+ SREG x20, 20*REGBYTES(sp)
+ SREG x21, 21*REGBYTES(sp)
+ SREG x22, 22*REGBYTES(sp)
+ SREG x23, 23*REGBYTES(sp)
+ SREG x24, 24*REGBYTES(sp)
+ SREG x25, 25*REGBYTES(sp)
+ SREG x26, 26*REGBYTES(sp)
+ SREG x27, 27*REGBYTES(sp)
+ SREG x28, 28*REGBYTES(sp)
+ SREG x29, 29*REGBYTES(sp)
+ SREG x30, 30*REGBYTES(sp)
+ SREG x31, 31*REGBYTES(sp)
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ jal handle_trap
+ csrw mepc, a0
/*
* Remain in M-mode after mret
*/
- li t0, MSTATUS_MPP
- csrs mstatus, t0
- LREG x1, 1*REGBYTES(sp)
- LREG x2, 2*REGBYTES(sp)
- LREG x3, 3*REGBYTES(sp)
- LREG x4, 4*REGBYTES(sp)
- LREG x5, 5*REGBYTES(sp)
- LREG x6, 6*REGBYTES(sp)
- LREG x7, 7*REGBYTES(sp)
- LREG x8, 8*REGBYTES(sp)
- LREG x9, 9*REGBYTES(sp)
- LREG x10, 10*REGBYTES(sp)
- LREG x11, 11*REGBYTES(sp)
- LREG x12, 12*REGBYTES(sp)
- LREG x13, 13*REGBYTES(sp)
- LREG x14, 14*REGBYTES(sp)
- LREG x15, 15*REGBYTES(sp)
- LREG x16, 16*REGBYTES(sp)
- LREG x17, 17*REGBYTES(sp)
- LREG x18, 18*REGBYTES(sp)
- LREG x19, 19*REGBYTES(sp)
- LREG x20, 20*REGBYTES(sp)
- LREG x21, 21*REGBYTES(sp)
- LREG x22, 22*REGBYTES(sp)
- LREG x23, 23*REGBYTES(sp)
- LREG x24, 24*REGBYTES(sp)
- LREG x25, 25*REGBYTES(sp)
- LREG x26, 26*REGBYTES(sp)
- LREG x27, 27*REGBYTES(sp)
- LREG x28, 28*REGBYTES(sp)
- LREG x29, 29*REGBYTES(sp)
- LREG x30, 30*REGBYTES(sp)
- LREG x31, 31*REGBYTES(sp)
- addi sp, sp, 32*REGBYTES
+ li t0, MSTATUS_MPP
+ csrs mstatus, t0
+ LREG x1, 1*REGBYTES(sp)
+ LREG x2, 2*REGBYTES(sp)
+ LREG x3, 3*REGBYTES(sp)
+ LREG x4, 4*REGBYTES(sp)
+ LREG x5, 5*REGBYTES(sp)
+ LREG x6, 6*REGBYTES(sp)
+ LREG x7, 7*REGBYTES(sp)
+ LREG x8, 8*REGBYTES(sp)
+ LREG x9, 9*REGBYTES(sp)
+ LREG x10, 10*REGBYTES(sp)
+ LREG x11, 11*REGBYTES(sp)
+ LREG x12, 12*REGBYTES(sp)
+ LREG x13, 13*REGBYTES(sp)
+ LREG x14, 14*REGBYTES(sp)
+ LREG x15, 15*REGBYTES(sp)
+ LREG x16, 16*REGBYTES(sp)
+ LREG x17, 17*REGBYTES(sp)
+ LREG x18, 18*REGBYTES(sp)
+ LREG x19, 19*REGBYTES(sp)
+ LREG x20, 20*REGBYTES(sp)
+ LREG x21, 21*REGBYTES(sp)
+ LREG x22, 22*REGBYTES(sp)
+ LREG x23, 23*REGBYTES(sp)
+ LREG x24, 24*REGBYTES(sp)
+ LREG x25, 25*REGBYTES(sp)
+ LREG x26, 26*REGBYTES(sp)
+ LREG x27, 27*REGBYTES(sp)
+ LREG x28, 28*REGBYTES(sp)
+ LREG x29, 29*REGBYTES(sp)
+ LREG x30, 30*REGBYTES(sp)
+ LREG x31, 31*REGBYTES(sp)
+ addi sp, sp, 32*REGBYTES
mret
#ifdef CONFIG_INIT_CRITICAL
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 18/29] riscv: align mtvec on a 4-byte boundary
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (16 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 17/29] riscv: fix inconsistent use of spaces and tabs in start.S Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 19/29] Drop CONFIG_INIT_CRITICAL Lukas Auer
` (10 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
The machine trap-vector base address (mtvec) must be aligned on a 4-byte
boundary. Add the necessary align directive to trap_entry.
This patch also removes the global directive for trap_entry, which is
not required.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2: None
arch/riscv/cpu/start.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bd5904500c..88b4aaa1c0 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -42,7 +42,6 @@ nmi_vector:
trap_vector:
j trap_entry
-.global trap_entry
handle_reset:
li t0, CONFIG_SYS_SDRAM_BASE
SREG a2, 0(t0)
@@ -208,6 +207,7 @@ call_board_init_r:
/*
* trap entry
*/
+.align 2
trap_entry:
addi sp, sp, -32*REGBYTES
SREG x1, 1*REGBYTES(sp)
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 19/29] Drop CONFIG_INIT_CRITICAL
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (17 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 18/29] riscv: align mtvec on a 4-byte boundary Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 20/29] riscv: remove unused labels in start.S Lukas Auer
` (9 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
From: Bin Meng <bmeng.cn@gmail.com>
This is now deprecated and no board is using it. Drop it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- New patch to replace patch "riscv: remove CONFIG_INIT_CRITICAL"
arch/nds32/cpu/n1213/start.S | 51 ----------------------------------
arch/riscv/cpu/start.S | 13 ---------
board/armltd/integrator/README | 4 +--
include/common.h | 5 ----
scripts/config_whitelist.txt | 1 -
5 files changed, 1 insertion(+), 73 deletions(-)
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index aa9457f5e4..cf966e2132 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -200,14 +200,6 @@ update_gp:
jal turnoff_watchdog
#endif
-/*
- * Do CPU critical regs init only at reboot,
- * not when booting from ram
- */
-#ifdef CONFIG_INIT_CRITICAL
- jal cpu_init_crit ! Do CPU critical regs init
-#endif
-
/*
* Set stackpointer in internal RAM to call board_init_f
* $sp must be 8-byte alignment for ABI compliance.
@@ -318,49 +310,6 @@ call_board_init_r:
/* jump to it ... */
jr $lp /* jump to board_init_r() */
-/*
- * Initialize CPU critical registers
- *
- * 1. Setup control registers
- * 1.1 Mask all IRQs
- * 1.2 Flush cache and TLB
- * 1.3 Disable MMU and cache
- * 2. Setup memory timing
- */
-
-cpu_init_crit:
-
- move $r0, $lp /* push ra */
-
- /* Disable Interrupts by clear GIE in $PSW reg */
- setgie.d
-
- /* Flush caches and TLB */
- /* Invalidate caches */
- jal invalidate_icac
- jal invalidate_dcac
-
- /* Flush TLB */
- mfsr $p0, $MMU_CFG
- andi $p0, $p0, 0x3 ! MMPS
- li $p1, 0x2 ! TLB MMU
- bne $p0, $p1, 1f
- tlbop flushall ! Flush TLB
-
-1:
- ! Disable MMU, Dcache
- ! Whitiger is MMU disabled when reset
- ! Disable the D$
- mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
- li $p1, DIS_DCAC
- and $p0, $p0, $p1 ! Set DC_EN bit
- mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
- isb
-
- move $lp, $r0
-2:
- ret
-
/*
* Invalidate I$
*/
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 88b4aaa1c0..9804a8ac44 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -50,14 +50,6 @@ handle_reset:
csrwi mstatus, 0
csrwi mie, 0
-/*
- * Do CPU critical regs init only at reboot,
- * not when booting from ram
- */
-#ifdef CONFIG_INIT_CRITICAL
- jal cpu_init_crit /* Do CPU critical regs init */
-#endif
-
/*
* Set stackpointer in internal/ex RAM to call board_init_f
*/
@@ -285,8 +277,3 @@ trap_entry:
LREG x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
-
-#ifdef CONFIG_INIT_CRITICAL
-cpu_init_crit:
- ret
-#endif
diff --git a/board/armltd/integrator/README b/board/armltd/integrator/README
index 5a0e934924..af9dcc1f4f 100644
--- a/board/armltd/integrator/README
+++ b/board/armltd/integrator/README
@@ -36,9 +36,7 @@ In case c) it may be necessary for U-Boot to perform CM dependent initialization
Configuring U-Boot :
------------------
The makefile contains targets for Integrator platforms of both types
-fitted with all current variants of CM. If these targets are to be used with
-boot process c) above then CONFIG_INIT_CRITICAL may need to be defined to ensure
-that the CM is correctly configured.
+fitted with all current variants of CM.
There are also targets independent of CM. These may not be suitable for
boot process c) above. They have been preserved for backward compatibility with
diff --git a/include/common.h b/include/common.h
index 8b9f859c07..9b9bedc53a 100644
--- a/include/common.h
+++ b/include/common.h
@@ -558,11 +558,6 @@ int cpu_release(u32 nr, int argc, char * const argv[]);
#endif
#endif
-#ifdef CONFIG_INIT_CRITICAL
-#error CONFIG_INIT_CRITICAL is deprecated!
-#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
-#endif
-
#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1))
/*
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 2126315460..933c9c5006 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -965,7 +965,6 @@ CONFIG_IMX_VIDEO_SKIP
CONFIG_IMX_WATCHDOG
CONFIG_INETSPACE_V2
CONFIG_INITRD_TAG
-CONFIG_INIT_CRITICAL
CONFIG_INIT_IGNORE_ERROR
CONFIG_INI_ALLOW_MULTILINE
CONFIG_INI_CASE_INSENSITIVE
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 20/29] riscv: remove unused labels in start.S
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (18 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 19/29] Drop CONFIG_INIT_CRITICAL Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-31 2:14 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 21/29] riscv: do not blindly modify the mstatus CSR Lukas Auer
` (8 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
The labels nmi_vector, trap_vector and handle_reset in start.S are not
used for RISC-V. Remove them.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- Drop removal of code that stores the contents of a2; this broke the
board ax25-ae350. The code will be removed again in a future patch.
arch/riscv/cpu/start.S | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 9804a8ac44..c313477ae0 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -34,15 +34,6 @@
.section .text
.globl _start
_start:
- j handle_reset
-
-nmi_vector:
- j nmi_vector
-
-trap_vector:
- j trap_entry
-
-handle_reset:
li t0, CONFIG_SYS_SDRAM_BASE
SREG a2, 0(t0)
la t0, trap_entry
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 21/29] riscv: do not blindly modify the mstatus CSR
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (19 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 20/29] riscv: remove unused labels in start.S Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 22/29] riscv: save hart ID and device tree passed by prior boot stage Lukas Auer
` (7 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
The mstatus CSR includes WPRI (writes preserve values, reads ignore
values) fields and must therefore not be set to zero without preserving
these fields. It is not apparent why mstatus is set to zero here since
it is not required for U-Boot to run. Remove it.
This instruction and others encode zero as an immediate. RISC-V has the
zero register for this purpose. Replace the immediates with the zero
register.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/cpu/start.S | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index c313477ae0..b01ea6e224 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -38,8 +38,9 @@ _start:
SREG a2, 0(t0)
la t0, trap_entry
csrw mtvec, t0
- csrwi mstatus, 0
- csrwi mie, 0
+
+ /* mask all interrupts */
+ csrw mie, zero
/*
* Set stackpointer in internal/ex RAM to call board_init_f
@@ -160,11 +161,10 @@ clear_bss:
add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
- li t2, 0x00000000 /* clear */
beq t0, t1, call_board_init_r
clbss_l:
- SREG t2, 0(t0) /* clear loop... */
+ SREG zero, 0(t0) /* clear loop... */
addi t0, t0, REGBYTES
bne t0, t1, clbss_l
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 22/29] riscv: save hart ID and device tree passed by prior boot stage
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (20 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 21/29] riscv: do not blindly modify the mstatus CSR Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 23/29] riscv: qemu: use " Lukas Auer
` (6 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Store the hart ID and device tree passed by the prior boot stage (in a0
and a1) in registers s0 and s1. Replace one use of s1 in start.S to
avoid overwriting it.
The device tree is also stored in memory to make it available to U-Boot
with the configuration CONFIG_OF_PRIOR_STAGE.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2: None
arch/riscv/cpu/cpu.c | 6 ++++++
arch/riscv/cpu/start.S | 12 ++++++++++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index ae57fb8313..d9f820c44c 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -6,6 +6,12 @@
#include <common.h>
#include <asm/csr.h>
+/*
+ * prior_stage_fdt_address must be stored in the data section since it is used
+ * before the bss section is available.
+ */
+phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+
enum {
ISA_INVALID = 0,
ISA_32BIT,
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index b01ea6e224..331a5345e3 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -34,6 +34,10 @@
.section .text
.globl _start
_start:
+ /* save hart id and dtb pointer */
+ mv s0, a0
+ mv s1, a1
+
li t0, CONFIG_SYS_SDRAM_BASE
SREG a2, 0(t0)
la t0, trap_entry
@@ -58,6 +62,10 @@ call_board_init_f_0:
mv a0, sp
jal board_init_f_alloc_reserve
mv sp, a0
+
+ la t0, prior_stage_fdt_address
+ SREG s1, 0(t0)
+
jal board_init_f_init_reserve
mv a0, zero /* a0 <-- boot_flags = 0 */
@@ -140,8 +148,8 @@ fix_rela_dyn:
LREG t3, -(REGBYTES*3)(t1)
li t5, SYM_SIZE
mul t0, t0, t5
- add s1, t4, t0
- LREG t5, REGBYTES(s1)
+ add s5, t4, t0
+ LREG t5, REGBYTES(s5)
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 23/29] riscv: qemu: use device tree passed by prior boot stage
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (21 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 22/29] riscv: save hart ID and device tree passed by prior boot stage Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment Lukas Auer
` (5 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
QEMU provides a device tree, which is passed to U-Boot using register
a1. We are now able to directly select the device tree with the
configuration CONFIG_OF_PRIOR_STAGE. Replace the hard-coded address in
qemu-riscv with it.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---
Changes in v2:
- Rebase onto u-boot-dm/next
board/emulation/qemu-riscv/qemu-riscv.c | 11 -----------
configs/qemu-riscv32_defconfig | 2 +-
configs/qemu-riscv64_defconfig | 2 +-
3 files changed, 2 insertions(+), 13 deletions(-)
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index 2730a288fb..2ce093e19a 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -9,8 +9,6 @@
#include <virtio_types.h>
#include <virtio.h>
-#define MROM_FDT_ADDR 0x1020
-
int board_init(void)
{
/*
@@ -21,12 +19,3 @@ int board_init(void)
return 0;
}
-
-void *board_fdt_blob_setup(void)
-{
- /*
- * QEMU loads a generated DTB for us immediately
- * after the reset vectors in the MROM
- */
- return (void *)MROM_FDT_ADDR;
-}
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index ff1fb1f30e..72c54a3dd5 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -3,4 +3,4 @@ CONFIG_TARGET_QEMU_VIRT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index 60b647efe8..44766c38f6 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -4,4 +4,4 @@ CONFIG_ARCH_RV64I=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (22 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 23/29] riscv: qemu: use " Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 13:19 ` Alexander Graf
2018-10-30 12:55 ` [U-Boot] [PATCH v2 25/29] riscv: qemu: support booting Linux Lukas Auer
` (4 subsequent siblings)
28 siblings, 1 reply; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
The device tree passed by the prior boot stage can be used to boot
Linux. Store it as environment variable "prior_stage_dtb", so that it
can be used as part of the boot command.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- New patch
arch/Kconfig | 1 +
arch/riscv/cpu/cpu.c | 7 +++++++
arch/riscv/include/asm/u-boot-riscv.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/arch/Kconfig b/arch/Kconfig
index 9fdd2f7e66..883e4a9308 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -74,6 +74,7 @@ config RISCV
imply MTD
imply TIMER
imply CMD_DM
+ imply ARCH_MISC_INIT
config SANDBOX
bool "Sandbox"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d9f820c44c..e06a8c6bab 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -53,3 +53,10 @@ int print_cpuinfo(void)
return 0;
}
+
+int arch_misc_init(void)
+{
+ env_set_hex("prior_stage_dtb", prior_stage_fdt_address);
+
+ return 0;
+}
diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h
index 49febd5881..937b2682dc 100644
--- a/arch/riscv/include/asm/u-boot-riscv.h
+++ b/arch/riscv/include/asm/u-boot-riscv.h
@@ -13,6 +13,7 @@
/* cpu/.../cpu.c */
int cleanup_before_linux(void);
+int arch_misc_init(void);
/* board/.../... */
int board_init(void);
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 25/29] riscv: qemu: support booting Linux
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (23 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 26/29] riscv: align bootm implementation with that of other architectures Lukas Auer
` (3 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Support booting Linux (as payload of BBL) from FIT images. For this, the
default CONFIG_SYS_BOOTM_LEN is increased to 16 MB, and the environment
variables fdt_high and initrd_high are set to mark the device tree and
initrd as in-place.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2: None
configs/qemu-riscv32_defconfig | 1 +
configs/qemu-riscv64_defconfig | 1 +
include/configs/qemu-riscv.h | 6 ++++++
3 files changed, 8 insertions(+)
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index 72c54a3dd5..b55644378a 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -1,6 +1,7 @@
CONFIG_RISCV=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index 44766c38f6..a542ac4893 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index d279c233b2..ba6a18f2e6 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -15,7 +15,13 @@
#define CONFIG_SYS_MALLOC_LEN SZ_8M
+#define CONFIG_SYS_BOOTM_LEN SZ_16M
+
/* Environment options */
#define CONFIG_ENV_SIZE SZ_4K
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0"
+
#endif /* __CONFIG_H */
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 26/29] riscv: align bootm implementation with that of other architectures
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (24 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 25/29] riscv: qemu: support booting Linux Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64 Lukas Auer
` (2 subsequent siblings)
28 siblings, 0 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
The bootm implementation of RISC-V diverges from that of other
architectures. Update it to match the implementation of other
architectures. The ARM implementation is used as a reference.
This adds the following features and changes to RISC-V.
* Add support for the BOOTM_STATE_OS_FAKE_GO command
* Call the remove function on devices with the removal flag set before
booting Linux
* Force disconnect USB devices from the host before booting Linux
* Print and add bootstage information to the device tree before booting
Linux
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2:
- Rebase onto u-boot-dm/next
arch/riscv/lib/bootm.c | 99 ++++++++++++++++++++++++++++++------------
1 file changed, 71 insertions(+), 28 deletions(-)
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index c1cf618806..4e349f5614 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -8,6 +8,8 @@
#include <common.h>
#include <command.h>
+#include <dm.h>
+#include <dm/root.h>
#include <image.h>
#include <asm/byteorder.h>
#include <asm/csr.h>
@@ -26,27 +28,41 @@ int arch_fixup_fdt(void *blob)
return 0;
}
-int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+/**
+ * announce_and_cleanup() - Print message and prepare for kernel boot
+ *
+ * @fake: non-zero to do everything except actually boot
+ */
+static void announce_and_cleanup(int fake)
{
- void (*kernel)(ulong hart, void *dtb);
-
- /*
- * allow the PREP bootm subcommand, it is required for bootm to work
- */
- if (flag & BOOTM_STATE_OS_PREP)
- return 0;
+ printf("\nStarting kernel ...%s\n\n", fake ?
+ "(fake run for tracing)" : "");
+ bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+#ifdef CONFIG_BOOTSTAGE_FDT
+ bootstage_fdt_add_report();
+#endif
+#ifdef CONFIG_BOOTSTAGE_REPORT
+ bootstage_report();
+#endif
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
+#ifdef CONFIG_USB_DEVICE
+ udc_disconnect();
+#endif
- kernel = (void (*)(ulong, void *))images->ep;
- invalidate_icache_all();
+ board_quiesce_devices();
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+ /*
+ * Call remove function of all devices with a removal flag set.
+ * This may be useful for last-stage operations, like cancelling
+ * of DMA operation or releasing device internal buffers.
+ */
+ dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
- debug("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong)kernel);
+ cleanup_before_linux();
+}
+static void boot_prep_linux(bootm_headers_t *images)
+{
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
@@ -55,24 +71,51 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
hang();
}
#endif
+ } else {
+ printf("Device tree not found or missing FDT support\n");
+ hang();
}
+}
- /* we assume that the kernel is in place */
- printf("\nStarting kernel ...\n\n");
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+ void (*kernel)(ulong hart, void *dtb);
+ int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
- /*
- * Call remove function of all devices with a removal flag set.
- * This may be useful for last-stage operations, like cancelling
- * of DMA operation or releasing device internal buffers.
- */
- dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+ kernel = (void (*)(ulong, void *))images->ep;
+ invalidate_icache_all();
- cleanup_before_linux();
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
- if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
- kernel(csr_read(mhartid), images->ft_addr);
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong)kernel);
- /* does not return */
+ announce_and_cleanup(fake);
- return 1;
+ if (!fake) {
+ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ kernel(csr_read(mhartid), images->ft_addr);
+ }
+}
+
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ /* No need for those on RISC-V */
+ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+ return -1;
+
+ if (flag & BOOTM_STATE_OS_PREP) {
+ boot_prep_linux(images);
+ return 0;
+ }
+
+ if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+ boot_jump_linux(images, flag);
+ return 0;
+ }
+
+ boot_prep_linux(images);
+ boot_jump_linux(images, flag);
+ return 0;
}
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (25 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 26/29] riscv: align bootm implementation with that of other architectures Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-31 2:14 ` Bin Meng
2018-11-03 6:08 ` Simon Glass
2018-10-30 12:55 ` [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL Lukas Auer
28 siblings, 2 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- Move prototype location to match the location of the function in
ofnode.c
include/dm/ofnode.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 2fc9fa39a3..92539b8b5f 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -236,6 +236,16 @@ int ofnode_read_u32_default(ofnode ref, const char *propname, u32 def);
*/
int ofnode_read_s32_default(ofnode node, const char *propname, s32 def);
+/**
+ * ofnode_read_u64() - Read a 64-bit integer from a property
+ *
+ * @node: valid node reference to read property from
+ * @propname: name of the property to read from
+ * @outp: place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int ofnode_read_u64(ofnode node, const char *propname, u64 *outp);
+
/**
* ofnode_read_u64_default() - Read a 64-bit integer from a property
*
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (26 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64 Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-30 15:02 ` Auer, Lukas
2018-11-04 14:39 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL Lukas Auer
28 siblings, 2 replies; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
QEMU embeds the location of the kernel image in the device tree. Store
this address in the environment as variable kernel_start and use it in
CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed by the
prior boot stage to boot Linux.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- Rebase onto u-boot-dm/next
- Boot Linux with the device tree provided by the prior boot stage
board/emulation/qemu-riscv/Kconfig | 1 +
board/emulation/qemu-riscv/qemu-riscv.c | 29 +++++++++++++++++++++++++
configs/qemu-riscv32_defconfig | 1 +
configs/qemu-riscv64_defconfig | 1 +
include/configs/qemu-riscv.h | 10 ++++++++-
5 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 37a80db6a9..be5839b7db 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_EXT2
imply CMD_EXT4
imply CMD_FAT
+ imply BOARD_LATE_INIT
endif
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index 2ce093e19a..ee20983095 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -19,3 +19,32 @@ int board_init(void)
return 0;
}
+
+int board_late_init(void)
+{
+ ulong kernel_start;
+ ofnode chosen_node;
+ int ret;
+
+ chosen_node = ofnode_path("/chosen");
+ if (!ofnode_valid(chosen_node)) {
+ printf("No chosen node found\n");
+ return 0;
+ }
+
+#ifdef CONFIG_ARCH_RV64I
+ ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
+ (u64 *)&kernel_start);
+#else
+ ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
+ (u32 *)&kernel_start);
+#endif
+ if (ret) {
+ printf("Can't find kernel start address in device tree\n");
+ return 0;
+ }
+
+ env_set_hex("kernel_start", kernel_start);
+
+ return 0;
+}
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index b55644378a..13dd53a550 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -4,4 +4,5 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_HUSH_PARSER=y
CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index a542ac4893..06eb3042fa 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -5,4 +5,5 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_HUSH_PARSER=y
CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index ba6a18f2e6..7c88ba300a 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -21,7 +21,15 @@
#define CONFIG_ENV_SIZE SZ_4K
#define CONFIG_EXTRA_ENV_SETTINGS \
- "fdt_high=0xffffffffffffffff\0" \
+ "fdt_high=0x82000000\0" \
+ "bootm_size=0x10000000\0" \
"initrd_high=0xffffffffffffffff\0"
+#define CONFIG_BOOTCOMMAND \
+ "if env exists kernel_start; then " \
+ "bootm ${kernel_start} - ${prior_stage_dtb};" \
+ "else " \
+ "echo Kernel address not found in the device tree;" \
+ "fi;"
+
#endif /* __CONFIG_H */
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
` (27 preceding siblings ...)
2018-10-30 12:55 ` [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU Lukas Auer
@ 2018-10-30 12:55 ` Lukas Auer
2018-10-31 2:14 ` Bin Meng
28 siblings, 1 reply; 56+ messages in thread
From: Lukas Auer @ 2018-10-30 12:55 UTC (permalink / raw)
To: u-boot
QEMU specifies the location of Linux (supplied with the -kernel
argument) in the device tree using the riscv,kernel-start and
riscv,kernel-end properties. We currently rely on the SBI implementation
of BBL to run Linux and therefore embed Linux as payload in BBL. This
causes an issue, because BBL detects the kernel properties in the device
tree and ignores the Linux payload as a result.
Work around this issue by clearing the kernel properties in the device
tree before booting Linux.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---
Changes in v2:
- New patch
board/emulation/qemu-riscv/Kconfig | 1 +
board/emulation/qemu-riscv/qemu-riscv.c | 39 +++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index be5839b7db..33ca253432 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -30,5 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_EXT4
imply CMD_FAT
imply BOARD_LATE_INIT
+ imply OF_BOARD_SETUP
endif
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index ee20983095..a938b0b39f 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -48,3 +48,42 @@ int board_late_init(void)
return 0;
}
+
+/*
+ * QEMU specifies the location of Linux (supplied with the -kernel argument)
+ * in the device tree using the riscv,kernel-start and riscv,kernel-end
+ * properties. We currently rely on the SBI implementation of BBL to run
+ * Linux and therefore embed Linux as payload in BBL. This causes an issue,
+ * because BBL detects the kernel properties in the device tree and ignores
+ * the Linux payload as a result. To work around this issue, we clear the
+ * kernel properties before booting Linux.
+ *
+ * This workaround can be removed, once we do not require BBL for its SBI
+ * implementation anymore.
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int chosen_offset, ret;
+
+ chosen_offset = fdt_path_offset(blob, "/chosen");
+ if (chosen_offset < 0)
+ return 0;
+
+#ifdef CONFIG_ARCH_RV64I
+ ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-start", 0);
+#else
+ ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-start", 0);
+#endif
+ if (ret)
+ return ret;
+
+#ifdef CONFIG_ARCH_RV64I
+ ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-end", 0);
+#else
+ ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-end", 0);
+#endif
+ if (ret)
+ return ret;
+
+ return 0;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment
2018-10-30 12:55 ` [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment Lukas Auer
@ 2018-10-30 13:19 ` Alexander Graf
2018-10-30 13:44 ` Auer, Lukas
0 siblings, 1 reply; 56+ messages in thread
From: Alexander Graf @ 2018-10-30 13:19 UTC (permalink / raw)
To: u-boot
On 30.10.18 13:55, Lukas Auer wrote:
> The device tree passed by the prior boot stage can be used to boot
> Linux. Store it as environment variable "prior_stage_dtb", so that it
> can be used as part of the boot command.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - New patch
>
> arch/Kconfig | 1 +
> arch/riscv/cpu/cpu.c | 7 +++++++
> arch/riscv/include/asm/u-boot-riscv.h | 1 +
> 3 files changed, 9 insertions(+)
>
> diff --git a/arch/Kconfig b/arch/Kconfig
> index 9fdd2f7e66..883e4a9308 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -74,6 +74,7 @@ config RISCV
> imply MTD
> imply TIMER
> imply CMD_DM
> + imply ARCH_MISC_INIT
>
> config SANDBOX
> bool "Sandbox"
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index d9f820c44c..e06a8c6bab 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -53,3 +53,10 @@ int print_cpuinfo(void)
>
> return 0;
> }
> +
> +int arch_misc_init(void)
> +{
> + env_set_hex("prior_stage_dtb", prior_stage_fdt_address);
Please reuse one of the many other variable names we have for this
already, such as "fdtaddr".
One thing I would always recommend is that if you have a prior stage DT
passed on to U-Boot is that U-Boot makes use of that (CONFIG_OF_BOARD).
That again means that the DT is already available in $fdtcontroladdr and
there is very little use for yet another env variable.
Alex
> +
> + return 0;
> +}
> diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h
> index 49febd5881..937b2682dc 100644
> --- a/arch/riscv/include/asm/u-boot-riscv.h
> +++ b/arch/riscv/include/asm/u-boot-riscv.h
> @@ -13,6 +13,7 @@
>
> /* cpu/.../cpu.c */
> int cleanup_before_linux(void);
> +int arch_misc_init(void);
>
> /* board/.../... */
> int board_init(void);
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment
2018-10-30 13:19 ` Alexander Graf
@ 2018-10-30 13:44 ` Auer, Lukas
2018-10-30 13:53 ` Alexander Graf
0 siblings, 1 reply; 56+ messages in thread
From: Auer, Lukas @ 2018-10-30 13:44 UTC (permalink / raw)
To: u-boot
On Tue, 2018-10-30 at 14:19 +0100, Alexander Graf wrote:
>
> On 30.10.18 13:55, Lukas Auer wrote:
> > The device tree passed by the prior boot stage can be used to boot
> > Linux. Store it as environment variable "prior_stage_dtb", so that
> > it
> > can be used as part of the boot command.
> >
> > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > ---
> >
> > Changes in v2:
> > - New patch
> >
> > arch/Kconfig | 1 +
> > arch/riscv/cpu/cpu.c | 7 +++++++
> > arch/riscv/include/asm/u-boot-riscv.h | 1 +
> > 3 files changed, 9 insertions(+)
> >
> > diff --git a/arch/Kconfig b/arch/Kconfig
> > index 9fdd2f7e66..883e4a9308 100644
> > --- a/arch/Kconfig
> > +++ b/arch/Kconfig
> > @@ -74,6 +74,7 @@ config RISCV
> > imply MTD
> > imply TIMER
> > imply CMD_DM
> > + imply ARCH_MISC_INIT
> >
> > config SANDBOX
> > bool "Sandbox"
> > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > index d9f820c44c..e06a8c6bab 100644
> > --- a/arch/riscv/cpu/cpu.c
> > +++ b/arch/riscv/cpu/cpu.c
> > @@ -53,3 +53,10 @@ int print_cpuinfo(void)
> >
> > return 0;
> > }
> > +
> > +int arch_misc_init(void)
> > +{
> > + env_set_hex("prior_stage_dtb", prior_stage_fdt_address);
>
> Please reuse one of the many other variable names we have for this
> already, such as "fdtaddr".
>
I will change the variable name.
> One thing I would always recommend is that if you have a prior stage
> DT
> passed on to U-Boot is that U-Boot makes use of that
> (CONFIG_OF_BOARD).
> That again means that the DT is already available in $fdtcontroladdr
> and
> there is very little use for yet another env variable.
>
>
> Alex
>
We are actually using the device tree passed to U-Boot (using
CONFIG_OF_PRIOR_STAGE). The reason I'm adding the device tree address
to the environment is so that it can be used to boot Linux. RISC-V
Linux does not include any device trees, they are instead stored
directly on the SoC (though this might change). This is therefore
important to have and this is the best way I could think of, of
implementing it.
Thanks,
Lukas
> > +
> > + return 0;
> > +}
> > diff --git a/arch/riscv/include/asm/u-boot-riscv.h
> > b/arch/riscv/include/asm/u-boot-riscv.h
> > index 49febd5881..937b2682dc 100644
> > --- a/arch/riscv/include/asm/u-boot-riscv.h
> > +++ b/arch/riscv/include/asm/u-boot-riscv.h
> > @@ -13,6 +13,7 @@
> >
> > /* cpu/.../cpu.c */
> > int cleanup_before_linux(void);
> > +int arch_misc_init(void);
> >
> > /* board/.../... */
> > int board_init(void);
> >
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment
2018-10-30 13:44 ` Auer, Lukas
@ 2018-10-30 13:53 ` Alexander Graf
2018-10-30 14:51 ` Auer, Lukas
0 siblings, 1 reply; 56+ messages in thread
From: Alexander Graf @ 2018-10-30 13:53 UTC (permalink / raw)
To: u-boot
On 30.10.18 14:44, Auer, Lukas wrote:
> On Tue, 2018-10-30 at 14:19 +0100, Alexander Graf wrote:
>>
>> On 30.10.18 13:55, Lukas Auer wrote:
>>> The device tree passed by the prior boot stage can be used to boot
>>> Linux. Store it as environment variable "prior_stage_dtb", so that
>>> it
>>> can be used as part of the boot command.
>>>
>>> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
>>> ---
>>>
>>> Changes in v2:
>>> - New patch
>>>
>>> arch/Kconfig | 1 +
>>> arch/riscv/cpu/cpu.c | 7 +++++++
>>> arch/riscv/include/asm/u-boot-riscv.h | 1 +
>>> 3 files changed, 9 insertions(+)
>>>
>>> diff --git a/arch/Kconfig b/arch/Kconfig
>>> index 9fdd2f7e66..883e4a9308 100644
>>> --- a/arch/Kconfig
>>> +++ b/arch/Kconfig
>>> @@ -74,6 +74,7 @@ config RISCV
>>> imply MTD
>>> imply TIMER
>>> imply CMD_DM
>>> + imply ARCH_MISC_INIT
>>>
>>> config SANDBOX
>>> bool "Sandbox"
>>> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
>>> index d9f820c44c..e06a8c6bab 100644
>>> --- a/arch/riscv/cpu/cpu.c
>>> +++ b/arch/riscv/cpu/cpu.c
>>> @@ -53,3 +53,10 @@ int print_cpuinfo(void)
>>>
>>> return 0;
>>> }
>>> +
>>> +int arch_misc_init(void)
>>> +{
>>> + env_set_hex("prior_stage_dtb", prior_stage_fdt_address);
>>
>> Please reuse one of the many other variable names we have for this
>> already, such as "fdtaddr".
>>
>
> I will change the variable name.
>
>> One thing I would always recommend is that if you have a prior stage
>> DT
>> passed on to U-Boot is that U-Boot makes use of that
>> (CONFIG_OF_BOARD).
>> That again means that the DT is already available in $fdtcontroladdr
>> and
>> there is very little use for yet another env variable.
>>
>>
>> Alex
>>
>
> We are actually using the device tree passed to U-Boot (using
> CONFIG_OF_PRIOR_STAGE). The reason I'm adding the device tree address
> to the environment is so that it can be used to boot Linux. RISC-V
> Linux does not include any device trees, they are instead stored
> directly on the SoC (though this might change). This is therefore
> important to have and this is the best way I could think of, of
> implementing it.
Oh, I'm in 100% agreement that this is the right choice. I'm just
surprised we have 2 Kconfig options to basically do the same thing. The
RPi uses CONFIG_OF_BOARD while newer BCM chips seem to use
CONFIG_PRIOR_STAGE. It's slightly counterintuitive :).
What I was saying is that U-Boot should be a consumer of said "platform
device tree" and thus exposes it as $fdtcontroladdr into the
environment. So instead of
# bootefi $kernel_addr_r $fdtaddr
you could as well just use
# bootefi $kernel_addr_r $fdtcontroladdr
which the distro scripts automatically do for you, so you already have
what you asked for :).
Alex
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment
2018-10-30 13:53 ` Alexander Graf
@ 2018-10-30 14:51 ` Auer, Lukas
0 siblings, 0 replies; 56+ messages in thread
From: Auer, Lukas @ 2018-10-30 14:51 UTC (permalink / raw)
To: u-boot
On Tue, 2018-10-30 at 14:53 +0100, Alexander Graf wrote:
>
> On 30.10.18 14:44, Auer, Lukas wrote:
> > On Tue, 2018-10-30 at 14:19 +0100, Alexander Graf wrote:
> > >
> > > On 30.10.18 13:55, Lukas Auer wrote:
> > > > The device tree passed by the prior boot stage can be used to
> > > > boot
> > > > Linux. Store it as environment variable "prior_stage_dtb", so
> > > > that
> > > > it
> > > > can be used as part of the boot command.
> > > >
> > > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > > ---
> > > >
> > > > Changes in v2:
> > > > - New patch
> > > >
> > > > arch/Kconfig | 1 +
> > > > arch/riscv/cpu/cpu.c | 7 +++++++
> > > > arch/riscv/include/asm/u-boot-riscv.h | 1 +
> > > > 3 files changed, 9 insertions(+)
> > > >
> > > > diff --git a/arch/Kconfig b/arch/Kconfig
> > > > index 9fdd2f7e66..883e4a9308 100644
> > > > --- a/arch/Kconfig
> > > > +++ b/arch/Kconfig
> > > > @@ -74,6 +74,7 @@ config RISCV
> > > > imply MTD
> > > > imply TIMER
> > > > imply CMD_DM
> > > > + imply ARCH_MISC_INIT
> > > >
> > > > config SANDBOX
> > > > bool "Sandbox"
> > > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > > index d9f820c44c..e06a8c6bab 100644
> > > > --- a/arch/riscv/cpu/cpu.c
> > > > +++ b/arch/riscv/cpu/cpu.c
> > > > @@ -53,3 +53,10 @@ int print_cpuinfo(void)
> > > >
> > > > return 0;
> > > > }
> > > > +
> > > > +int arch_misc_init(void)
> > > > +{
> > > > + env_set_hex("prior_stage_dtb",
> > > > prior_stage_fdt_address);
> > >
> > > Please reuse one of the many other variable names we have for
> > > this
> > > already, such as "fdtaddr".
> > >
> >
> > I will change the variable name.
> >
> > > One thing I would always recommend is that if you have a prior
> > > stage
> > > DT
> > > passed on to U-Boot is that U-Boot makes use of that
> > > (CONFIG_OF_BOARD).
> > > That again means that the DT is already available in
> > > $fdtcontroladdr
> > > and
> > > there is very little use for yet another env variable.
> > >
> > >
> > > Alex
> > >
> >
> > We are actually using the device tree passed to U-Boot (using
> > CONFIG_OF_PRIOR_STAGE). The reason I'm adding the device tree
> > address
> > to the environment is so that it can be used to boot Linux. RISC-V
> > Linux does not include any device trees, they are instead stored
> > directly on the SoC (though this might change). This is therefore
> > important to have and this is the best way I could think of, of
> > implementing it.
>
> Oh, I'm in 100% agreement that this is the right choice. I'm just
> surprised we have 2 Kconfig options to basically do the same thing.
> The
> RPi uses CONFIG_OF_BOARD while newer BCM chips seem to use
> CONFIG_PRIOR_STAGE. It's slightly counterintuitive :).
>
That's true. I actually picked CONFIG_OF_PRIOR_STAGE just because I
didn't need the flexibility of CONFIG_OF_BOARD.
> What I was saying is that U-Boot should be a consumer of said
> "platform
> device tree" and thus exposes it as $fdtcontroladdr into the
> environment. So instead of
>
> # bootefi $kernel_addr_r $fdtaddr
>
> you could as well just use
>
> # bootefi $kernel_addr_r $fdtcontroladdr
>
> which the distro scripts automatically do for you, so you already
> have
> what you asked for :).
>
>
> Alex
Oh right, I completely missed that. Thanks for pointing that out! :)
Lukas
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-10-30 12:55 ` [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU Lukas Auer
@ 2018-10-30 15:02 ` Auer, Lukas
2018-10-30 15:27 ` Alexander Graf
2018-11-04 14:39 ` Bin Meng
1 sibling, 1 reply; 56+ messages in thread
From: Auer, Lukas @ 2018-10-30 15:02 UTC (permalink / raw)
To: u-boot
On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
> QEMU embeds the location of the kernel image in the device tree.
> Store
> this address in the environment as variable kernel_start and use it
> in
> CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed by
> the
> prior boot stage to boot Linux.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Rebase onto u-boot-dm/next
> - Boot Linux with the device tree provided by the prior boot stage
>
> board/emulation/qemu-riscv/Kconfig | 1 +
> board/emulation/qemu-riscv/qemu-riscv.c | 29
> +++++++++++++++++++++++++
> configs/qemu-riscv32_defconfig | 1 +
> configs/qemu-riscv64_defconfig | 1 +
> include/configs/qemu-riscv.h | 10 ++++++++-
> 5 files changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/board/emulation/qemu-riscv/Kconfig
> b/board/emulation/qemu-riscv/Kconfig
> index 37a80db6a9..be5839b7db 100644
> --- a/board/emulation/qemu-riscv/Kconfig
> +++ b/board/emulation/qemu-riscv/Kconfig
> @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> imply CMD_EXT2
> imply CMD_EXT4
> imply CMD_FAT
> + imply BOARD_LATE_INIT
>
> endif
> diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
> b/board/emulation/qemu-riscv/qemu-riscv.c
> index 2ce093e19a..ee20983095 100644
> --- a/board/emulation/qemu-riscv/qemu-riscv.c
> +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> @@ -19,3 +19,32 @@ int board_init(void)
>
> return 0;
> }
> +
> +int board_late_init(void)
> +{
> + ulong kernel_start;
> + ofnode chosen_node;
> + int ret;
> +
> + chosen_node = ofnode_path("/chosen");
> + if (!ofnode_valid(chosen_node)) {
> + printf("No chosen node found\n");
> + return 0;
> + }
> +
> +#ifdef CONFIG_ARCH_RV64I
> + ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
> + (u64 *)&kernel_start);
> +#else
> + ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
> + (u32 *)&kernel_start);
> +#endif
> + if (ret) {
> + printf("Can't find kernel start address in device
> tree\n");
> + return 0;
> + }
> +
> + env_set_hex("kernel_start", kernel_start);
> +
> + return 0;
> +}
> diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-
> riscv32_defconfig
> index b55644378a..13dd53a550 100644
> --- a/configs/qemu-riscv32_defconfig
> +++ b/configs/qemu-riscv32_defconfig
> @@ -4,4 +4,5 @@ CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> CONFIG_DISPLAY_CPUINFO=y
> CONFIG_DISPLAY_BOARDINFO=y
> +CONFIG_HUSH_PARSER=y
> CONFIG_OF_PRIOR_STAGE=y
> diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-
> riscv64_defconfig
> index a542ac4893..06eb3042fa 100644
> --- a/configs/qemu-riscv64_defconfig
> +++ b/configs/qemu-riscv64_defconfig
> @@ -5,4 +5,5 @@ CONFIG_NR_DRAM_BANKS=1
> CONFIG_FIT=y
> CONFIG_DISPLAY_CPUINFO=y
> CONFIG_DISPLAY_BOARDINFO=y
> +CONFIG_HUSH_PARSER=y
> CONFIG_OF_PRIOR_STAGE=y
> diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-
> riscv.h
> index ba6a18f2e6..7c88ba300a 100644
> --- a/include/configs/qemu-riscv.h
> +++ b/include/configs/qemu-riscv.h
> @@ -21,7 +21,15 @@
> #define CONFIG_ENV_SIZE SZ_4K
>
> #define CONFIG_EXTRA_ENV_SETTINGS \
> - "fdt_high=0xffffffffffffffff\0" \
> + "fdt_high=0x82000000\0" \
> + "bootm_size=0x10000000\0" \
> "initrd_high=0xffffffffffffffff\0"
>
> +#define CONFIG_BOOTCOMMAND \
> + "if env exists kernel_start; then " \
> + "bootm ${kernel_start} - ${prior_stage_dtb};" \
As Alexander Graf pointed out in reply to patch 24, we don't need the
separate environment variable "prior_stage_dtb". I will replace it with
"fdtcontroladdr" here and drop patch 24 in the next version.
> + "else " \
> + "echo Kernel address not found in the device tree;" \
> + "fi;"
> +
> #endif /* __CONFIG_H */
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-10-30 15:02 ` Auer, Lukas
@ 2018-10-30 15:27 ` Alexander Graf
2018-10-30 17:13 ` Auer, Lukas
2018-11-03 17:07 ` Auer, Lukas
0 siblings, 2 replies; 56+ messages in thread
From: Alexander Graf @ 2018-10-30 15:27 UTC (permalink / raw)
To: u-boot
On 30.10.18 16:02, Auer, Lukas wrote:
> On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
>> QEMU embeds the location of the kernel image in the device tree.
>> Store
>> this address in the environment as variable kernel_start and use it
>> in
>> CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed by
>> the
>> prior boot stage to boot Linux.
>>
>> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
>> ---
>>
>> Changes in v2:
>> - Rebase onto u-boot-dm/next
>> - Boot Linux with the device tree provided by the prior boot stage
>>
>> board/emulation/qemu-riscv/Kconfig | 1 +
>> board/emulation/qemu-riscv/qemu-riscv.c | 29
>> +++++++++++++++++++++++++
>> configs/qemu-riscv32_defconfig | 1 +
>> configs/qemu-riscv64_defconfig | 1 +
>> include/configs/qemu-riscv.h | 10 ++++++++-
>> 5 files changed, 41 insertions(+), 1 deletion(-)
>>
>> diff --git a/board/emulation/qemu-riscv/Kconfig
>> b/board/emulation/qemu-riscv/Kconfig
>> index 37a80db6a9..be5839b7db 100644
>> --- a/board/emulation/qemu-riscv/Kconfig
>> +++ b/board/emulation/qemu-riscv/Kconfig
>> @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>> imply CMD_EXT2
>> imply CMD_EXT4
>> imply CMD_FAT
>> + imply BOARD_LATE_INIT
>>
>> endif
>> diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
>> b/board/emulation/qemu-riscv/qemu-riscv.c
>> index 2ce093e19a..ee20983095 100644
>> --- a/board/emulation/qemu-riscv/qemu-riscv.c
>> +++ b/board/emulation/qemu-riscv/qemu-riscv.c
>> @@ -19,3 +19,32 @@ int board_init(void)
>>
>> return 0;
>> }
>> +
>> +int board_late_init(void)
>> +{
>> + ulong kernel_start;
>> + ofnode chosen_node;
>> + int ret;
>> +
>> + chosen_node = ofnode_path("/chosen");
>> + if (!ofnode_valid(chosen_node)) {
>> + printf("No chosen node found\n");
>> + return 0;
>> + }
>> +
>> +#ifdef CONFIG_ARCH_RV64I
>> + ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
>> + (u64 *)&kernel_start);
>> +#else
>> + ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
>> + (u32 *)&kernel_start);
>> +#endif
>> + if (ret) {
>> + printf("Can't find kernel start address in device
>> tree\n");
>> + return 0;
>> + }
>> +
>> + env_set_hex("kernel_start", kernel_start);
>> +
>> + return 0;
>> +}
>> diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-
>> riscv32_defconfig
>> index b55644378a..13dd53a550 100644
>> --- a/configs/qemu-riscv32_defconfig
>> +++ b/configs/qemu-riscv32_defconfig
>> @@ -4,4 +4,5 @@ CONFIG_NR_DRAM_BANKS=1
>> CONFIG_FIT=y
>> CONFIG_DISPLAY_CPUINFO=y
>> CONFIG_DISPLAY_BOARDINFO=y
>> +CONFIG_HUSH_PARSER=y
>> CONFIG_OF_PRIOR_STAGE=y
>> diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-
>> riscv64_defconfig
>> index a542ac4893..06eb3042fa 100644
>> --- a/configs/qemu-riscv64_defconfig
>> +++ b/configs/qemu-riscv64_defconfig
>> @@ -5,4 +5,5 @@ CONFIG_NR_DRAM_BANKS=1
>> CONFIG_FIT=y
>> CONFIG_DISPLAY_CPUINFO=y
>> CONFIG_DISPLAY_BOARDINFO=y
>> +CONFIG_HUSH_PARSER=y
>> CONFIG_OF_PRIOR_STAGE=y
>> diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-
>> riscv.h
>> index ba6a18f2e6..7c88ba300a 100644
>> --- a/include/configs/qemu-riscv.h
>> +++ b/include/configs/qemu-riscv.h
>> @@ -21,7 +21,15 @@
>> #define CONFIG_ENV_SIZE SZ_4K
>>
>> #define CONFIG_EXTRA_ENV_SETTINGS \
>> - "fdt_high=0xffffffffffffffff\0" \
>> + "fdt_high=0x82000000\0" \
>> + "bootm_size=0x10000000\0" \
>> "initrd_high=0xffffffffffffffff\0"
>>
>> +#define CONFIG_BOOTCOMMAND \
>> + "if env exists kernel_start; then " \
>> + "bootm ${kernel_start} - ${prior_stage_dtb};" \
>
> As Alexander Graf pointed out in reply to patch 24, we don't need the
> separate environment variable "prior_stage_dtb". I will replace it with
> "fdtcontroladdr" here and drop patch 24 in the next version.
Also, can you please enable distro boot? :)
Thanks,
Alex
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-10-30 15:27 ` Alexander Graf
@ 2018-10-30 17:13 ` Auer, Lukas
2018-11-03 17:07 ` Auer, Lukas
1 sibling, 0 replies; 56+ messages in thread
From: Auer, Lukas @ 2018-10-30 17:13 UTC (permalink / raw)
To: u-boot
On Tue, 2018-10-30 at 16:27 +0100, Alexander Graf wrote:
>
> On 30.10.18 16:02, Auer, Lukas wrote:
> > On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
> > > QEMU embeds the location of the kernel image in the device tree.
> > > Store
> > > this address in the environment as variable kernel_start and use
> > > it
> > > in
> > > CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed
> > > by
> > > the
> > > prior boot stage to boot Linux.
> > >
> > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > ---
> > >
> > > Changes in v2:
> > > - Rebase onto u-boot-dm/next
> > > - Boot Linux with the device tree provided by the prior boot
> > > stage
> > >
> > > board/emulation/qemu-riscv/Kconfig | 1 +
> > > board/emulation/qemu-riscv/qemu-riscv.c | 29
> > > +++++++++++++++++++++++++
> > > configs/qemu-riscv32_defconfig | 1 +
> > > configs/qemu-riscv64_defconfig | 1 +
> > > include/configs/qemu-riscv.h | 10 ++++++++-
> > > 5 files changed, 41 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/board/emulation/qemu-riscv/Kconfig
> > > b/board/emulation/qemu-riscv/Kconfig
> > > index 37a80db6a9..be5839b7db 100644
> > > --- a/board/emulation/qemu-riscv/Kconfig
> > > +++ b/board/emulation/qemu-riscv/Kconfig
> > > @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > imply CMD_EXT2
> > > imply CMD_EXT4
> > > imply CMD_FAT
> > > + imply BOARD_LATE_INIT
> > >
> > > endif
> > > diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
> > > b/board/emulation/qemu-riscv/qemu-riscv.c
> > > index 2ce093e19a..ee20983095 100644
> > > --- a/board/emulation/qemu-riscv/qemu-riscv.c
> > > +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> > > @@ -19,3 +19,32 @@ int board_init(void)
> > >
> > > return 0;
> > > }
> > > +
> > > +int board_late_init(void)
> > > +{
> > > + ulong kernel_start;
> > > + ofnode chosen_node;
> > > + int ret;
> > > +
> > > + chosen_node = ofnode_path("/chosen");
> > > + if (!ofnode_valid(chosen_node)) {
> > > + printf("No chosen node found\n");
> > > + return 0;
> > > + }
> > > +
> > > +#ifdef CONFIG_ARCH_RV64I
> > > + ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
> > > + (u64 *)&kernel_start);
> > > +#else
> > > + ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
> > > + (u32 *)&kernel_start);
> > > +#endif
> > > + if (ret) {
> > > + printf("Can't find kernel start address in device
> > > tree\n");
> > > + return 0;
> > > + }
> > > +
> > > + env_set_hex("kernel_start", kernel_start);
> > > +
> > > + return 0;
> > > +}
> > > diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-
> > > riscv32_defconfig
> > > index b55644378a..13dd53a550 100644
> > > --- a/configs/qemu-riscv32_defconfig
> > > +++ b/configs/qemu-riscv32_defconfig
> > > @@ -4,4 +4,5 @@ CONFIG_NR_DRAM_BANKS=1
> > > CONFIG_FIT=y
> > > CONFIG_DISPLAY_CPUINFO=y
> > > CONFIG_DISPLAY_BOARDINFO=y
> > > +CONFIG_HUSH_PARSER=y
> > > CONFIG_OF_PRIOR_STAGE=y
> > > diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-
> > > riscv64_defconfig
> > > index a542ac4893..06eb3042fa 100644
> > > --- a/configs/qemu-riscv64_defconfig
> > > +++ b/configs/qemu-riscv64_defconfig
> > > @@ -5,4 +5,5 @@ CONFIG_NR_DRAM_BANKS=1
> > > CONFIG_FIT=y
> > > CONFIG_DISPLAY_CPUINFO=y
> > > CONFIG_DISPLAY_BOARDINFO=y
> > > +CONFIG_HUSH_PARSER=y
> > > CONFIG_OF_PRIOR_STAGE=y
> > > diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-
> > > riscv.h
> > > index ba6a18f2e6..7c88ba300a 100644
> > > --- a/include/configs/qemu-riscv.h
> > > +++ b/include/configs/qemu-riscv.h
> > > @@ -21,7 +21,15 @@
> > > #define CONFIG_ENV_SIZE SZ_4K
> > >
> > > #define CONFIG_EXTRA_ENV_SETTINGS \
> > > - "fdt_high=0xffffffffffffffff\0" \
> > > + "fdt_high=0x82000000\0" \
> > > + "bootm_size=0x10000000\0" \
> > > "initrd_high=0xffffffffffffffff\0"
> > >
> > > +#define CONFIG_BOOTCOMMAND \
> > > + "if env exists kernel_start; then " \
> > > + "bootm ${kernel_start} - ${prior_stage_dtb};" \
> >
> > As Alexander Graf pointed out in reply to patch 24, we don't need
> > the
> > separate environment variable "prior_stage_dtb". I will replace it
> > with
> > "fdtcontroladdr" here and drop patch 24 in the next version.
>
> Also, can you please enable distro boot? :)
>
>
> Thanks,
>
> Alex
I haven't used distro boot yet, but I will take a look and see if I can
get it working. :)
Thanks,
Lukas
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 05/29] riscv: add Kconfig entries for the C and A ISA extensions
2018-10-30 12:55 ` [U-Boot] [PATCH v2 05/29] riscv: add Kconfig entries for the C and A ISA extensions Lukas Auer
@ 2018-10-31 2:13 ` Bin Meng
0 siblings, 0 replies; 56+ messages in thread
From: Bin Meng @ 2018-10-31 2:13 UTC (permalink / raw)
To: u-boot
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Add Kconfig entries for the C (compressed instructions) and A (atomic
> instructions) ISA extensions. Only the C ISA extension is selectable.
> This matches the configuration in Linux.
>
> The Kconfig entries are not used yet. A follow-up patch will select the
> appropriate compiler flags based on the Kconfig configuration.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Replace the description of RISCV_ISA_C with that of the Linux kernel,
> as suggested by Bin Meng
>
> arch/riscv/Kconfig | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 06/29] riscv: set -march and -mabi based on the Kconfig configuration
2018-10-30 12:55 ` [U-Boot] [PATCH v2 06/29] riscv: set -march and -mabi based on the Kconfig configuration Lukas Auer
@ 2018-10-31 2:13 ` Bin Meng
0 siblings, 0 replies; 56+ messages in thread
From: Bin Meng @ 2018-10-31 2:13 UTC (permalink / raw)
To: u-boot
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Use the new Kconfig entries to construct the ISA string for the -march
> compiler flag. The -mabi compiler flag is selected based on the base
> integer instruction set.
>
> With this change, the C (compressed instructions) ISA extension is now
> enabled for all boards with CONFIG_RISCV_ISA_C set. Buildman reports a
> decrease in binary size of 71590 bytes.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Change ISA string construction, as suggested by Bin Meng
>
> arch/riscv/Makefile | 20 ++++++++++++++++++++
> arch/riscv/config.mk | 4 ----
> 2 files changed, 20 insertions(+), 4 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model
2018-10-30 12:55 ` [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model Lukas Auer
@ 2018-10-31 2:13 ` Bin Meng
2018-10-31 15:01 ` Auer, Lukas
0 siblings, 1 reply; 56+ messages in thread
From: Bin Meng @ 2018-10-31 2:13 UTC (permalink / raw)
To: u-boot
Hi Lukas,
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> RISC-V has two code models, medium low (medlow) and medium any (medany).
> Medlow limits addressable memory to a single 2 GiB range between the
> absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
> to any single 2 GiB address range.
> By default, medlow is selected on 32-bit systems and medany on 64-bit
> systems. This matches the configuration in Linux.
>
> The -mcmodel compiler flag is selected according to the Kconfig
> configuration.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Change ISA string construction, as suggested by Bin Meng
>
> arch/riscv/Kconfig | 19 +++++++++++++++++++
> arch/riscv/Makefile | 9 ++++++++-
> 2 files changed, 27 insertions(+), 1 deletion(-)
>
I had a further look at this, and I suspect we should stick to medlow
for U-Boot, even for 64-bit. As U-Boot will be only running within the
low 4GB memory space even for 64-bit. Adding medany seems unnecessary.
Regards,
Bin
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 09/29] riscv: fix use of incorrectly sized variables
2018-10-30 12:55 ` [U-Boot] [PATCH v2 09/29] riscv: fix use of incorrectly sized variables Lukas Auer
@ 2018-10-31 2:13 ` Bin Meng
0 siblings, 0 replies; 56+ messages in thread
From: Bin Meng @ 2018-10-31 2:13 UTC (permalink / raw)
To: u-boot
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
> several places. Fix this.
> In addition, BITS_PER_LONG is set to 64 on RV64I systems.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Remove 0-padding in the format string to avoid printing 16 digits on
> RV32I systems
>
> arch/riscv/include/asm/io.h | 6 +++---
> arch/riscv/include/asm/posix_types.h | 6 +++---
> arch/riscv/include/asm/types.h | 4 ++++
> arch/riscv/lib/interrupts.c | 10 +++++-----
> 4 files changed, 15 insertions(+), 11 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 16/29] riscv: invalidate the instruction cache before jumping to Linux
2018-10-30 12:55 ` [U-Boot] [PATCH v2 16/29] riscv: invalidate the instruction cache before jumping to Linux Lukas Auer
@ 2018-10-31 2:14 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A3ECAA@ATCPCS16.andestech.com>
1 sibling, 0 replies; 56+ messages in thread
From: Bin Meng @ 2018-10-31 2:14 UTC (permalink / raw)
To: u-boot
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> RISC-V does not guarantee that stores to instruction memory are visible
> to instruction fetches (i.e. incoherent instruction caches). Invalidate
> the instruction cache to ensure the kernel function pointer points to
> the correct memory location.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Clarify reasoning behind patch in commit message
>
> arch/riscv/lib/bootm.c | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 20/29] riscv: remove unused labels in start.S
2018-10-30 12:55 ` [U-Boot] [PATCH v2 20/29] riscv: remove unused labels in start.S Lukas Auer
@ 2018-10-31 2:14 ` Bin Meng
0 siblings, 0 replies; 56+ messages in thread
From: Bin Meng @ 2018-10-31 2:14 UTC (permalink / raw)
To: u-boot
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> The labels nmi_vector, trap_vector and handle_reset in start.S are not
> used for RISC-V. Remove them.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Drop removal of code that stores the contents of a2; this broke the
> board ax25-ae350. The code will be removed again in a future patch.
>
> arch/riscv/cpu/start.S | 9 ---------
> 1 file changed, 9 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64
2018-10-30 12:55 ` [U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64 Lukas Auer
@ 2018-10-31 2:14 ` Bin Meng
2018-11-03 6:08 ` Simon Glass
1 sibling, 0 replies; 56+ messages in thread
From: Bin Meng @ 2018-10-31 2:14 UTC (permalink / raw)
To: u-boot
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Move prototype location to match the location of the function in
> ofnode.c
>
> include/dm/ofnode.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL
2018-10-30 12:55 ` [U-Boot] [PATCH v2 29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL Lukas Auer
@ 2018-10-31 2:14 ` Bin Meng
0 siblings, 0 replies; 56+ messages in thread
From: Bin Meng @ 2018-10-31 2:14 UTC (permalink / raw)
To: u-boot
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> QEMU specifies the location of Linux (supplied with the -kernel
> argument) in the device tree using the riscv,kernel-start and
> riscv,kernel-end properties. We currently rely on the SBI implementation
> of BBL to run Linux and therefore embed Linux as payload in BBL. This
> causes an issue, because BBL detects the kernel properties in the device
> tree and ignores the Linux payload as a result.
> Work around this issue by clearing the kernel properties in the device
> tree before booting Linux.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - New patch
>
> board/emulation/qemu-riscv/Kconfig | 1 +
> board/emulation/qemu-riscv/qemu-riscv.c | 39 +++++++++++++++++++++++++
> 2 files changed, 40 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model
2018-10-31 2:13 ` Bin Meng
@ 2018-10-31 15:01 ` Auer, Lukas
2018-11-13 7:34 ` Bin Meng
0 siblings, 1 reply; 56+ messages in thread
From: Auer, Lukas @ 2018-10-31 15:01 UTC (permalink / raw)
To: u-boot
Hi Bin,
On Wed, 2018-10-31 at 10:13 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
> <lukas.auer@aisec.fraunhofer.de> wrote:
> >
> > RISC-V has two code models, medium low (medlow) and medium any
> > (medany).
> > Medlow limits addressable memory to a single 2 GiB range between
> > the
> > absolute addresses -2 GiB and +2 GiB. Medany limits addressable
> > memory
> > to any single 2 GiB address range.
> > By default, medlow is selected on 32-bit systems and medany on 64-
> > bit
> > systems. This matches the configuration in Linux.
> >
> > The -mcmodel compiler flag is selected according to the Kconfig
> > configuration.
> >
> > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > ---
> >
> > Changes in v2:
> > - Change ISA string construction, as suggested by Bin Meng
> >
> > arch/riscv/Kconfig | 19 +++++++++++++++++++
> > arch/riscv/Makefile | 9 ++++++++-
> > 2 files changed, 27 insertions(+), 1 deletion(-)
> >
>
> I had a further look at this, and I suspect we should stick to medlow
> for U-Boot, even for 64-bit. As U-Boot will be only running within
> the
> low 4GB memory space even for 64-bit. Adding medany seems
> unnecessary.
>
> Regards,
> Bin
You are right, however I think it's actually because U-Boot is compiled
as a position independent binary. U-Boot can be relocated above what's
addressable with 32-bit if the memory is large enough. This should
cause issues with medlow.
I suspects that's the reason, but I am not entirely sure. What do you
think?
Thanks,
Lukas
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 16/29] riscv: invalidate the instruction cache before jumping to Linux
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A3ECAA@ATCPCS16.andestech.com>
@ 2018-11-01 4:23 ` Rick Chen
0 siblings, 0 replies; 56+ messages in thread
From: Rick Chen @ 2018-11-01 4:23 UTC (permalink / raw)
To: u-boot
<rick@andestech.com> 於 2018年11月1日 週四 下午12:13寫道:
>
> > RISC-V does not guarantee that stores to instruction memory are visible to
> > instruction fetches (i.e. incoherent instruction caches). Invalidate the instruction
> > cache to ensure the kernel function pointer points to the correct memory
> > location.
> >
> > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > ---
> >
> > Changes in v2:
> > - Clarify reasoning behind patch in commit message
> >
> > arch/riscv/lib/bootm.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index
> > 2b5ccce933..c1cf618806 100644
> > --- a/arch/riscv/lib/bootm.c
> > +++ b/arch/riscv/lib/bootm.c
> > @@ -40,6 +40,7 @@ int do_bootm_linux(int flag, int argc, char *argv[],
> > bootm_headers_t *images)
> > return 1;
> >
> > kernel = (void (*)(ulong, void *))images->ep;
> > + invalidate_icache_all();
> >
Hi Lukas
[PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]
will implement
+void cache_flush(void)
{
+ invalidate_icache_all();
+ flush_dcache_all();
}
It seem redundant here.
Rick
> > bootstage_mark(BOOTSTAGE_ID_RUN_OS);
> >
> > --
> > 2.17.2
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64
2018-10-30 12:55 ` [U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64 Lukas Auer
2018-10-31 2:14 ` Bin Meng
@ 2018-11-03 6:08 ` Simon Glass
1 sibling, 0 replies; 56+ messages in thread
From: Simon Glass @ 2018-11-03 6:08 UTC (permalink / raw)
To: u-boot
On 30 October 2018 at 06:55, Lukas Auer <lukas.auer@aisec.fraunhofer.de> wrote:
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Move prototype location to match the location of the function in
> ofnode.c
>
> include/dm/ofnode.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
Thanks.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-10-30 15:27 ` Alexander Graf
2018-10-30 17:13 ` Auer, Lukas
@ 2018-11-03 17:07 ` Auer, Lukas
2018-11-03 19:33 ` Alexander Graf
1 sibling, 1 reply; 56+ messages in thread
From: Auer, Lukas @ 2018-11-03 17:07 UTC (permalink / raw)
To: u-boot
On Tue, 2018-10-30 at 16:27 +0100, Alexander Graf wrote:
>
> On 30.10.18 16:02, Auer, Lukas wrote:
> > On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
> > > QEMU embeds the location of the kernel image in the device tree.
> > > Store
> > > this address in the environment as variable kernel_start and use
> > > it
> > > in
> > > CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed
> > > by
> > > the
> > > prior boot stage to boot Linux.
> > >
> > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > ---
> > >
> > > Changes in v2:
> > > - Rebase onto u-boot-dm/next
> > > - Boot Linux with the device tree provided by the prior boot
> > > stage
> > >
> > > board/emulation/qemu-riscv/Kconfig | 1 +
> > > board/emulation/qemu-riscv/qemu-riscv.c | 29
> > > +++++++++++++++++++++++++
> > > configs/qemu-riscv32_defconfig | 1 +
> > > configs/qemu-riscv64_defconfig | 1 +
> > > include/configs/qemu-riscv.h | 10 ++++++++-
> > > 5 files changed, 41 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/board/emulation/qemu-riscv/Kconfig
> > > b/board/emulation/qemu-riscv/Kconfig
> > > index 37a80db6a9..be5839b7db 100644
> > > --- a/board/emulation/qemu-riscv/Kconfig
> > > +++ b/board/emulation/qemu-riscv/Kconfig
> > > @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > imply CMD_EXT2
> > > imply CMD_EXT4
> > > imply CMD_FAT
> > > + imply BOARD_LATE_INIT
> > >
> > > endif
> > > diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
> > > b/board/emulation/qemu-riscv/qemu-riscv.c
> > > index 2ce093e19a..ee20983095 100644
> > > --- a/board/emulation/qemu-riscv/qemu-riscv.c
> > > +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> > > @@ -19,3 +19,32 @@ int board_init(void)
> > >
> > > return 0;
> > > }
> > > +
> > > +int board_late_init(void)
> > > +{
> > > + ulong kernel_start;
> > > + ofnode chosen_node;
> > > + int ret;
> > > +
> > > + chosen_node = ofnode_path("/chosen");
> > > + if (!ofnode_valid(chosen_node)) {
> > > + printf("No chosen node found\n");
> > > + return 0;
> > > + }
> > > +
> > > +#ifdef CONFIG_ARCH_RV64I
> > > + ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
> > > + (u64 *)&kernel_start);
> > > +#else
> > > + ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
> > > + (u32 *)&kernel_start);
> > > +#endif
> > > + if (ret) {
> > > + printf("Can't find kernel start address in device
> > > tree\n");
> > > + return 0;
> > > + }
> > > +
> > > + env_set_hex("kernel_start", kernel_start);
> > > +
> > > + return 0;
> > > +}
> > > diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-
> > > riscv32_defconfig
> > > index b55644378a..13dd53a550 100644
> > > --- a/configs/qemu-riscv32_defconfig
> > > +++ b/configs/qemu-riscv32_defconfig
> > > @@ -4,4 +4,5 @@ CONFIG_NR_DRAM_BANKS=1
> > > CONFIG_FIT=y
> > > CONFIG_DISPLAY_CPUINFO=y
> > > CONFIG_DISPLAY_BOARDINFO=y
> > > +CONFIG_HUSH_PARSER=y
> > > CONFIG_OF_PRIOR_STAGE=y
> > > diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-
> > > riscv64_defconfig
> > > index a542ac4893..06eb3042fa 100644
> > > --- a/configs/qemu-riscv64_defconfig
> > > +++ b/configs/qemu-riscv64_defconfig
> > > @@ -5,4 +5,5 @@ CONFIG_NR_DRAM_BANKS=1
> > > CONFIG_FIT=y
> > > CONFIG_DISPLAY_CPUINFO=y
> > > CONFIG_DISPLAY_BOARDINFO=y
> > > +CONFIG_HUSH_PARSER=y
> > > CONFIG_OF_PRIOR_STAGE=y
> > > diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-
> > > riscv.h
> > > index ba6a18f2e6..7c88ba300a 100644
> > > --- a/include/configs/qemu-riscv.h
> > > +++ b/include/configs/qemu-riscv.h
> > > @@ -21,7 +21,15 @@
> > > #define CONFIG_ENV_SIZE SZ_4K
> > >
> > > #define CONFIG_EXTRA_ENV_SETTINGS \
> > > - "fdt_high=0xffffffffffffffff\0" \
> > > + "fdt_high=0x82000000\0" \
> > > + "bootm_size=0x10000000\0" \
> > > "initrd_high=0xffffffffffffffff\0"
> > >
> > > +#define CONFIG_BOOTCOMMAND \
> > > + "if env exists kernel_start; then " \
> > > + "bootm ${kernel_start} - ${prior_stage_dtb};" \
> >
> > As Alexander Graf pointed out in reply to patch 24, we don't need
> > the
> > separate environment variable "prior_stage_dtb". I will replace it
> > with
> > "fdtcontroladdr" here and drop patch 24 in the next version.
>
> Also, can you please enable distro boot? :)
>
>
> Thanks,
>
> Alex
I just had a closer look at distro boot and it's actually quite easy to
use. I will update this patch to enable it and will add a bootcmd for
virtio block devices (virtio support is currently in u-boot-dm/next).
I was looking into testing bootefi on U-Boot and tried to run the hello
world and selftest EFI binaries, however I could not get them running.
After starting them I immediately get a load access fault. The faulting
instruction is at 0xfe77c1fa, which is strange since the binary is
loaded to 0x80200000. Do you know what this could be caused by?
Also note that I completed the list of exception codes in this patch
series. U-Boot master will not indicate this exception occurred.
Thanks,
Lukas
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-11-03 17:07 ` Auer, Lukas
@ 2018-11-03 19:33 ` Alexander Graf
2018-11-04 12:52 ` Auer, Lukas
0 siblings, 1 reply; 56+ messages in thread
From: Alexander Graf @ 2018-11-03 19:33 UTC (permalink / raw)
To: u-boot
On 03.11.18 18:07, Auer, Lukas wrote:
> On Tue, 2018-10-30 at 16:27 +0100, Alexander Graf wrote:
>>
>> On 30.10.18 16:02, Auer, Lukas wrote:
>>> On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
>>>> QEMU embeds the location of the kernel image in the device tree.
>>>> Store
>>>> this address in the environment as variable kernel_start and use
>>>> it
>>>> in
>>>> CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed
>>>> by
>>>> the
>>>> prior boot stage to boot Linux.
>>>>
>>>> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
>>>> ---
>>>>
>>>> Changes in v2:
>>>> - Rebase onto u-boot-dm/next
>>>> - Boot Linux with the device tree provided by the prior boot
>>>> stage
>>>>
>>>> board/emulation/qemu-riscv/Kconfig | 1 +
>>>> board/emulation/qemu-riscv/qemu-riscv.c | 29
>>>> +++++++++++++++++++++++++
>>>> configs/qemu-riscv32_defconfig | 1 +
>>>> configs/qemu-riscv64_defconfig | 1 +
>>>> include/configs/qemu-riscv.h | 10 ++++++++-
>>>> 5 files changed, 41 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/board/emulation/qemu-riscv/Kconfig
>>>> b/board/emulation/qemu-riscv/Kconfig
>>>> index 37a80db6a9..be5839b7db 100644
>>>> --- a/board/emulation/qemu-riscv/Kconfig
>>>> +++ b/board/emulation/qemu-riscv/Kconfig
>>>> @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>>>> imply CMD_EXT2
>>>> imply CMD_EXT4
>>>> imply CMD_FAT
>>>> + imply BOARD_LATE_INIT
>>>>
>>>> endif
>>>> diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
>>>> b/board/emulation/qemu-riscv/qemu-riscv.c
>>>> index 2ce093e19a..ee20983095 100644
>>>> --- a/board/emulation/qemu-riscv/qemu-riscv.c
>>>> +++ b/board/emulation/qemu-riscv/qemu-riscv.c
>>>> @@ -19,3 +19,32 @@ int board_init(void)
>>>>
>>>> return 0;
>>>> }
>>>> +
>>>> +int board_late_init(void)
>>>> +{
>>>> + ulong kernel_start;
>>>> + ofnode chosen_node;
>>>> + int ret;
>>>> +
>>>> + chosen_node = ofnode_path("/chosen");
>>>> + if (!ofnode_valid(chosen_node)) {
>>>> + printf("No chosen node found\n");
>>>> + return 0;
>>>> + }
>>>> +
>>>> +#ifdef CONFIG_ARCH_RV64I
>>>> + ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
>>>> + (u64 *)&kernel_start);
>>>> +#else
>>>> + ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
>>>> + (u32 *)&kernel_start);
>>>> +#endif
>>>> + if (ret) {
>>>> + printf("Can't find kernel start address in device
>>>> tree\n");
>>>> + return 0;
>>>> + }
>>>> +
>>>> + env_set_hex("kernel_start", kernel_start);
>>>> +
>>>> + return 0;
>>>> +}
>>>> diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-
>>>> riscv32_defconfig
>>>> index b55644378a..13dd53a550 100644
>>>> --- a/configs/qemu-riscv32_defconfig
>>>> +++ b/configs/qemu-riscv32_defconfig
>>>> @@ -4,4 +4,5 @@ CONFIG_NR_DRAM_BANKS=1
>>>> CONFIG_FIT=y
>>>> CONFIG_DISPLAY_CPUINFO=y
>>>> CONFIG_DISPLAY_BOARDINFO=y
>>>> +CONFIG_HUSH_PARSER=y
>>>> CONFIG_OF_PRIOR_STAGE=y
>>>> diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-
>>>> riscv64_defconfig
>>>> index a542ac4893..06eb3042fa 100644
>>>> --- a/configs/qemu-riscv64_defconfig
>>>> +++ b/configs/qemu-riscv64_defconfig
>>>> @@ -5,4 +5,5 @@ CONFIG_NR_DRAM_BANKS=1
>>>> CONFIG_FIT=y
>>>> CONFIG_DISPLAY_CPUINFO=y
>>>> CONFIG_DISPLAY_BOARDINFO=y
>>>> +CONFIG_HUSH_PARSER=y
>>>> CONFIG_OF_PRIOR_STAGE=y
>>>> diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-
>>>> riscv.h
>>>> index ba6a18f2e6..7c88ba300a 100644
>>>> --- a/include/configs/qemu-riscv.h
>>>> +++ b/include/configs/qemu-riscv.h
>>>> @@ -21,7 +21,15 @@
>>>> #define CONFIG_ENV_SIZE SZ_4K
>>>>
>>>> #define CONFIG_EXTRA_ENV_SETTINGS \
>>>> - "fdt_high=0xffffffffffffffff\0" \
>>>> + "fdt_high=0x82000000\0" \
>>>> + "bootm_size=0x10000000\0" \
>>>> "initrd_high=0xffffffffffffffff\0"
>>>>
>>>> +#define CONFIG_BOOTCOMMAND \
>>>> + "if env exists kernel_start; then " \
>>>> + "bootm ${kernel_start} - ${prior_stage_dtb};" \
>>>
>>> As Alexander Graf pointed out in reply to patch 24, we don't need
>>> the
>>> separate environment variable "prior_stage_dtb". I will replace it
>>> with
>>> "fdtcontroladdr" here and drop patch 24 in the next version.
>>
>> Also, can you please enable distro boot? :)
>>
>>
>> Thanks,
>>
>> Alex
>
> I just had a closer look at distro boot and it's actually quite easy to
> use. I will update this patch to enable it and will add a bootcmd for
> virtio block devices (virtio support is currently in u-boot-dm/next).
>
> I was looking into testing bootefi on U-Boot and tried to run the hello
> world and selftest EFI binaries, however I could not get them running.
> After starting them I immediately get a load access fault. The faulting
> instruction is at 0xfe77c1fa, which is strange since the binary is
> loaded to 0x80200000. Do you know what this could be caused by?
I'm not quite sure yet what goes wrong. I tested and verified the riscv
uefi port on andes targets (where at least grub still works), but I can
confirm that the same code just falls apart for me on the qemu target.
Any help to debug it down a bit further is much appreciated.
> Also note that I completed the list of exception codes in this patch
> series. U-Boot master will not indicate this exception occurred.
Ah nice, that will definitely help to debug what's going wrong :).
Alex
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-11-03 19:33 ` Alexander Graf
@ 2018-11-04 12:52 ` Auer, Lukas
2018-11-04 21:19 ` Alexander Graf
0 siblings, 1 reply; 56+ messages in thread
From: Auer, Lukas @ 2018-11-04 12:52 UTC (permalink / raw)
To: u-boot
On Sat, 2018-11-03 at 20:33 +0100, Alexander Graf wrote:
>
> On 03.11.18 18:07, Auer, Lukas wrote:
> > On Tue, 2018-10-30 at 16:27 +0100, Alexander Graf wrote:
> > >
> > > On 30.10.18 16:02, Auer, Lukas wrote:
> > > > On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
> > > > > QEMU embeds the location of the kernel image in the device
> > > > > tree.
> > > > > Store
> > > > > this address in the environment as variable kernel_start and
> > > > > use
> > > > > it
> > > > > in
> > > > > CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree
> > > > > passed
> > > > > by
> > > > > the
> > > > > prior boot stage to boot Linux.
> > > > >
> > > > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > > > ---
> > > > >
> > > > > Changes in v2:
> > > > > - Rebase onto u-boot-dm/next
> > > > > - Boot Linux with the device tree provided by the prior boot
> > > > > stage
> > > > >
> > > > > board/emulation/qemu-riscv/Kconfig | 1 +
> > > > > board/emulation/qemu-riscv/qemu-riscv.c | 29
> > > > > +++++++++++++++++++++++++
> > > > > configs/qemu-riscv32_defconfig | 1 +
> > > > > configs/qemu-riscv64_defconfig | 1 +
> > > > > include/configs/qemu-riscv.h | 10 ++++++++-
> > > > > 5 files changed, 41 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/board/emulation/qemu-riscv/Kconfig
> > > > > b/board/emulation/qemu-riscv/Kconfig
> > > > > index 37a80db6a9..be5839b7db 100644
> > > > > --- a/board/emulation/qemu-riscv/Kconfig
> > > > > +++ b/board/emulation/qemu-riscv/Kconfig
> > > > > @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > > > > imply CMD_EXT2
> > > > > imply CMD_EXT4
> > > > > imply CMD_FAT
> > > > > + imply BOARD_LATE_INIT
> > > > >
> > > > > endif
> > > > > diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
> > > > > b/board/emulation/qemu-riscv/qemu-riscv.c
> > > > > index 2ce093e19a..ee20983095 100644
> > > > > --- a/board/emulation/qemu-riscv/qemu-riscv.c
> > > > > +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> > > > > @@ -19,3 +19,32 @@ int board_init(void)
> > > > >
> > > > > return 0;
> > > > > }
> > > > > +
> > > > > +int board_late_init(void)
> > > > > +{
> > > > > + ulong kernel_start;
> > > > > + ofnode chosen_node;
> > > > > + int ret;
> > > > > +
> > > > > + chosen_node = ofnode_path("/chosen");
> > > > > + if (!ofnode_valid(chosen_node)) {
> > > > > + printf("No chosen node found\n");
> > > > > + return 0;
> > > > > + }
> > > > > +
> > > > > +#ifdef CONFIG_ARCH_RV64I
> > > > > + ret = ofnode_read_u64(chosen_node, "riscv,kernel-
> > > > > start",
> > > > > + (u64 *)&kernel_start);
> > > > > +#else
> > > > > + ret = ofnode_read_u32(chosen_node, "riscv,kernel-
> > > > > start",
> > > > > + (u32 *)&kernel_start);
> > > > > +#endif
> > > > > + if (ret) {
> > > > > + printf("Can't find kernel start address in
> > > > > device
> > > > > tree\n");
> > > > > + return 0;
> > > > > + }
> > > > > +
> > > > > + env_set_hex("kernel_start", kernel_start);
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-
> > > > > riscv32_defconfig
> > > > > index b55644378a..13dd53a550 100644
> > > > > --- a/configs/qemu-riscv32_defconfig
> > > > > +++ b/configs/qemu-riscv32_defconfig
> > > > > @@ -4,4 +4,5 @@ CONFIG_NR_DRAM_BANKS=1
> > > > > CONFIG_FIT=y
> > > > > CONFIG_DISPLAY_CPUINFO=y
> > > > > CONFIG_DISPLAY_BOARDINFO=y
> > > > > +CONFIG_HUSH_PARSER=y
> > > > > CONFIG_OF_PRIOR_STAGE=y
> > > > > diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-
> > > > > riscv64_defconfig
> > > > > index a542ac4893..06eb3042fa 100644
> > > > > --- a/configs/qemu-riscv64_defconfig
> > > > > +++ b/configs/qemu-riscv64_defconfig
> > > > > @@ -5,4 +5,5 @@ CONFIG_NR_DRAM_BANKS=1
> > > > > CONFIG_FIT=y
> > > > > CONFIG_DISPLAY_CPUINFO=y
> > > > > CONFIG_DISPLAY_BOARDINFO=y
> > > > > +CONFIG_HUSH_PARSER=y
> > > > > CONFIG_OF_PRIOR_STAGE=y
> > > > > diff --git a/include/configs/qemu-riscv.h
> > > > > b/include/configs/qemu-
> > > > > riscv.h
> > > > > index ba6a18f2e6..7c88ba300a 100644
> > > > > --- a/include/configs/qemu-riscv.h
> > > > > +++ b/include/configs/qemu-riscv.h
> > > > > @@ -21,7 +21,15 @@
> > > > > #define CONFIG_ENV_SIZE SZ_4K
> > > > >
> > > > > #define CONFIG_EXTRA_ENV_SETTINGS \
> > > > > - "fdt_high=0xffffffffffffffff\0" \
> > > > > + "fdt_high=0x82000000\0" \
> > > > > + "bootm_size=0x10000000\0" \
> > > > > "initrd_high=0xffffffffffffffff\0"
> > > > >
> > > > > +#define CONFIG_BOOTCOMMAND \
> > > > > + "if env exists kernel_start; then " \
> > > > > + "bootm ${kernel_start} - ${prior_stage_dtb};" \
> > > >
> > > > As Alexander Graf pointed out in reply to patch 24, we don't
> > > > need
> > > > the
> > > > separate environment variable "prior_stage_dtb". I will replace
> > > > it
> > > > with
> > > > "fdtcontroladdr" here and drop patch 24 in the next version.
> > >
> > > Also, can you please enable distro boot? :)
> > >
> > >
> > > Thanks,
> > >
> > > Alex
> >
> > I just had a closer look at distro boot and it's actually quite
> > easy to
> > use. I will update this patch to enable it and will add a bootcmd
> > for
> > virtio block devices (virtio support is currently in u-boot-
> > dm/next).
> >
> > I was looking into testing bootefi on U-Boot and tried to run the
> > hello
> > world and selftest EFI binaries, however I could not get them
> > running.
> > After starting them I immediately get a load access fault. The
> > faulting
> > instruction is at 0xfe77c1fa, which is strange since the binary is
> > loaded to 0x80200000. Do you know what this could be caused by?
>
> I'm not quite sure yet what goes wrong. I tested and verified the
> riscv
> uefi port on andes targets (where at least grub still works), but I
> can
> confirm that the same code just falls apart for me on the qemu
> target.
>
> Any help to debug it down a bit further is much appreciated.
>
I started to narrow it down further. The hello EFI application faults
at the very beginning of its efi_main. The first thing it does is to
print "Hello World". For that, it needs the con_out protocol from the
systable. This is where it goes wrong. con_out is listed to be at
0x17ffd8638, which is above the available system memory. Once it is
accessed, the system throws the load access fault.
So, I think something with the relocation of the systable entries does
not work.
Thanks,
Lukas
> > Also note that I completed the list of exception codes in this
> > patch
> > series. U-Boot master will not indicate this exception occurred.
>
> Ah nice, that will definitely help to debug what's going wrong :).
>
>
> Alex
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-10-30 12:55 ` [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU Lukas Auer
2018-10-30 15:02 ` Auer, Lukas
@ 2018-11-04 14:39 ` Bin Meng
2018-11-04 19:41 ` Auer, Lukas
1 sibling, 1 reply; 56+ messages in thread
From: Bin Meng @ 2018-11-04 14:39 UTC (permalink / raw)
To: u-boot
Hi Lukas,
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> QEMU embeds the location of the kernel image in the device tree. Store
> this address in the environment as variable kernel_start and use it in
> CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed by the
> prior boot stage to boot Linux.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Rebase onto u-boot-dm/next
> - Boot Linux with the device tree provided by the prior boot stage
>
> board/emulation/qemu-riscv/Kconfig | 1 +
> board/emulation/qemu-riscv/qemu-riscv.c | 29 +++++++++++++++++++++++++
> configs/qemu-riscv32_defconfig | 1 +
> configs/qemu-riscv64_defconfig | 1 +
> include/configs/qemu-riscv.h | 10 ++++++++-
> 5 files changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
> index 37a80db6a9..be5839b7db 100644
> --- a/board/emulation/qemu-riscv/Kconfig
> +++ b/board/emulation/qemu-riscv/Kconfig
> @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> imply CMD_EXT2
> imply CMD_EXT4
> imply CMD_FAT
> + imply BOARD_LATE_INIT
>
> endif
> diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
> index 2ce093e19a..ee20983095 100644
> --- a/board/emulation/qemu-riscv/qemu-riscv.c
> +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> @@ -19,3 +19,32 @@ int board_init(void)
>
> return 0;
> }
> +
> +int board_late_init(void)
> +{
> + ulong kernel_start;
> + ofnode chosen_node;
> + int ret;
> +
> + chosen_node = ofnode_path("/chosen");
> + if (!ofnode_valid(chosen_node)) {
> + printf("No chosen node found\n");
> + return 0;
> + }
> +
> +#ifdef CONFIG_ARCH_RV64I
> + ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
> + (u64 *)&kernel_start);
> +#else
> + ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
> + (u32 *)&kernel_start);
> +#endif
> + if (ret) {
> + printf("Can't find kernel start address in device tree\n");
I think we need use 'debug' instead of 'printf' here, for situation
that kernel is not passed to QEMU.
> + return 0;
> + }
> +
> + env_set_hex("kernel_start", kernel_start);
> +
> + return 0;
> +}
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-11-04 14:39 ` Bin Meng
@ 2018-11-04 19:41 ` Auer, Lukas
0 siblings, 0 replies; 56+ messages in thread
From: Auer, Lukas @ 2018-11-04 19:41 UTC (permalink / raw)
To: u-boot
Hi Bin,
On Sun, 2018-11-04 at 22:39 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
> <lukas.auer@aisec.fraunhofer.de> wrote:
> >
> > QEMU embeds the location of the kernel image in the device tree.
> > Store
> > this address in the environment as variable kernel_start and use it
> > in
> > CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed
> > by the
> > prior boot stage to boot Linux.
> >
> > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > ---
> >
> > Changes in v2:
> > - Rebase onto u-boot-dm/next
> > - Boot Linux with the device tree provided by the prior boot stage
> >
> > board/emulation/qemu-riscv/Kconfig | 1 +
> > board/emulation/qemu-riscv/qemu-riscv.c | 29
> > +++++++++++++++++++++++++
> > configs/qemu-riscv32_defconfig | 1 +
> > configs/qemu-riscv64_defconfig | 1 +
> > include/configs/qemu-riscv.h | 10 ++++++++-
> > 5 files changed, 41 insertions(+), 1 deletion(-)
> >
> > diff --git a/board/emulation/qemu-riscv/Kconfig
> > b/board/emulation/qemu-riscv/Kconfig
> > index 37a80db6a9..be5839b7db 100644
> > --- a/board/emulation/qemu-riscv/Kconfig
> > +++ b/board/emulation/qemu-riscv/Kconfig
> > @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > imply CMD_EXT2
> > imply CMD_EXT4
> > imply CMD_FAT
> > + imply BOARD_LATE_INIT
> >
> > endif
> > diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
> > b/board/emulation/qemu-riscv/qemu-riscv.c
> > index 2ce093e19a..ee20983095 100644
> > --- a/board/emulation/qemu-riscv/qemu-riscv.c
> > +++ b/board/emulation/qemu-riscv/qemu-riscv.c
> > @@ -19,3 +19,32 @@ int board_init(void)
> >
> > return 0;
> > }
> > +
> > +int board_late_init(void)
> > +{
> > + ulong kernel_start;
> > + ofnode chosen_node;
> > + int ret;
> > +
> > + chosen_node = ofnode_path("/chosen");
> > + if (!ofnode_valid(chosen_node)) {
> > + printf("No chosen node found\n");
> > + return 0;
> > + }
> > +
> > +#ifdef CONFIG_ARCH_RV64I
> > + ret = ofnode_read_u64(chosen_node, "riscv,kernel-start",
> > + (u64 *)&kernel_start);
> > +#else
> > + ret = ofnode_read_u32(chosen_node, "riscv,kernel-start",
> > + (u32 *)&kernel_start);
> > +#endif
> > + if (ret) {
> > + printf("Can't find kernel start address in device
> > tree\n");
>
> I think we need use 'debug' instead of 'printf' here, for situation
> that kernel is not passed to QEMU.
>
Yes, you are right. What is the current best-practice here? Should I
use one of the pr_* functions or just debug?
Looking at the function, I am also not sure how useful the printf above
is (no chosen node found). I could replace it with the same text as in
the last printf. What do you think?
Thanks,
Lukas
> > + return 0;
> > + }
> > +
> > + env_set_hex("kernel_start", kernel_start);
> > +
> > + return 0;
> > +}
>
> [snip]
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU
2018-11-04 12:52 ` Auer, Lukas
@ 2018-11-04 21:19 ` Alexander Graf
0 siblings, 0 replies; 56+ messages in thread
From: Alexander Graf @ 2018-11-04 21:19 UTC (permalink / raw)
To: u-boot
On 04.11.18 13:52, Auer, Lukas wrote:
> On Sat, 2018-11-03 at 20:33 +0100, Alexander Graf wrote:
>>
>> On 03.11.18 18:07, Auer, Lukas wrote:
>>> On Tue, 2018-10-30 at 16:27 +0100, Alexander Graf wrote:
>>>>
>>>> On 30.10.18 16:02, Auer, Lukas wrote:
>>>>> On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
>>>>>> QEMU embeds the location of the kernel image in the device
>>>>>> tree.
>>>>>> Store
>>>>>> this address in the environment as variable kernel_start and
>>>>>> use
>>>>>> it
>>>>>> in
>>>>>> CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree
>>>>>> passed
>>>>>> by
>>>>>> the
>>>>>> prior boot stage to boot Linux.
>>>>>>
>>>>>> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
>>>>>> ---
>>>>>>
>>>>>> Changes in v2:
>>>>>> - Rebase onto u-boot-dm/next
>>>>>> - Boot Linux with the device tree provided by the prior boot
>>>>>> stage
>>>>>>
>>>>>> board/emulation/qemu-riscv/Kconfig | 1 +
>>>>>> board/emulation/qemu-riscv/qemu-riscv.c | 29
>>>>>> +++++++++++++++++++++++++
>>>>>> configs/qemu-riscv32_defconfig | 1 +
>>>>>> configs/qemu-riscv64_defconfig | 1 +
>>>>>> include/configs/qemu-riscv.h | 10 ++++++++-
>>>>>> 5 files changed, 41 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/board/emulation/qemu-riscv/Kconfig
>>>>>> b/board/emulation/qemu-riscv/Kconfig
>>>>>> index 37a80db6a9..be5839b7db 100644
>>>>>> --- a/board/emulation/qemu-riscv/Kconfig
>>>>>> +++ b/board/emulation/qemu-riscv/Kconfig
>>>>>> @@ -29,5 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>>>>>> imply CMD_EXT2
>>>>>> imply CMD_EXT4
>>>>>> imply CMD_FAT
>>>>>> + imply BOARD_LATE_INIT
>>>>>>
>>>>>> endif
>>>>>> diff --git a/board/emulation/qemu-riscv/qemu-riscv.c
>>>>>> b/board/emulation/qemu-riscv/qemu-riscv.c
>>>>>> index 2ce093e19a..ee20983095 100644
>>>>>> --- a/board/emulation/qemu-riscv/qemu-riscv.c
>>>>>> +++ b/board/emulation/qemu-riscv/qemu-riscv.c
>>>>>> @@ -19,3 +19,32 @@ int board_init(void)
>>>>>>
>>>>>> return 0;
>>>>>> }
>>>>>> +
>>>>>> +int board_late_init(void)
>>>>>> +{
>>>>>> + ulong kernel_start;
>>>>>> + ofnode chosen_node;
>>>>>> + int ret;
>>>>>> +
>>>>>> + chosen_node = ofnode_path("/chosen");
>>>>>> + if (!ofnode_valid(chosen_node)) {
>>>>>> + printf("No chosen node found\n");
>>>>>> + return 0;
>>>>>> + }
>>>>>> +
>>>>>> +#ifdef CONFIG_ARCH_RV64I
>>>>>> + ret = ofnode_read_u64(chosen_node, "riscv,kernel-
>>>>>> start",
>>>>>> + (u64 *)&kernel_start);
>>>>>> +#else
>>>>>> + ret = ofnode_read_u32(chosen_node, "riscv,kernel-
>>>>>> start",
>>>>>> + (u32 *)&kernel_start);
>>>>>> +#endif
>>>>>> + if (ret) {
>>>>>> + printf("Can't find kernel start address in
>>>>>> device
>>>>>> tree\n");
>>>>>> + return 0;
>>>>>> + }
>>>>>> +
>>>>>> + env_set_hex("kernel_start", kernel_start);
>>>>>> +
>>>>>> + return 0;
>>>>>> +}
>>>>>> diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-
>>>>>> riscv32_defconfig
>>>>>> index b55644378a..13dd53a550 100644
>>>>>> --- a/configs/qemu-riscv32_defconfig
>>>>>> +++ b/configs/qemu-riscv32_defconfig
>>>>>> @@ -4,4 +4,5 @@ CONFIG_NR_DRAM_BANKS=1
>>>>>> CONFIG_FIT=y
>>>>>> CONFIG_DISPLAY_CPUINFO=y
>>>>>> CONFIG_DISPLAY_BOARDINFO=y
>>>>>> +CONFIG_HUSH_PARSER=y
>>>>>> CONFIG_OF_PRIOR_STAGE=y
>>>>>> diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-
>>>>>> riscv64_defconfig
>>>>>> index a542ac4893..06eb3042fa 100644
>>>>>> --- a/configs/qemu-riscv64_defconfig
>>>>>> +++ b/configs/qemu-riscv64_defconfig
>>>>>> @@ -5,4 +5,5 @@ CONFIG_NR_DRAM_BANKS=1
>>>>>> CONFIG_FIT=y
>>>>>> CONFIG_DISPLAY_CPUINFO=y
>>>>>> CONFIG_DISPLAY_BOARDINFO=y
>>>>>> +CONFIG_HUSH_PARSER=y
>>>>>> CONFIG_OF_PRIOR_STAGE=y
>>>>>> diff --git a/include/configs/qemu-riscv.h
>>>>>> b/include/configs/qemu-
>>>>>> riscv.h
>>>>>> index ba6a18f2e6..7c88ba300a 100644
>>>>>> --- a/include/configs/qemu-riscv.h
>>>>>> +++ b/include/configs/qemu-riscv.h
>>>>>> @@ -21,7 +21,15 @@
>>>>>> #define CONFIG_ENV_SIZE SZ_4K
>>>>>>
>>>>>> #define CONFIG_EXTRA_ENV_SETTINGS \
>>>>>> - "fdt_high=0xffffffffffffffff\0" \
>>>>>> + "fdt_high=0x82000000\0" \
>>>>>> + "bootm_size=0x10000000\0" \
>>>>>> "initrd_high=0xffffffffffffffff\0"
>>>>>>
>>>>>> +#define CONFIG_BOOTCOMMAND \
>>>>>> + "if env exists kernel_start; then " \
>>>>>> + "bootm ${kernel_start} - ${prior_stage_dtb};" \
>>>>>
>>>>> As Alexander Graf pointed out in reply to patch 24, we don't
>>>>> need
>>>>> the
>>>>> separate environment variable "prior_stage_dtb". I will replace
>>>>> it
>>>>> with
>>>>> "fdtcontroladdr" here and drop patch 24 in the next version.
>>>>
>>>> Also, can you please enable distro boot? :)
>>>>
>>>>
>>>> Thanks,
>>>>
>>>> Alex
>>>
>>> I just had a closer look at distro boot and it's actually quite
>>> easy to
>>> use. I will update this patch to enable it and will add a bootcmd
>>> for
>>> virtio block devices (virtio support is currently in u-boot-
>>> dm/next).
>>>
>>> I was looking into testing bootefi on U-Boot and tried to run the
>>> hello
>>> world and selftest EFI binaries, however I could not get them
>>> running.
>>> After starting them I immediately get a load access fault. The
>>> faulting
>>> instruction is at 0xfe77c1fa, which is strange since the binary is
>>> loaded to 0x80200000. Do you know what this could be caused by?
>>
>> I'm not quite sure yet what goes wrong. I tested and verified the
>> riscv
>> uefi port on andes targets (where at least grub still works), but I
>> can
>> confirm that the same code just falls apart for me on the qemu
>> target.
>>
>> Any help to debug it down a bit further is much appreciated.
>>
>
> I started to narrow it down further. The hello EFI application faults
> at the very beginning of its efi_main. The first thing it does is to
> print "Hello World". For that, it needs the con_out protocol from the
> systable. This is where it goes wrong. con_out is listed to be at
> 0x17ffd8638, which is above the available system memory. Once it is
> accessed, the system throws the load access fault.
> So, I think something with the relocation of the systable entries does
> not work.
Thanks for digging it to that. Relocations for runtime code are broken
(efi_runtime_relocate()). The R_ABSOLUTE path doesn't properly handle
dynsyms.
Alex
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model
2018-10-31 15:01 ` Auer, Lukas
@ 2018-11-13 7:34 ` Bin Meng
2018-11-13 10:20 ` Auer, Lukas
0 siblings, 1 reply; 56+ messages in thread
From: Bin Meng @ 2018-11-13 7:34 UTC (permalink / raw)
To: u-boot
Hi Lukas,
On Wed, Oct 31, 2018 at 11:01 PM Auer, Lukas
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Hi Bin,
>
> On Wed, 2018-10-31 at 10:13 +0800, Bin Meng wrote:
> > Hi Lukas,
> >
> > On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
> > <lukas.auer@aisec.fraunhofer.de> wrote:
> > >
> > > RISC-V has two code models, medium low (medlow) and medium any
> > > (medany).
> > > Medlow limits addressable memory to a single 2 GiB range between
> > > the
> > > absolute addresses -2 GiB and +2 GiB. Medany limits addressable
> > > memory
> > > to any single 2 GiB address range.
> > > By default, medlow is selected on 32-bit systems and medany on 64-
> > > bit
> > > systems. This matches the configuration in Linux.
> > >
> > > The -mcmodel compiler flag is selected according to the Kconfig
> > > configuration.
> > >
> > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > ---
> > >
> > > Changes in v2:
> > > - Change ISA string construction, as suggested by Bin Meng
> > >
> > > arch/riscv/Kconfig | 19 +++++++++++++++++++
> > > arch/riscv/Makefile | 9 ++++++++-
> > > 2 files changed, 27 insertions(+), 1 deletion(-)
> > >
> >
> > I had a further look at this, and I suspect we should stick to medlow
> > for U-Boot, even for 64-bit. As U-Boot will be only running within
> > the
> > low 4GB memory space even for 64-bit. Adding medany seems
> > unnecessary.
> >
> > Regards,
> > Bin
>
> You are right, however I think it's actually because U-Boot is compiled
> as a position independent binary. U-Boot can be relocated above what's
> addressable with 32-bit if the memory is large enough. This should
> cause issues with medlow.
> I suspects that's the reason, but I am not entirely sure. What do you
> think?
Sorry I missed this email. I just found in your v3 this patch was
dropped. I think this is still needed to explicitly pass the code
model to the compiler. I believe we only need change to:
+choice
+ prompt "Code Model"
+ default CMODEL_MEDLOW
I can include the modified patch in my upcoming series.
Regards,
Bin
^ permalink raw reply [flat|nested] 56+ messages in thread
* [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model
2018-11-13 7:34 ` Bin Meng
@ 2018-11-13 10:20 ` Auer, Lukas
0 siblings, 0 replies; 56+ messages in thread
From: Auer, Lukas @ 2018-11-13 10:20 UTC (permalink / raw)
To: u-boot
Hi Bin,
On Tue, 2018-11-13 at 15:34 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Oct 31, 2018 at 11:01 PM Auer, Lukas
> <lukas.auer@aisec.fraunhofer.de> wrote:
> >
> > Hi Bin,
> >
> > On Wed, 2018-10-31 at 10:13 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> > > On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
> > > <lukas.auer@aisec.fraunhofer.de> wrote:
> > > >
> > > > RISC-V has two code models, medium low (medlow) and medium any
> > > > (medany).
> > > > Medlow limits addressable memory to a single 2 GiB range
> > > > between
> > > > the
> > > > absolute addresses -2 GiB and +2 GiB. Medany limits addressable
> > > > memory
> > > > to any single 2 GiB address range.
> > > > By default, medlow is selected on 32-bit systems and medany on
> > > > 64-
> > > > bit
> > > > systems. This matches the configuration in Linux.
> > > >
> > > > The -mcmodel compiler flag is selected according to the Kconfig
> > > > configuration.
> > > >
> > > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > > ---
> > > >
> > > > Changes in v2:
> > > > - Change ISA string construction, as suggested by Bin Meng
> > > >
> > > > arch/riscv/Kconfig | 19 +++++++++++++++++++
> > > > arch/riscv/Makefile | 9 ++++++++-
> > > > 2 files changed, 27 insertions(+), 1 deletion(-)
> > > >
> > >
> > > I had a further look at this, and I suspect we should stick to
> > > medlow
> > > for U-Boot, even for 64-bit. As U-Boot will be only running
> > > within
> > > the
> > > low 4GB memory space even for 64-bit. Adding medany seems
> > > unnecessary.
> > >
> > > Regards,
> > > Bin
> >
> > You are right, however I think it's actually because U-Boot is
> > compiled
> > as a position independent binary. U-Boot can be relocated above
> > what's
> > addressable with 32-bit if the memory is large enough. This should
> > cause issues with medlow.
> > I suspects that's the reason, but I am not entirely sure. What do
> > you
> > think?
>
> Sorry I missed this email. I just found in your v3 this patch was
> dropped. I think this is still needed to explicitly pass the code
> model to the compiler. I believe we only need change to:
>
> +choice
> + prompt "Code Model"
> + default CMODEL_MEDLOW
>
> I can include the modified patch in my upcoming series.
>
> Regards,
> Bin
Ok, I miss-understood that. Sounds good, thanks!
Lukas
^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2018-11-13 10:20 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-30 12:55 [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 01/29] tools: .gitignore: add prelink-riscv Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 02/29] dts: riscv: update makefile to also clean the RISC-V dts directory Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 03/29] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 04/29] riscv: select CONFIG_PHYS_64BIT on RV64I systems Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 05/29] riscv: add Kconfig entries for the C and A ISA extensions Lukas Auer
2018-10-31 2:13 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 06/29] riscv: set -march and -mabi based on the Kconfig configuration Lukas Auer
2018-10-31 2:13 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model Lukas Auer
2018-10-31 2:13 ` Bin Meng
2018-10-31 15:01 ` Auer, Lukas
2018-11-13 7:34 ` Bin Meng
2018-11-13 10:20 ` Auer, Lukas
2018-10-30 12:55 ` [U-Boot] [PATCH v2 08/29] riscv: enable -fdata-sections Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 09/29] riscv: fix use of incorrectly sized variables Lukas Auer
2018-10-31 2:13 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 10/29] riscv: make use of the barrier functions from Linux Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 11/29] riscv: do not reimplement generic io functions Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 12/29] riscv: complete the list of exception codes Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 13/29] riscv: treat undefined exception codes as reserved Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 14/29] riscv: hang on unhandled exceptions Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 15/29] riscv: implement the invalidate_icache_* functions Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 16/29] riscv: invalidate the instruction cache before jumping to Linux Lukas Auer
2018-10-31 2:14 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A3ECAA@ATCPCS16.andestech.com>
2018-11-01 4:23 ` Rick Chen
2018-10-30 12:55 ` [U-Boot] [PATCH v2 17/29] riscv: fix inconsistent use of spaces and tabs in start.S Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 18/29] riscv: align mtvec on a 4-byte boundary Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 19/29] Drop CONFIG_INIT_CRITICAL Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 20/29] riscv: remove unused labels in start.S Lukas Auer
2018-10-31 2:14 ` Bin Meng
2018-10-30 12:55 ` [U-Boot] [PATCH v2 21/29] riscv: do not blindly modify the mstatus CSR Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 22/29] riscv: save hart ID and device tree passed by prior boot stage Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 23/29] riscv: qemu: use " Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 24/29] riscv: store device tree passed by prior boot stage in environment Lukas Auer
2018-10-30 13:19 ` Alexander Graf
2018-10-30 13:44 ` Auer, Lukas
2018-10-30 13:53 ` Alexander Graf
2018-10-30 14:51 ` Auer, Lukas
2018-10-30 12:55 ` [U-Boot] [PATCH v2 25/29] riscv: qemu: support booting Linux Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 26/29] riscv: align bootm implementation with that of other architectures Lukas Auer
2018-10-30 12:55 ` [U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64 Lukas Auer
2018-10-31 2:14 ` Bin Meng
2018-11-03 6:08 ` Simon Glass
2018-10-30 12:55 ` [U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU Lukas Auer
2018-10-30 15:02 ` Auer, Lukas
2018-10-30 15:27 ` Alexander Graf
2018-10-30 17:13 ` Auer, Lukas
2018-11-03 17:07 ` Auer, Lukas
2018-11-03 19:33 ` Alexander Graf
2018-11-04 12:52 ` Auer, Lukas
2018-11-04 21:19 ` Alexander Graf
2018-11-04 14:39 ` Bin Meng
2018-11-04 19:41 ` Auer, Lukas
2018-10-30 12:55 ` [U-Boot] [PATCH v2 29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL Lukas Auer
2018-10-31 2:14 ` Bin Meng
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