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From: BALATON Zoltan <balaton@eik.bme.hu>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org,
	 Daniel Henrique Barboza <danielhb413@gmail.com>,
	 Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together
Date: Sun, 18 Sep 2022 23:24:31 +0200 (CEST)	[thread overview]
Message-ID: <f933fad5-26b4-7e68-a4b0-a1b07014da1a@eik.bme.hu> (raw)
In-Reply-To: <8495fbef-7eda-fea5-1cf2-60dcb0a50dc4@amsat.org>

[-- Attachment #1: Type: text/plain, Size: 2054 bytes --]

On Sun, 18 Sep 2022, Philippe Mathieu-Daudé wrote:
> Hi Zoltan,
>
> On 18/9/22 22:24, BALATON Zoltan wrote:
>> Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
>> called ppc4xx_sdram to separate from other device models and put them
>> in one place allowing sharing some code between them.
>> 
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>>   hw/ppc/meson.build      |   3 +-
>>   hw/ppc/ppc440_uc.c      | 332 -----------------
>>   hw/ppc/ppc4xx_devs.c    | 414 ---------------------
>>   hw/ppc/ppc4xx_sdram.c   | 771 ++++++++++++++++++++++++++++++++++++++++
>>   include/hw/ppc/ppc4xx.h |  24 +-
>>   5 files changed, 785 insertions(+), 759 deletions(-)
>
> This seems a proper cleanup, but even using `git-diff 
> --color-moved=dimmed-zebra` I'm having hard time reviewing this single
> patch.
> Looking at the changes in the ppc4xx_sdram_types[] array, it
> seems we can be move one model at a time, right?

I could try to break this patch up some more if absolutely necessary but 
I've already spent a lot of time rebasing this series as every little 
change in earlier patch leads to conflicts later then patches get squashed 
during rebase and I have to redo it again to separate them. So if you 
can't review it looking at it some more I could try a v6 but don't want if 
can be avoided. I'll wait for Cédric's comments too in any case to only do 
as many respins as needed.

Regards,
BALATON Zoltan

> [...]
>> +static const TypeInfo ppc4xx_sdram_types[] = {
>> +    {
>> +        .name           = TYPE_PPC4xx_SDRAM_DDR,
>> +        .parent         = TYPE_PPC4xx_DCR_DEVICE,
>> +        .instance_size  = sizeof(Ppc4xxSdramDdrState),
>> +        .class_init     = ppc4xx_sdram_ddr_class_init,
>> +    }, {
>> +        .name           = TYPE_PPC4xx_SDRAM_DDR2,
>> +        .parent         = TYPE_PPC4xx_DCR_DEVICE,
>> +        .instance_size  = sizeof(Ppc4xxSdramDdr2State),
>> +        .class_init     = ppc4xx_sdram_ddr2_class_init,
>> +    }
>> +};
>> +
>> +DEFINE_TYPES(ppc4xx_sdram_types)
> [...]
>
>

  reply	other threads:[~2022-09-18 21:25 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 01/21] ppc440_bamboo: Remove unnecessary memsets BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 02/21] ppc4xx: Introduce Ppc4xxSdramBank struct BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 03/21] ppc4xx_sdram: Get rid of the init RAM hack BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 04/21] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 05/21] ppc440_bamboo: Add missing 4 MiB valid memory size BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 07/21] ppc4xx_sdram: QOM'ify BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 08/21] ppc4xx_sdram: Drop extra zeros for readability BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse BALATON Zoltan
2022-09-18 20:35   ` Philippe Mathieu-Daudé via
2022-09-18 20:24 ` [PATCH v5 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 11/21] ppc440_sdram: Get rid of the init RAM hack BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 12/21] ppc440_sdram: Rename local variable for readability BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 13/21] ppc4xx_sdram: Rename functions to prevent name clashes BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 15/21] ppc440_sdram: QOM'ify BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together BALATON Zoltan
2022-09-18 21:02   ` Philippe Mathieu-Daudé via
2022-09-18 21:24     ` BALATON Zoltan [this message]
2022-09-18 21:36       ` Philippe Mathieu-Daudé via
2022-09-18 20:24 ` [PATCH v5 17/21] ppc4xx_sdram: Use hwaddr for memory bank size BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 18/21] ppc4xx_sdram: Rename local state variable for brevity BALATON Zoltan
2022-09-18 20:51   ` Philippe Mathieu-Daudé via
2022-09-18 20:24 ` [PATCH v5 19/21] ppc4xx_sdram: Generalise bank setup BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 20/21] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks() BALATON Zoltan
2022-09-18 20:33 ` [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups Philippe Mathieu-Daudé via

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