* [PATCH v1 01/23] phy: marvell: add comphy type PHY_TYPE_USB3
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX Stefan Roese
` (22 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: jinghua <jinghua@marvell.com>
- For some Marvell SoCs, like armada-3700, there are both
USB host and device controller, but on PHY level the
configuration is the same.
- The new type supports both USB device and USB host
- This patch is cherry-picked from u-boot-2015 as-is.
Signed-off-by: jinghua <jinghua@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_core.c | 2 +-
include/dt-bindings/comphy/comphy_data.h | 25 ++++++++++++------------
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index cd54e7f88907..cffceb1395bb 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -40,7 +40,7 @@ static const char *get_type_string(u32 type)
static const char * const type_strings[] = {
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
"SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
- "SGMII1", "SGMII2", "SGMII3", "QSGMII",
+ "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3"
"USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
"XAUI0", "XAUI1", "XAUI2", "XAUI3",
"RXAUI0", "RXAUI1", "SFI", "IGNORE"
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
index 4f7e2821b8ee..08544fa758bf 100644
--- a/include/dt-bindings/comphy/comphy_data.h
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -33,18 +33,19 @@
#define PHY_TYPE_SGMII2 11
#define PHY_TYPE_SGMII3 12
#define PHY_TYPE_QSGMII 13
-#define PHY_TYPE_USB3_HOST0 14
-#define PHY_TYPE_USB3_HOST1 15
-#define PHY_TYPE_USB3_DEVICE 16
-#define PHY_TYPE_XAUI0 17
-#define PHY_TYPE_XAUI1 18
-#define PHY_TYPE_XAUI2 19
-#define PHY_TYPE_XAUI3 20
-#define PHY_TYPE_RXAUI0 21
-#define PHY_TYPE_RXAUI1 22
-#define PHY_TYPE_SFI 23
-#define PHY_TYPE_IGNORE 24
-#define PHY_TYPE_MAX 25
+#define PHY_TYPE_USB3 14
+#define PHY_TYPE_USB3_HOST0 15
+#define PHY_TYPE_USB3_HOST1 16
+#define PHY_TYPE_USB3_DEVICE 17
+#define PHY_TYPE_XAUI0 18
+#define PHY_TYPE_XAUI1 19
+#define PHY_TYPE_XAUI2 20
+#define PHY_TYPE_XAUI3 21
+#define PHY_TYPE_RXAUI0 22
+#define PHY_TYPE_RXAUI1 23
+#define PHY_TYPE_SFI 24
+#define PHY_TYPE_IGNORE 25
+#define PHY_TYPE_MAX 26
#define PHY_TYPE_INVALID 0xff
#define PHY_POLARITY_NO_INVERT 0
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
2021-03-24 14:06 ` [PATCH v1 01/23] phy: marvell: add comphy type PHY_TYPE_USB3 Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:42 ` Pali Rohár
2021-03-24 14:06 ` [PATCH v1 03/23] phy: marvell: add missing speed during info prints Stefan Roese
` (21 subsequent siblings)
23 siblings, 1 reply; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX.
Those definition might be confused with MDIO PHY definitions.
This patch does the following changes:
- PHY_TYPE_XX --> COMPHY_TYPE_XX
- PHY_SPEED_XX --> COMPHY_SPEED_XX
This improves readability, no functional change.
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/arm/dts/armada-3720-db.dts | 8 +-
arch/arm/dts/armada-3720-espressobin.dts | 12 +-
arch/arm/dts/armada-3720-turris-mox.dts | 12 +-
arch/arm/dts/armada-3720-uDPU.dts | 23 ++--
arch/arm/dts/armada-7040-db-nand.dts | 24 ++--
arch/arm/dts/armada-7040-db.dts | 22 ++--
arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 30 ++---
arch/arm/dts/armada-8040-db.dts | 24 ++--
arch/arm/dts/armada-8040-mcbin.dts | 27 +++--
arch/arm/dts/armada-8040-puzzle-m801.dts | 32 ++---
arch/arm/dts/cn9130-crb-A.dts | 16 +--
arch/arm/dts/cn9130-crb-B.dts | 16 +--
board/CZ.NIC/turris_mox/turris_mox.c | 8 +-
drivers/phy/marvell/comphy_a3700.c | 70 +++++------
drivers/phy/marvell/comphy_core.c | 14 +--
drivers/phy/marvell/comphy_cp110.c | 124 +++++++++++---------
drivers/phy/marvell/comphy_mux.c | 10 +-
include/dt-bindings/comphy/comphy_data.h | 90 +++++++-------
18 files changed, 288 insertions(+), 274 deletions(-)
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 1b1b66b94de6..fd1892ac8106 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -70,13 +70,13 @@
&comphy {
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_2_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_2_5G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
index 96a4b3d95b88..3cea5218d2b3 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -83,18 +83,18 @@
&comphy {
max-lanes = <3>;
phy0 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_2_5G>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_2_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SATA0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts
index 974270cc8c68..8e0ebf508d44 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -73,18 +73,18 @@
&comphy {
max-lanes = <3>;
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts
index 7f4b8222f4af..4b30f3cea8c7 100644
--- a/arch/arm/dts/armada-3720-uDPU.dts
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -108,18 +108,19 @@
&comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_SGMII0>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
- phy1 {
- phy-type = <PHY_TYPE_SGMII0>;
- phy-speed = <PHY_SPEED_3_125G>;
- };
-
- phy2 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
- };
};
ð0 {
diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts
index f249c71f6561..ccf470b317f1 100644
--- a/arch/arm/dts/armada-7040-db-nand.dts
+++ b/arch/arm/dts/armada-7040-db-nand.dts
@@ -129,33 +129,33 @@
&cp0_comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SGMII0>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII0>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX2>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index 6037f12f0e9f..f475fb361071 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -122,32 +122,32 @@
&cp0_comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX2>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index 86df6ac0b202..ce5832c2fbd7 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -160,22 +160,22 @@
* Lane 5: Not connected
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI>;
};
phy3 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy5 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
};
@@ -272,25 +272,25 @@
* Lane 5: SGMII2 - Connected to Topaz switch
*/
phy0 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-invert = <PHY_POLARITY_RXD_INVERT>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-invert = <COMPHY_POLARITY_RXD_INVERT>;
};
phy1 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
};
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index a2b7c992a406..1edfaab682eb 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -89,22 +89,22 @@
* Lane 5: PCIe2 (x1)
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
+ phy-type = <COMPHY_TYPE_PEX2>;
};
};
@@ -188,22 +188,22 @@
* Lane 5: PCIe2 (x1)
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_PEX1>;
+ phy-type = <COMPHY_TYPE_PEX1>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
+ phy-type = <COMPHY_TYPE_PEX2>;
};
};
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index b0a36e328bc9..98a582df26fe 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -171,22 +171,22 @@
* Lane 5: SATA1
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy3 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI>;
};
phy5 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
};
@@ -286,22 +286,23 @@
* Lane 5: SGMII3
*/
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII3>;
+ phy-type = <COMPHY_TYPE_SGMII3>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
};
diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts
index ff46ce50cbc7..0becc4ff0d34 100644
--- a/arch/arm/dts/armada-8040-puzzle-m801.dts
+++ b/arch/arm/dts/armada-8040-puzzle-m801.dts
@@ -220,24 +220,24 @@
* Lane 5: SATA1
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy2 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI>;
};
phy5 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
};
@@ -367,23 +367,23 @@
* Lane 5: SGMII2
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
};
diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts
index fa21ef314cba..5c5e0fb2eb1e 100644
--- a/arch/arm/dts/cn9130-crb-A.dts
+++ b/arch/arm/dts/cn9130-crb-A.dts
@@ -15,29 +15,29 @@
&cp0_comphy {
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy3 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
- phy-speed = <PHY_SPEED_10_3125G>;
+ phy-type = <COMPHY_TYPE_SFI>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
};
diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts
index 7cb587ada826..6041084a2c87 100644
--- a/arch/arm/dts/cn9130-crb-B.dts
+++ b/arch/arm/dts/cn9130-crb-B.dts
@@ -15,29 +15,29 @@
&cp0_comphy {
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy2 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy3 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
- phy-speed = <PHY_SPEED_10_3125G>;
+ phy-type = <COMPHY_TYPE_SFI>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
};
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index 486680a49e88..15cbf92550e6 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -216,13 +216,13 @@ int comphy_update_map(struct comphy_map *serdes_map, int count)
if (sfpindex >= 0 && swindex >= 0) {
if (sfpindex < swindex)
- serdes_map[0].speed = PHY_SPEED_1_25G;
+ serdes_map[0].speed = COMPHY_SPEED_1_25G;
else
- serdes_map[0].speed = PHY_SPEED_3_125G;
+ serdes_map[0].speed = COMPHY_SPEED_3_125G;
} else if (sfpindex >= 0) {
- serdes_map[0].speed = PHY_SPEED_1_25G;
+ serdes_map[0].speed = COMPHY_SPEED_1_25G;
} else if (swindex >= 0) {
- serdes_map[0].speed = PHY_SPEED_3_125G;
+ serdes_map[0].speed = COMPHY_SPEED_3_125G;
}
return 0;
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 12523d18a805..06822d1d12e0 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -17,33 +17,33 @@
DECLARE_GLOBAL_DATA_PTR;
struct comphy_mux_data a3700_comphy_mux_data[] = {
-/* Lane 0 */
+ /* Lane 0 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0 },
- { PHY_TYPE_SGMII1, 0x0 },
- { PHY_TYPE_USB3_HOST0, 0x1 },
- { PHY_TYPE_USB3_DEVICE, 0x1 }
+ { COMPHY_TYPE_UNCONNECTED, 0x0 },
+ { COMPHY_TYPE_SGMII1, 0x0 },
+ { COMPHY_TYPE_USB3_HOST0, 0x1 },
+ { COMPHY_TYPE_USB3_DEVICE, 0x1 }
}
},
-/* Lane 1 */
+ /* Lane 1 */
{
3,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SGMII0, 0x0},
- { PHY_TYPE_PEX0, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SGMII0, 0x0},
+ { COMPHY_TYPE_PEX0, 0x1}
}
},
-/* Lane 2 */
+ /* Lane 2 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SATA0, 0x0},
- { PHY_TYPE_USB3_HOST0, 0x1},
- { PHY_TYPE_USB3_DEVICE, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SATA0, 0x0},
+ { COMPHY_TYPE_USB3_HOST0, 0x1},
+ { COMPHY_TYPE_USB3_DEVICE, 0x1}
}
},
};
@@ -228,10 +228,10 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
/*
* 10. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -284,10 +284,10 @@ static int comphy_sata_power_up(u32 invert)
/*
* 0. Check the Polarity invert bits
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
data |= bs_txd_inv;
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
data |= bs_rxd_inv;
reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv);
@@ -465,10 +465,10 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
/*
* 9. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
/*
@@ -513,7 +513,7 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
* Set Soft ID for Host mode (Device mode works with Hard ID
* detection)
*/
- if (type == PHY_TYPE_USB3_HOST0) {
+ if (type == COMPHY_TYPE_USB3_HOST0) {
/*
* set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
* clear BIT1: set SOFT_ID = Host
@@ -685,8 +685,8 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed)
* comparison to 3.125 Gbps values. These register values are
* stored in "sgmii_phy_init_fix" array.
*/
- if ((speed != PHY_SPEED_1_25G) &&
- (sgmii_phy_init_fix[fix_idx].addr == addr)) {
+ if (speed != COMPHY_SPEED_1_25G &&
+ sgmii_phy_init_fix[fix_idx].addr == addr) {
/* Use new value */
val = sgmii_phy_init_fix[fix_idx].value;
if (fix_idx < fix_arr_sz)
@@ -737,13 +737,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
* 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
* COMPHY bit rate
*/
- if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
+ if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x8 << rf_gen_rx_sel_shift) |
(0x8 << rf_gen_tx_sel_shift),
rf_gen_rx_select | rf_gen_tx_select);
- } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
+ } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x6 << rf_gen_rx_sel_shift) |
(0x6 << rf_gen_tx_sel_shift),
@@ -819,7 +819,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
* registers are OK.
*/
debug("Running C-DPI phy init %s mode\n",
- speed == PHY_SPEED_3_125G ? "2G5" : "1G");
+ speed == COMPHY_SPEED_3_125G ? "2G5" : "1G");
if (get_ref_clk() == 40)
comphy_sgmii_phy_init(lane, speed);
@@ -837,10 +837,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
/*
* 18. Check the PHY Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -976,30 +976,30 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
comphy_map->type, comphy_map->invert);
switch (comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
+ case COMPHY_TYPE_UNCONNECTED:
continue;
break;
- case PHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX0:
ret = comphy_pcie_power_up(comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_DEVICE:
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_DEVICE:
ret = comphy_usb3_power_up(lane,
comphy_map->type,
comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
ret = comphy_sgmii_power_up(lane, comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA0:
ret = comphy_sata_power_up(comphy_map->invert);
break;
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index cffceb1395bb..f1f061d7c116 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -29,7 +29,7 @@ static const char *get_speed_string(u32 speed)
"6.25 Gbps", "10.31 Gbps"
};
- if (speed < 0 || speed > PHY_SPEED_MAX)
+ if (speed < 0 || speed > COMPHY_SPEED_MAX)
return "invalid";
return speed_strings[speed];
@@ -46,7 +46,7 @@ static const char *get_type_string(u32 type)
"RXAUI0", "RXAUI1", "SFI", "IGNORE"
};
- if (type < 0 || type > PHY_TYPE_MAX)
+ if (type < 0 || type > COMPHY_TYPE_MAX)
return "invalid";
return type_strings[type];
@@ -59,7 +59,7 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg,
for (lane = 0; lane < chip_cfg->comphy_lanes_count;
lane++, comphy_map_data++) {
- if (comphy_map_data->speed == PHY_SPEED_INVALID) {
+ if (comphy_map_data->speed == COMPHY_SPEED_INVALID) {
printf("Comphy-%d: %-13s\n", lane,
get_type_string(comphy_map_data->type));
} else {
@@ -136,16 +136,16 @@ static int comphy_probe(struct udevice *dev)
continue;
comphy_map_data[lane].speed = fdtdec_get_int(
- blob, subnode, "phy-speed", PHY_TYPE_INVALID);
+ blob, subnode, "phy-speed", COMPHY_TYPE_INVALID);
comphy_map_data[lane].type = fdtdec_get_int(
- blob, subnode, "phy-type", PHY_SPEED_INVALID);
+ blob, subnode, "phy-type", COMPHY_SPEED_INVALID);
comphy_map_data[lane].invert = fdtdec_get_int(
- blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT);
+ blob, subnode, "phy-invert", COMPHY_POLARITY_NO_INVERT);
comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
"clk-src");
comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode,
"end_point");
- if (comphy_map_data[lane].type == PHY_TYPE_INVALID) {
+ if (comphy_map_data[lane].type == COMPHY_TYPE_INVALID) {
printf("no phy type for lane %d, setting lane as unconnected\n",
lane + 1);
}
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index a323de7c76d0..e4ab90121c74 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -74,35 +74,47 @@ struct utmi_phy_data {
* Eth_port_0 that include (SGMII0, RXAUI0, SFI)
*/
struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
- {PHY_TYPE_SATA1, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
- {PHY_TYPE_SATA0, 0x4} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
- {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
- {PHY_TYPE_SATA0, 0x4} } },
- {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
- {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
- {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
- {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
- {PHY_TYPE_SGMII1, 0x1} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
- {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
+ /* Lane 0 */
+ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1},
+ {COMPHY_TYPE_SATA1, 0x4} } },
+ /* Lane 1 */
+ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
+ {COMPHY_TYPE_SATA0, 0x4} } },
+ /* Lane 2 */
+ {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1},
+ {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1},
+ {COMPHY_TYPE_SATA0, 0x4} } },
+ /* Lane 3 */
+ {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1},
+ {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } },
+ /* Lane 4 */
+ {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2},
+ {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2},
+ {COMPHY_TYPE_SGMII1, 0x1} } },
+ /* Lane 5 */
+ {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
+ {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } },
};
struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
- {PHY_TYPE_PEX0, 0x4} } },
- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
- {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
- {PHY_TYPE_USB3_HOST1, 0x1},
- {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
+ /* Lane 0 */
+ {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX0, 0x4} } },
+ /* Lane 1 */
+ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0},
+ {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_USB3_DEVICE, 0x2},
+ {COMPHY_TYPE_PEX0, 0x4} } },
+ /* Lane 2 */
+ {3, {{COMPHY_TYPE_UNCONNECTED, 0x0},
+ {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } },
+ /* Lane 3 */
+ {3, {{COMPHY_TYPE_UNCONNECTED, 0x0},
+ {COMPHY_TYPE_USB3_HOST1, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } },
+ /* Lane 4 */
+ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0},
+ {COMPHY_TYPE_USB3_HOST1, 0x1},
+ {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PEX1, 0x4} } },
+ /* Lane 5 */
+ {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX2, 0x4} } },
};
static u32 polling_with_timeout(void __iomem *addr, u32 val,
@@ -868,9 +880,9 @@ static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
/* Fix the type after check the PHY and PIPE configuration */
for (lane = 0; lane < comphy_max_count; lane++) {
- if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
- (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
- serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
+ if ((comphy_map_pipe_data[lane].type == COMPHY_TYPE_UNCONNECTED) &&
+ (comphy_map_phy_data[lane].type == COMPHY_TYPE_UNCONNECTED))
+ serdes_map[lane].type = COMPHY_TYPE_UNCONNECTED;
}
}
@@ -895,7 +907,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
/* Check if the first 4 lanes configured as By-4 */
for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
lane++, ptr_comphy_map++) {
- if (ptr_comphy_map->type != PHY_TYPE_PEX0)
+ if (ptr_comphy_map->type != COMPHY_TYPE_PEX0)
break;
pcie_width++;
}
@@ -912,14 +924,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
pcie_width = 1;
}
switch (ptr_comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
- case PHY_TYPE_IGNORE:
+ case COMPHY_TYPE_UNCONNECTED:
+ case COMPHY_TYPE_IGNORE:
continue;
break;
- case PHY_TYPE_PEX0:
- case PHY_TYPE_PEX1:
- case PHY_TYPE_PEX2:
- case PHY_TYPE_PEX3:
+ case COMPHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX1:
+ case COMPHY_TYPE_PEX2:
+ case COMPHY_TYPE_PEX3:
mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
ptr_comphy_map->clk_src,
COMPHY_PCIE_MODE,
@@ -928,30 +940,30 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SATA0:
- case PHY_TYPE_SATA1:
- case PHY_TYPE_SATA2:
- case PHY_TYPE_SATA3:
+ case COMPHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA1:
+ case COMPHY_TYPE_SATA2:
+ case COMPHY_TYPE_SATA3:
mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
ret = comphy_sata_power_up(lane, hpipe_base_addr,
comphy_base_addr,
ptr_chip_cfg->cp_index,
mode);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_HOST1:
- case PHY_TYPE_USB3_DEVICE:
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_HOST1:
+ case COMPHY_TYPE_USB3_DEVICE:
ret = comphy_usb3_power_up(lane, hpipe_base_addr,
comphy_base_addr);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
+ if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
debug("Warning: ");
debug("SGMII PHY speed in lane %d is invalid,",
lane);
debug(" set PHY speed to 1.25G\n");
- ptr_comphy_map->speed = PHY_SPEED_1_25G;
+ ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
}
/*
@@ -965,12 +977,12 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SGMII2:
- case PHY_TYPE_SGMII3:
- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
+ case COMPHY_TYPE_SGMII2:
+ case COMPHY_TYPE_SGMII3:
+ if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
lane);
- ptr_comphy_map->speed = PHY_SPEED_1_25G;
+ ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
}
mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
@@ -980,7 +992,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SFI:
+ case COMPHY_TYPE_SFI:
mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
COMPHY_UNIT_ID0,
ptr_comphy_map->speed);
@@ -988,8 +1000,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_RXAUI0:
- case PHY_TYPE_RXAUI1:
+ case COMPHY_TYPE_RXAUI0:
+ case COMPHY_TYPE_RXAUI1:
ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
comphy_base_addr);
break;
@@ -1001,9 +1013,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
if (ret == 0) {
/*
* If interface wans't initialized, set the lane to
- * PHY_TYPE_UNCONNECTED state.
+ * COMPHY_TYPE_UNCONNECTED state.
*/
- ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
+ ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED;
pr_err("PLL is not locked - Failed to initialize lane %d\n",
lane);
}
diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c
index 98327557a899..aaef736b75dd 100644
--- a/drivers/phy/marvell/comphy_mux.c
+++ b/drivers/phy/marvell/comphy_mux.c
@@ -15,7 +15,7 @@
* description: this function passes over the COMPHY lanes and check if the type
* is valid for specific lane. If the type is not valid,
* the function update the struct and set the type of the lane as
- * PHY_TYPE_UNCONNECTED
+ * COMPHY_TYPE_UNCONNECTED
*/
static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
struct comphy_map *comphy_map_data, int comphy_max_lanes)
@@ -28,7 +28,7 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
/* Don't check ignored COMPHYs */
- if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ if (comphy_map_data->type == COMPHY_TYPE_IGNORE)
continue;
mux_opt = mux_data->mux_values;
@@ -43,8 +43,8 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
debug("lane number %d, had invalid type %d\n",
lane, comphy_map_data->type);
debug("set lane %d as type %d\n", lane,
- PHY_TYPE_UNCONNECTED);
- comphy_map_data->type = PHY_TYPE_UNCONNECTED;
+ COMPHY_TYPE_UNCONNECTED);
+ comphy_map_data->type = COMPHY_TYPE_UNCONNECTED;
} else {
debug("lane number %d, has type %d\n",
lane, comphy_map_data->type);
@@ -88,7 +88,7 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
- if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ if (comphy_map_data->type == COMPHY_TYPE_IGNORE)
continue;
/*
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
index 08544fa758bf..7d62dcf7fa51 100644
--- a/include/dt-bindings/comphy/comphy_data.h
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -6,53 +6,53 @@
#ifndef _COMPHY_DATA_H_
#define _COMPHY_DATA_H_
-#define PHY_SPEED_1_25G 0
-#define PHY_SPEED_1_5G 1
-#define PHY_SPEED_2_5G 2
-#define PHY_SPEED_3G 3
-#define PHY_SPEED_3_125G 4
-#define PHY_SPEED_5G 5
-#define PHY_SPEED_5_15625G 6
-#define PHY_SPEED_6G 7
-#define PHY_SPEED_6_25G 8
-#define PHY_SPEED_10_3125G 9
-#define PHY_SPEED_MAX 10
-#define PHY_SPEED_INVALID 0xff
+#define COMPHY_SPEED_1_25G 0
+#define COMPHY_SPEED_1_5G 1
+#define COMPHY_SPEED_2_5G 2
+#define COMPHY_SPEED_3G 3
+#define COMPHY_SPEED_3_125G 4
+#define COMPHY_SPEED_5G 5
+#define COMPHY_SPEED_5_15625G 6
+#define COMPHY_SPEED_6G 7
+#define COMPHY_SPEED_6_25G 8
+#define COMPHY_SPEED_10_3125G 9
+#define COMPHY_SPEED_MAX 10
+#define COMPHY_SPEED_INVALID 0xff
-#define PHY_TYPE_UNCONNECTED 0
-#define PHY_TYPE_PEX0 1
-#define PHY_TYPE_PEX1 2
-#define PHY_TYPE_PEX2 3
-#define PHY_TYPE_PEX3 4
-#define PHY_TYPE_SATA0 5
-#define PHY_TYPE_SATA1 6
-#define PHY_TYPE_SATA2 7
-#define PHY_TYPE_SATA3 8
-#define PHY_TYPE_SGMII0 9
-#define PHY_TYPE_SGMII1 10
-#define PHY_TYPE_SGMII2 11
-#define PHY_TYPE_SGMII3 12
-#define PHY_TYPE_QSGMII 13
-#define PHY_TYPE_USB3 14
-#define PHY_TYPE_USB3_HOST0 15
-#define PHY_TYPE_USB3_HOST1 16
-#define PHY_TYPE_USB3_DEVICE 17
-#define PHY_TYPE_XAUI0 18
-#define PHY_TYPE_XAUI1 19
-#define PHY_TYPE_XAUI2 20
-#define PHY_TYPE_XAUI3 21
-#define PHY_TYPE_RXAUI0 22
-#define PHY_TYPE_RXAUI1 23
-#define PHY_TYPE_SFI 24
-#define PHY_TYPE_IGNORE 25
-#define PHY_TYPE_MAX 26
-#define PHY_TYPE_INVALID 0xff
+#define COMPHY_TYPE_UNCONNECTED 0
+#define COMPHY_TYPE_PEX0 1
+#define COMPHY_TYPE_PEX1 2
+#define COMPHY_TYPE_PEX2 3
+#define COMPHY_TYPE_PEX3 4
+#define COMPHY_TYPE_SATA0 5
+#define COMPHY_TYPE_SATA1 6
+#define COMPHY_TYPE_SATA2 7
+#define COMPHY_TYPE_SATA3 8
+#define COMPHY_TYPE_SGMII0 9
+#define COMPHY_TYPE_SGMII1 10
+#define COMPHY_TYPE_SGMII2 11
+#define COMPHY_TYPE_SGMII3 12
+#define COMPHY_TYPE_QSGMII 13
+#define COMPHY_TYPE_USB3 14
+#define COMPHY_TYPE_USB3_HOST0 15
+#define COMPHY_TYPE_USB3_HOST1 16
+#define COMPHY_TYPE_USB3_DEVICE 17
+#define COMPHY_TYPE_XAUI0 18
+#define COMPHY_TYPE_XAUI1 19
+#define COMPHY_TYPE_XAUI2 20
+#define COMPHY_TYPE_XAUI3 21
+#define COMPHY_TYPE_RXAUI0 22
+#define COMPHY_TYPE_RXAUI1 23
+#define COMPHY_TYPE_SFI 24
+#define COMPHY_TYPE_IGNORE 25
+#define COMPHY_TYPE_MAX 26
+#define COMPHY_TYPE_INVALID 0xff
-#define PHY_POLARITY_NO_INVERT 0
-#define PHY_POLARITY_TXD_INVERT 1
-#define PHY_POLARITY_RXD_INVERT 2
-#define PHY_POLARITY_ALL_INVERT \
- (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
+#define COMPHY_POLARITY_NO_INVERT 0
+#define COMPHY_POLARITY_TXD_INVERT 1
+#define COMPHY_POLARITY_RXD_INVERT 2
+#define COMPHY_POLARITY_ALL_INVERT \
+ (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT)
#define UTMI_PHY_TO_USB3_HOST0 0
#define UTMI_PHY_TO_USB3_HOST1 1
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX
2021-03-24 14:06 ` [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX Stefan Roese
@ 2021-03-24 14:42 ` Pali Rohár
2021-03-24 15:04 ` [EXT] " Kostya Porotchkin
0 siblings, 1 reply; 39+ messages in thread
From: Pali Rohár @ 2021-03-24 14:42 UTC (permalink / raw)
To: u-boot
On Wednesday 24 March 2021 15:06:28 Stefan Roese wrote:
> diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
> index 96a4b3d95b88..3cea5218d2b3 100644
> --- a/arch/arm/dts/armada-3720-espressobin.dts
> +++ b/arch/arm/dts/armada-3720-espressobin.dts
> @@ -83,18 +83,18 @@
> &comphy {
> max-lanes = <3>;
> phy0 {
> - phy-type = <PHY_TYPE_USB3_HOST0>;
> - phy-speed = <PHY_SPEED_5G>;
> + phy-type = <COMPHY_TYPE_PEX0>;
> + phy-speed = <COMPHY_SPEED_2_5G>;
Why you are changing type USB to type PCIe? Possible typo?
> };
>
> phy1 {
> - phy-type = <PHY_TYPE_PEX0>;
> - phy-speed = <PHY_SPEED_2_5G>;
> + phy-type = <COMPHY_TYPE_USB3_HOST0>;
> + phy-speed = <COMPHY_SPEED_5G>;
Same here. PCIe is changed to USB.
> };
>
> phy2 {
> - phy-type = <PHY_TYPE_SATA0>;
> - phy-speed = <PHY_SPEED_5G>;
> + phy-type = <COMPHY_TYPE_SATA0>;
> + phy-speed = <COMPHY_SPEED_5G>;
> };
> };
^ permalink raw reply [flat|nested] 39+ messages in thread* [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX
2021-03-24 14:42 ` Pali Rohár
@ 2021-03-24 15:04 ` Kostya Porotchkin
2021-03-24 15:39 ` Stefan Roese
0 siblings, 1 reply; 39+ messages in thread
From: Kostya Porotchkin @ 2021-03-24 15:04 UTC (permalink / raw)
To: u-boot
Hi, Pali,
> -----Original Message-----
> From: Pali Roh?r <pali@kernel.org>
> Sent: Wednesday, March 24, 2021 16:43
> To: Stefan Roese <sr@denx.de>
> Cc: u-boot at lists.denx.de; Nadav Haklai <nadavh@marvell.com>; Kostya
> Porotchkin <kostap@marvell.com>; Marek Beh?n <marek.behun@nic.cz>;
> Grzegorz Jaszczyk <jaz@semihalf.com>; Igal Liberman <igall@marvell.com>;
> Baruch Siach <baruch@tkos.co.il>
> Subject: [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related
> definitions to COMPHY_XX
>
> External Email
>
> ----------------------------------------------------------------------
> On Wednesday 24 March 2021 15:06:28 Stefan Roese wrote:
> > diff --git a/arch/arm/dts/armada-3720-espressobin.dts
> b/arch/arm/dts/armada-3720-espressobin.dts
> > index 96a4b3d95b88..3cea5218d2b3 100644
> > --- a/arch/arm/dts/armada-3720-espressobin.dts
> > +++ b/arch/arm/dts/armada-3720-espressobin.dts
> > @@ -83,18 +83,18 @@
> > &comphy {
> > max-lanes = <3>;
> > phy0 {
> > - phy-type = <PHY_TYPE_USB3_HOST0>;
> > - phy-speed = <PHY_SPEED_5G>;
> > + phy-type = <COMPHY_TYPE_PEX0>;
> > + phy-speed = <COMPHY_SPEED_2_5G>;
>
> Why you are changing type USB to type PCIe? Possible typo?
[KP] This patch is older that the one that fixed A3720 SERDES assignment.
So you are right, this change is wrong today and I missed it.
Stefan, we should either take into account the below patch, or fix this one.
commit 9869490d13d8b47b3464e1de04bb82b7a3f39fd0
Author: Ken Ma <make@marvell.com>
Date: Fri May 12 10:55:56 2017 +0800
arm64: dts: a37xx: update comphy lane numbers
The latest change in the comphy_a3700.c driver aligned
the lanes assignment to the functional specification.
Reflect that in supported device trees.
Change-Id: Id7a239bd00e35e66b4e5023db081bb417267b8ca
Signed-off-by: Ken Ma <make@marvell.com>
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 169828cbc4..8ee3bdf533 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -101,13 +101,13 @@
&comphy {
phy0 {
- phy-type = <COMPHY_TYPE_PEX0>;
- phy-speed = <COMPHY_SPEED_2_5G>;
+ phy-type = <COMPHY_TYPE_USB3>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy1 {
- phy-type = <COMPHY_TYPE_USB3>;
- phy-speed = <COMPHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_2_5G>;
};
phy2 {
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
index f8fd4ed244..94cab2f4d1 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -72,13 +72,13 @@
&comphy {
max-lanes = <3>;
phy0 {
- phy-type = <COMPHY_TYPE_PEX0>;
- phy-speed = <COMPHY_SPEED_2_5G>;
+ phy-type = <COMPHY_TYPE_USB3>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy1 {
- phy-type = <COMPHY_TYPE_USB3>;
- phy-speed = <COMPHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_2_5G>;
};
phy2 {
>
> > };
> >
> > phy1 {
> > - phy-type = <PHY_TYPE_PEX0>;
> > - phy-speed = <PHY_SPEED_2_5G>;
> > + phy-type = <COMPHY_TYPE_USB3_HOST0>;
> > + phy-speed = <COMPHY_SPEED_5G>;
>
> Same here. PCIe is changed to USB.
[KP] Yes, need to be fixed, thanks, Pali.
Regards
Kosta
>
> > };
> >
> > phy2 {
> > - phy-type = <PHY_TYPE_SATA0>;
> > - phy-speed = <PHY_SPEED_5G>;
> > + phy-type = <COMPHY_TYPE_SATA0>;
> > + phy-speed = <COMPHY_SPEED_5G>;
> > };
> > };
^ permalink raw reply related [flat|nested] 39+ messages in thread* [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX
2021-03-24 15:04 ` [EXT] " Kostya Porotchkin
@ 2021-03-24 15:39 ` Stefan Roese
2021-03-24 15:47 ` Pali Rohár
0 siblings, 1 reply; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 15:39 UTC (permalink / raw)
To: u-boot
On 24.03.21 16:04, Kostya Porotchkin wrote:
> Hi, Pali,
>
>> -----Original Message-----
>> From: Pali Roh?r <pali@kernel.org>
>> Sent: Wednesday, March 24, 2021 16:43
>> To: Stefan Roese <sr@denx.de>
>> Cc: u-boot at lists.denx.de; Nadav Haklai <nadavh@marvell.com>; Kostya
>> Porotchkin <kostap@marvell.com>; Marek Beh?n <marek.behun@nic.cz>;
>> Grzegorz Jaszczyk <jaz@semihalf.com>; Igal Liberman <igall@marvell.com>;
>> Baruch Siach <baruch@tkos.co.il>
>> Subject: [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related
>> definitions to COMPHY_XX
>>
>> External Email
>>
>> ----------------------------------------------------------------------
>> On Wednesday 24 March 2021 15:06:28 Stefan Roese wrote:
>>> diff --git a/arch/arm/dts/armada-3720-espressobin.dts
>> b/arch/arm/dts/armada-3720-espressobin.dts
>>> index 96a4b3d95b88..3cea5218d2b3 100644
>>> --- a/arch/arm/dts/armada-3720-espressobin.dts
>>> +++ b/arch/arm/dts/armada-3720-espressobin.dts
>>> @@ -83,18 +83,18 @@
>>> &comphy {
>>> max-lanes = <3>;
>>> phy0 {
>>> - phy-type = <PHY_TYPE_USB3_HOST0>;
>>> - phy-speed = <PHY_SPEED_5G>;
>>> + phy-type = <COMPHY_TYPE_PEX0>;
>>> + phy-speed = <COMPHY_SPEED_2_5G>;
>>
>> Why you are changing type USB to type PCIe? Possible typo?
> [KP] This patch is older that the one that fixed A3720 SERDES assignment.
> So you are right, this change is wrong today and I missed it.
>
> Stefan, we should either take into account the below patch, or fix this one.
Sure. I'll either fix this in v2 and add some follow-up patch to
fix this.
Pali, thanks for spotting this.
Thanks,
Stefan
> commit 9869490d13d8b47b3464e1de04bb82b7a3f39fd0
> Author: Ken Ma <make@marvell.com>
> Date: Fri May 12 10:55:56 2017 +0800
>
> arm64: dts: a37xx: update comphy lane numbers
>
> The latest change in the comphy_a3700.c driver aligned
> the lanes assignment to the functional specification.
> Reflect that in supported device trees.
>
> Change-Id: Id7a239bd00e35e66b4e5023db081bb417267b8ca
> Signed-off-by: Ken Ma <make@marvell.com>
>
> diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
> index 169828cbc4..8ee3bdf533 100644
> --- a/arch/arm/dts/armada-3720-db.dts
> +++ b/arch/arm/dts/armada-3720-db.dts
> @@ -101,13 +101,13 @@
>
> &comphy {
> phy0 {
> - phy-type = <COMPHY_TYPE_PEX0>;
> - phy-speed = <COMPHY_SPEED_2_5G>;
> + phy-type = <COMPHY_TYPE_USB3>;
> + phy-speed = <COMPHY_SPEED_5G>;
> };
>
> phy1 {
> - phy-type = <COMPHY_TYPE_USB3>;
> - phy-speed = <COMPHY_SPEED_5G>;
> + phy-type = <COMPHY_TYPE_PEX0>;
> + phy-speed = <COMPHY_SPEED_2_5G>;
> };
>
> phy2 {
> diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
> index f8fd4ed244..94cab2f4d1 100644
> --- a/arch/arm/dts/armada-3720-espressobin.dts
> +++ b/arch/arm/dts/armada-3720-espressobin.dts
> @@ -72,13 +72,13 @@
> &comphy {
> max-lanes = <3>;
> phy0 {
> - phy-type = <COMPHY_TYPE_PEX0>;
> - phy-speed = <COMPHY_SPEED_2_5G>;
> + phy-type = <COMPHY_TYPE_USB3>;
> + phy-speed = <COMPHY_SPEED_5G>;
> };
>
> phy1 {
> - phy-type = <COMPHY_TYPE_USB3>;
> - phy-speed = <COMPHY_SPEED_5G>;
> + phy-type = <COMPHY_TYPE_PEX0>;
> + phy-speed = <COMPHY_SPEED_2_5G>;
> };
>
> phy2 {
>
>>
>>> };
>>>
>>> phy1 {
>>> - phy-type = <PHY_TYPE_PEX0>;
>>> - phy-speed = <PHY_SPEED_2_5G>;
>>> + phy-type = <COMPHY_TYPE_USB3_HOST0>;
>>> + phy-speed = <COMPHY_SPEED_5G>;
>>
>> Same here. PCIe is changed to USB.
> [KP] Yes, need to be fixed, thanks, Pali.
>
> Regards
> Kosta
>>
>>> };
>>>
>>> phy2 {
>>> - phy-type = <PHY_TYPE_SATA0>;
>>> - phy-speed = <PHY_SPEED_5G>;
>>> + phy-type = <COMPHY_TYPE_SATA0>;
>>> + phy-speed = <COMPHY_SPEED_5G>;
>>> };
>>> };
Viele Gr??e,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread* [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX
2021-03-24 15:39 ` Stefan Roese
@ 2021-03-24 15:47 ` Pali Rohár
2021-03-24 17:41 ` Marek Behun
2021-04-08 8:03 ` Stefan Roese
0 siblings, 2 replies; 39+ messages in thread
From: Pali Rohár @ 2021-03-24 15:47 UTC (permalink / raw)
To: u-boot
On Wednesday 24 March 2021 16:39:22 Stefan Roese wrote:
> On 24.03.21 16:04, Kostya Porotchkin wrote:
> > Hi, Pali,
> >
> > > -----Original Message-----
> > > From: Pali Roh?r <pali@kernel.org>
> > > Sent: Wednesday, March 24, 2021 16:43
> > > To: Stefan Roese <sr@denx.de>
> > > Cc: u-boot at lists.denx.de; Nadav Haklai <nadavh@marvell.com>; Kostya
> > > Porotchkin <kostap@marvell.com>; Marek Beh?n <marek.behun@nic.cz>;
> > > Grzegorz Jaszczyk <jaz@semihalf.com>; Igal Liberman <igall@marvell.com>;
> > > Baruch Siach <baruch@tkos.co.il>
> > > Subject: [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related
> > > definitions to COMPHY_XX
> > >
> > > External Email
> > >
> > > ----------------------------------------------------------------------
> > > On Wednesday 24 March 2021 15:06:28 Stefan Roese wrote:
> > > > diff --git a/arch/arm/dts/armada-3720-espressobin.dts
> > > b/arch/arm/dts/armada-3720-espressobin.dts
> > > > index 96a4b3d95b88..3cea5218d2b3 100644
> > > > --- a/arch/arm/dts/armada-3720-espressobin.dts
> > > > +++ b/arch/arm/dts/armada-3720-espressobin.dts
> > > > @@ -83,18 +83,18 @@
> > > > &comphy {
> > > > max-lanes = <3>;
> > > > phy0 {
> > > > - phy-type = <PHY_TYPE_USB3_HOST0>;
> > > > - phy-speed = <PHY_SPEED_5G>;
> > > > + phy-type = <COMPHY_TYPE_PEX0>;
> > > > + phy-speed = <COMPHY_SPEED_2_5G>;
> > >
> > > Why you are changing type USB to type PCIe? Possible typo?
> > [KP] This patch is older that the one that fixed A3720 SERDES assignment.
> > So you are right, this change is wrong today and I missed it.
> >
> > Stefan, we should either take into account the below patch, or fix this one.
>
> Sure. I'll either fix this in v2 and add some follow-up patch to
> fix this.
Just squash fixup patch into 02/23, so code in u-boot git would be
working at every commit (very useful for git bisect).
> Pali, thanks for spotting this.
>
> Thanks,
> Stefan
>
> > commit 9869490d13d8b47b3464e1de04bb82b7a3f39fd0
> > Author: Ken Ma <make@marvell.com>
> > Date: Fri May 12 10:55:56 2017 +0800
> >
> > arm64: dts: a37xx: update comphy lane numbers
> > The latest change in the comphy_a3700.c driver aligned
> > the lanes assignment to the functional specification.
> > Reflect that in supported device trees.
> > Change-Id: Id7a239bd00e35e66b4e5023db081bb417267b8ca
> > Signed-off-by: Ken Ma <make@marvell.com>
> >
> > diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
> > index 169828cbc4..8ee3bdf533 100644
> > --- a/arch/arm/dts/armada-3720-db.dts
> > +++ b/arch/arm/dts/armada-3720-db.dts
> > @@ -101,13 +101,13 @@
> > &comphy {
> > phy0 {
> > - phy-type = <COMPHY_TYPE_PEX0>;
> > - phy-speed = <COMPHY_SPEED_2_5G>;
> > + phy-type = <COMPHY_TYPE_USB3>;
> > + phy-speed = <COMPHY_SPEED_5G>;
> > };
> > phy1 {
> > - phy-type = <COMPHY_TYPE_USB3>;
> > - phy-speed = <COMPHY_SPEED_5G>;
> > + phy-type = <COMPHY_TYPE_PEX0>;
> > + phy-speed = <COMPHY_SPEED_2_5G>;
> > };
> > phy2 {
> > diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
> > index f8fd4ed244..94cab2f4d1 100644
> > --- a/arch/arm/dts/armada-3720-espressobin.dts
> > +++ b/arch/arm/dts/armada-3720-espressobin.dts
> > @@ -72,13 +72,13 @@
> > &comphy {
> > max-lanes = <3>;
> > phy0 {
> > - phy-type = <COMPHY_TYPE_PEX0>;
> > - phy-speed = <COMPHY_SPEED_2_5G>;
> > + phy-type = <COMPHY_TYPE_USB3>;
> > + phy-speed = <COMPHY_SPEED_5G>;
> > };
> > phy1 {
> > - phy-type = <COMPHY_TYPE_USB3>;
> > - phy-speed = <COMPHY_SPEED_5G>;
> > + phy-type = <COMPHY_TYPE_PEX0>;
> > + phy-speed = <COMPHY_SPEED_2_5G>;
> > };
> > phy2 {
> >
> > >
> > > > };
> > > >
> > > > phy1 {
> > > > - phy-type = <PHY_TYPE_PEX0>;
> > > > - phy-speed = <PHY_SPEED_2_5G>;
> > > > + phy-type = <COMPHY_TYPE_USB3_HOST0>;
> > > > + phy-speed = <COMPHY_SPEED_5G>;
> > >
> > > Same here. PCIe is changed to USB.
> > [KP] Yes, need to be fixed, thanks, Pali.
> >
> > Regards
> > Kosta
> > >
> > > > };
> > > >
> > > > phy2 {
> > > > - phy-type = <PHY_TYPE_SATA0>;
> > > > - phy-speed = <PHY_SPEED_5G>;
> > > > + phy-type = <COMPHY_TYPE_SATA0>;
> > > > + phy-speed = <COMPHY_SPEED_5G>;
> > > > };
> > > > };
>
>
> Viele Gr??e,
> Stefan
>
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread* [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX
2021-03-24 15:47 ` Pali Rohár
@ 2021-03-24 17:41 ` Marek Behun
2021-04-08 8:03 ` Stefan Roese
1 sibling, 0 replies; 39+ messages in thread
From: Marek Behun @ 2021-03-24 17:41 UTC (permalink / raw)
To: u-boot
Please be also aware the we have the following patch U-Boot
commit 545591132aa701ff1262bb309fbcd0c3ff0acd75
Author: Marek Beh?n <marek.behun@nic.cz>
Date: Wed Aug 19 11:57:25 2020 +0200
arm64: dts: armada-3720-espressobin: fix COMPHY nodes
This commit fixes initialization of COMPHY on EspressoBin.
Commit 22f418935be4 ("phy: marvell: a3700: Use comphy_mux on Armada
37xx.") introduced usage of comphy_mux on Armada 37xx comphy driver.
The lanes are defined in comphy_a3700.c as described in functional
specification, that is:
lane 0 is SGMII1 or USB3
lane 1 is PCIe or SGMII0
lane 2 is SATA or USB3
But the DTS for EspressoBin configures PCIe on lane 0 and USB3 on
lane 1, which is wrong in the sense of the specification and doesn't
work with the comphy_mux code, which is 2 years now (the aardvark driver
causes synchronous abort in U-Boot).
It worked till the above mentioned commit, because the code for powering
up PCIe PHY doesn't work with lane number at all, and the code for
powering up USB3 PHY works differently only if USB3 is on lane 2, ie.
the check goes like:
if (lane == 2)
something
else
something else
so it does not differentiate between lanes 0 and 1.
In the future I shall post patches that remove the comphy_a3700 driver
and add comphy driver which uses calls to ATF, like Linux' driver does.
This will have the advantage of same DTS bindings as Linux', but till
this is done, we need this patch.
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
Tested-by: Pali Roh?r <pali@kernel.org>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Andre Heider <a.heider@gmail.com>
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
index 84e2c2adba..50381e979e 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -72,13 +72,13 @@
&comphy {
max-lanes = <3>;
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_2_5G>;
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-speed = <PHY_SPEED_5G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <PHY_TYPE_PEX0>;
+ phy-speed = <PHY_SPEED_2_5G>;
};
phy2 {
^ permalink raw reply related [flat|nested] 39+ messages in thread* [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX
2021-03-24 15:47 ` Pali Rohár
2021-03-24 17:41 ` Marek Behun
@ 2021-04-08 8:03 ` Stefan Roese
1 sibling, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-04-08 8:03 UTC (permalink / raw)
To: u-boot
On 24.03.21 16:47, Pali Roh?r wrote:
> On Wednesday 24 March 2021 16:39:22 Stefan Roese wrote:
>> On 24.03.21 16:04, Kostya Porotchkin wrote:
>>> Hi, Pali,
>>>
>>>> -----Original Message-----
>>>> From: Pali Roh?r <pali@kernel.org>
>>>> Sent: Wednesday, March 24, 2021 16:43
>>>> To: Stefan Roese <sr@denx.de>
>>>> Cc: u-boot at lists.denx.de; Nadav Haklai <nadavh@marvell.com>; Kostya
>>>> Porotchkin <kostap@marvell.com>; Marek Beh?n <marek.behun@nic.cz>;
>>>> Grzegorz Jaszczyk <jaz@semihalf.com>; Igal Liberman <igall@marvell.com>;
>>>> Baruch Siach <baruch@tkos.co.il>
>>>> Subject: [EXT] Re: [PATCH v1 02/23] phy: marvell: rename comphy related
>>>> definitions to COMPHY_XX
>>>>
>>>> External Email
>>>>
>>>> ----------------------------------------------------------------------
>>>> On Wednesday 24 March 2021 15:06:28 Stefan Roese wrote:
>>>>> diff --git a/arch/arm/dts/armada-3720-espressobin.dts
>>>> b/arch/arm/dts/armada-3720-espressobin.dts
>>>>> index 96a4b3d95b88..3cea5218d2b3 100644
>>>>> --- a/arch/arm/dts/armada-3720-espressobin.dts
>>>>> +++ b/arch/arm/dts/armada-3720-espressobin.dts
>>>>> @@ -83,18 +83,18 @@
>>>>> &comphy {
>>>>> max-lanes = <3>;
>>>>> phy0 {
>>>>> - phy-type = <PHY_TYPE_USB3_HOST0>;
>>>>> - phy-speed = <PHY_SPEED_5G>;
>>>>> + phy-type = <COMPHY_TYPE_PEX0>;
>>>>> + phy-speed = <COMPHY_SPEED_2_5G>;
>>>>
>>>> Why you are changing type USB to type PCIe? Possible typo?
>>> [KP] This patch is older that the one that fixed A3720 SERDES assignment.
>>> So you are right, this change is wrong today and I missed it.
>>>
>>> Stefan, we should either take into account the below patch, or fix this one.
>>
>> Sure. I'll either fix this in v2 and add some follow-up patch to
>> fix this.
>
> Just squash fixup patch into 02/23, so code in u-boot git would be
> working at every commit (very useful for git bisect).
Okay, done. I've send v2 of only this patch.
Thanks,
Stefan
>> Pali, thanks for spotting this.
>>
>> Thanks,
>> Stefan
>>
>>> commit 9869490d13d8b47b3464e1de04bb82b7a3f39fd0
>>> Author: Ken Ma <make@marvell.com>
>>> Date: Fri May 12 10:55:56 2017 +0800
>>>
>>> arm64: dts: a37xx: update comphy lane numbers
>>> The latest change in the comphy_a3700.c driver aligned
>>> the lanes assignment to the functional specification.
>>> Reflect that in supported device trees.
>>> Change-Id: Id7a239bd00e35e66b4e5023db081bb417267b8ca
>>> Signed-off-by: Ken Ma <make@marvell.com>
>>>
>>> diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
>>> index 169828cbc4..8ee3bdf533 100644
>>> --- a/arch/arm/dts/armada-3720-db.dts
>>> +++ b/arch/arm/dts/armada-3720-db.dts
>>> @@ -101,13 +101,13 @@
>>> &comphy {
>>> phy0 {
>>> - phy-type = <COMPHY_TYPE_PEX0>;
>>> - phy-speed = <COMPHY_SPEED_2_5G>;
>>> + phy-type = <COMPHY_TYPE_USB3>;
>>> + phy-speed = <COMPHY_SPEED_5G>;
>>> };
>>> phy1 {
>>> - phy-type = <COMPHY_TYPE_USB3>;
>>> - phy-speed = <COMPHY_SPEED_5G>;
>>> + phy-type = <COMPHY_TYPE_PEX0>;
>>> + phy-speed = <COMPHY_SPEED_2_5G>;
>>> };
>>> phy2 {
>>> diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
>>> index f8fd4ed244..94cab2f4d1 100644
>>> --- a/arch/arm/dts/armada-3720-espressobin.dts
>>> +++ b/arch/arm/dts/armada-3720-espressobin.dts
>>> @@ -72,13 +72,13 @@
>>> &comphy {
>>> max-lanes = <3>;
>>> phy0 {
>>> - phy-type = <COMPHY_TYPE_PEX0>;
>>> - phy-speed = <COMPHY_SPEED_2_5G>;
>>> + phy-type = <COMPHY_TYPE_USB3>;
>>> + phy-speed = <COMPHY_SPEED_5G>;
>>> };
>>> phy1 {
>>> - phy-type = <COMPHY_TYPE_USB3>;
>>> - phy-speed = <COMPHY_SPEED_5G>;
>>> + phy-type = <COMPHY_TYPE_PEX0>;
>>> + phy-speed = <COMPHY_SPEED_2_5G>;
>>> };
>>> phy2 {
>>>
>>>>
>>>>> };
>>>>>
>>>>> phy1 {
>>>>> - phy-type = <PHY_TYPE_PEX0>;
>>>>> - phy-speed = <PHY_SPEED_2_5G>;
>>>>> + phy-type = <COMPHY_TYPE_USB3_HOST0>;
>>>>> + phy-speed = <COMPHY_SPEED_5G>;
>>>>
>>>> Same here. PCIe is changed to USB.
>>> [KP] Yes, need to be fixed, thanks, Pali.
>>>
>>> Regards
>>> Kosta
>>>>
>>>>> };
>>>>>
>>>>> phy2 {
>>>>> - phy-type = <PHY_TYPE_SATA0>;
>>>>> - phy-speed = <PHY_SPEED_5G>;
>>>>> + phy-type = <COMPHY_TYPE_SATA0>;
>>>>> + phy-speed = <COMPHY_SPEED_5G>;
>>>>> };
>>>>> };
>>
>>
>> Viele Gr??e,
>> Stefan
>>
>> --
>> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
Viele Gr??e,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 03/23] phy: marvell: add missing speed during info prints
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
2021-03-24 14:06 ` [PATCH v1 01/23] phy: marvell: add comphy type PHY_TYPE_USB3 Stefan Roese
2021-03-24 14:06 ` [PATCH v1 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 04/23] phy: marvell: cp110: initialize only enabled UTMI units Stefan Roese
` (20 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
In get_speed_string() we have an array (speed_strings[])
which includes all possible speed strings.
This array size and content must be aligned to the speed
defines in comphy_data.h.
This patch adds missing 5.125G speed, aligns speed_strings[]
and fixes incorrect printing when speed > 5.0G.
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_core.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index f1f061d7c116..835fc2e907f2 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -25,8 +25,9 @@ static const char *get_speed_string(u32 speed)
{
static const char * const speed_strings[] = {
"1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
- "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps",
- "6.25 Gbps", "10.31 Gbps"
+ "3.0 Gbps", "3.125 Gbps", "5 Gbps",
+ "5.125 Gpbs", "6 Gbps", "6.25 Gbps",
+ "10.3125 Gbps"
};
if (speed < 0 || speed > COMPHY_SPEED_MAX)
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 04/23] phy: marvell: cp110: initialize only enabled UTMI units
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (2 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 03/23] phy: marvell: add missing speed during info prints Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 05/23] phy: marvell: cp110: utmi: update analog parameters according to latest ETP Stefan Roese
` (19 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Omri Itach <omrii@marvell.com>
UTMI should be initialized only for enabled device tree nodes.
This fix overrides current internal configuration array
entry with the next DT entry data if error is detected
during the current DT entry parsing or the current port
is disabled.
This way the internal configuration structure will only
contain valid ports information obtained from the DT.
Signed-off-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 51 +++++++++++++++---------------
1 file changed, 26 insertions(+), 25 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index e4ab90121c74..82d869368858 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -715,7 +715,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
* the init split in 3 parts:
* 1. Power down transceiver and PLL
* 2. UTMI PHY configure
- * 3. Powe up transceiver and PLL
+ * 3. Power up transceiver and PLL
* Note: - Power down/up should be once for both UTMI PHYs
* - comphy_dedicated_phys_init call this function if at least there is
* one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
@@ -782,45 +782,47 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count,
void comphy_dedicated_phys_init(void)
{
struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
- int node;
- int i;
+ int node = -1;
+ int node_idx;
debug_enter();
debug("Initialize USB UTMI PHYs\n");
- /* Find the UTMI phy node in device tree and go over them */
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "marvell,mvebu-utmi-2.6.0");
+ for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) {
+ /* Find the UTMI phy node in device tree */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
+ "marvell,mvebu-utmi-2.6.0");
+ if (node <= 0)
+ break;
+
+ /* check if node is enabled */
+ if (!fdtdec_get_is_enabled(gd->fdt_blob, node))
+ continue;
- i = 0;
- while (node > 0) {
/* get base address of UTMI phy */
- cp110_utmi_data[i].utmi_base_addr =
+ cp110_utmi_data[node_idx].utmi_base_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 0, NULL, true);
- if (cp110_utmi_data[i].utmi_base_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].utmi_base_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
/* get usb config address */
- cp110_utmi_data[i].usb_cfg_addr =
+ cp110_utmi_data[node_idx].usb_cfg_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 1, NULL, true);
- if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].usb_cfg_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
/* get UTMI config address */
- cp110_utmi_data[i].utmi_cfg_addr =
+ cp110_utmi_data[node_idx].utmi_cfg_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 2, NULL, true);
- if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].utmi_cfg_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
@@ -828,21 +830,20 @@ void comphy_dedicated_phys_init(void)
* get the port number (to check if the utmi connected to
* host/device)
*/
- cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
+ cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int(
gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
- if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
+ if (cp110_utmi_data[node_idx].utmi_phy_port ==
+ UTMI_PHY_INVALID) {
pr_err("UTMI PHY port type is invalid\n");
- i++;
continue;
}
- node = fdt_node_offset_by_compatible(
- gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
- i++;
+ /* count valid UTMI unit */
+ node_idx++;
}
- if (i > 0)
- comphy_utmi_phy_init(i, cp110_utmi_data);
+ if (node_idx > 0)
+ comphy_utmi_phy_init(node_idx, cp110_utmi_data);
debug_exit();
}
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 05/23] phy: marvell: cp110: utmi: update analog parameters according to latest ETP
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (3 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 04/23] phy: marvell: cp110: initialize only enabled UTMI units Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 06/23] phy: marvell: fix several minor bugs in comphy_probe Stefan Roese
` (18 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
Add UTMI analog parameters initialization values according to
latest ETP.
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 9 +++------
drivers/phy/marvell/utmi_phy.h | 5 ++++-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 82d869368858..72563f8bc1c5 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -614,15 +614,12 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
/* Impedance Calibration Threshold Setting */
reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
- 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
+ 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
/* Set LS TX driver strength coarse control */
- mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
- data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
- /* Set LS TX driver fine adjustment */
- mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
- data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
+ mask = UTMI_TX_CH_CTRL_AMP_MASK;
+ data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
/* Enable SQ */
diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h
index 682a3acc40d8..fa6bf3c9141e 100644
--- a/drivers/phy/marvell/utmi_phy.h
+++ b/drivers/phy/marvell/utmi_phy.h
@@ -52,6 +52,9 @@
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
+#define UTMI_TX_CH_CTRL_AMP_OFFSET 20
+#define UTMI_TX_CH_CTRL_AMP_MASK \
+ (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
#define UTMI_RX_CH_CTRL0_REG 0x14
#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
@@ -64,7 +67,7 @@
#define UTMI_RX_CH_CTRL1_REG 0x18
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \
- (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
+ (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \
(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 06/23] phy: marvell: fix several minor bugs in comphy_probe
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (4 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 05/23] phy: marvell: cp110: utmi: update analog parameters according to latest ETP Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 07/23] phy: marvell: save comphy_map_data priv structure Stefan Roese
` (17 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
If fdtdec_get_int can't find speed, set COMPHY_SPEED_INVALID
If fdtdec_get_int can't find type, set COMPHY_TYPE_INVALID
Move the error print if phy-type is invalid
Add continue to the probe loop (in a case of invalid phy)
Cosmetic changes
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_core.c | 29 +++++++++++++++++++----------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 835fc2e907f2..d3c89c97747e 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -136,21 +136,30 @@ static int comphy_probe(struct udevice *dev)
if (!fdtdec_get_is_enabled(blob, subnode))
continue;
- comphy_map_data[lane].speed = fdtdec_get_int(
- blob, subnode, "phy-speed", COMPHY_TYPE_INVALID);
- comphy_map_data[lane].type = fdtdec_get_int(
- blob, subnode, "phy-type", COMPHY_SPEED_INVALID);
- comphy_map_data[lane].invert = fdtdec_get_int(
- blob, subnode, "phy-invert", COMPHY_POLARITY_NO_INVERT);
- comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
- "clk-src");
- comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode,
- "end_point");
+ comphy_map_data[lane].type =
+ fdtdec_get_int(blob, subnode, "phy-type",
+ COMPHY_TYPE_INVALID);
+
if (comphy_map_data[lane].type == COMPHY_TYPE_INVALID) {
printf("no phy type for lane %d, setting lane as unconnected\n",
lane + 1);
+ continue;
}
+ comphy_map_data[lane].speed =
+ fdtdec_get_int(blob, subnode, "phy-speed",
+ COMPHY_SPEED_INVALID);
+
+ comphy_map_data[lane].invert =
+ fdtdec_get_int(blob, subnode, "phy-invert",
+ COMPHY_POLARITY_NO_INVERT);
+
+ comphy_map_data[lane].clk_src =
+ fdtdec_get_bool(blob, subnode, "clk-src");
+
+ comphy_map_data[lane].end_point =
+ fdtdec_get_bool(blob, subnode, "end_point");
+
lane++;
}
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 07/23] phy: marvell: save comphy_map_data priv structure
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (5 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 06/23] phy: marvell: fix several minor bugs in comphy_probe Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 08/23] phy: marvell: add RX training command Stefan Roese
` (16 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
This allows the lower level driver access to comphy map data
(required for RX training support, which is introduced
in the following patches).
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_core.c | 20 ++++++++++----------
drivers/phy/marvell/comphy_core.h | 1 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index d3c89c97747e..d8df7ac949a3 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -81,7 +81,6 @@ static int comphy_probe(struct udevice *dev)
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
- struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
int subnode;
int lane;
int last_idx = 0;
@@ -136,45 +135,46 @@ static int comphy_probe(struct udevice *dev)
if (!fdtdec_get_is_enabled(blob, subnode))
continue;
- comphy_map_data[lane].type =
+ chip_cfg->comphy_map_data[lane].type =
fdtdec_get_int(blob, subnode, "phy-type",
COMPHY_TYPE_INVALID);
- if (comphy_map_data[lane].type == COMPHY_TYPE_INVALID) {
+ if (chip_cfg->comphy_map_data[lane].type ==
+ COMPHY_TYPE_INVALID) {
printf("no phy type for lane %d, setting lane as unconnected\n",
lane + 1);
continue;
}
- comphy_map_data[lane].speed =
+ chip_cfg->comphy_map_data[lane].speed =
fdtdec_get_int(blob, subnode, "phy-speed",
COMPHY_SPEED_INVALID);
- comphy_map_data[lane].invert =
+ chip_cfg->comphy_map_data[lane].invert =
fdtdec_get_int(blob, subnode, "phy-invert",
COMPHY_POLARITY_NO_INVERT);
- comphy_map_data[lane].clk_src =
+ chip_cfg->comphy_map_data[lane].clk_src =
fdtdec_get_bool(blob, subnode, "clk-src");
- comphy_map_data[lane].end_point =
+ chip_cfg->comphy_map_data[lane].end_point =
fdtdec_get_bool(blob, subnode, "end_point");
lane++;
}
- res = comphy_update_map(comphy_map_data, chip_cfg->comphy_lanes_count);
+ res = comphy_update_map(chip_cfg->comphy_map_data, chip_cfg->comphy_lanes_count);
if (res < 0)
return res;
/* Save CP index for MultiCP devices (A8K) */
chip_cfg->cp_index = current_idx++;
/* PHY power UP sequence */
- chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
+ chip_cfg->ptr_comphy_chip_init(chip_cfg, chip_cfg->comphy_map_data);
/* PHY print SerDes status */
if (of_machine_is_compatible("marvell,armada8040"))
printf("Comphy chip #%d:\n", chip_cfg->cp_index);
- comphy_print(chip_cfg, comphy_map_data);
+ comphy_print(chip_cfg, chip_cfg->comphy_map_data);
/*
* Only run the dedicated PHY init code once, in the last PHY init call
diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h
index 12ab921d24c3..c08677e56d2e 100644
--- a/drivers/phy/marvell/comphy_core.h
+++ b/drivers/phy/marvell/comphy_core.h
@@ -90,6 +90,7 @@ struct chip_serdes_phy_config {
u32 comphy_mux_bitcount;
const fdt32_t *comphy_mux_lane_order;
u32 cp_index;
+ struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
};
/* Register helper functions */
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 08/23] phy: marvell: add RX training command
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (6 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 07/23] phy: marvell: save comphy_map_data priv structure Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 17:46 ` Marek Behun
2021-03-24 14:06 ` [PATCH v1 09/23] phy: marvell: enable comphy info prints for all devices Stefan Roese
` (15 subsequent siblings)
23 siblings, 1 reply; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
This patch adds support for running RX training using new command called
"rx_training"
Usage:
rx_training - rx_training <cp id> <comphy id>
RX training allows to improve link quality (for SFI mode)
by running training sequence between us and the link partner,
this allows to reach better link quality then using static configuration.
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
cmd/mvebu/Kconfig | 7 +
cmd/mvebu/Makefile | 2 +-
cmd/mvebu/rx_training.c | 57 +++++++++
configs/mvebu_db_armada8k_defconfig | 1 +
drivers/phy/marvell/comphy_core.c | 18 ++-
drivers/phy/marvell/comphy_core.h | 14 ++
drivers/phy/marvell/comphy_cp110.c | 190 ++++++++++++++++++++++++++++
drivers/phy/marvell/comphy_hpipe.h | 62 ++++++++-
include/mvebu/comphy.h | 2 +-
9 files changed, 348 insertions(+), 5 deletions(-)
create mode 100644 cmd/mvebu/rx_training.c
diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig
index f1eb00614dd6..f0e4f884d703 100644
--- a/cmd/mvebu/Kconfig
+++ b/cmd/mvebu/Kconfig
@@ -49,4 +49,11 @@ config MVEBU_UBOOT_DFLT_NAME
This option should contain a default file name to be used with
MVEBU "bubt" command if the source file name is omitted
+config CMD_MVEBU_RX_TRAINING
+ bool "rx_training"
+ depends on TARGET_MVEBU_ARMADA_8K
+ default n
+ help
+ Perform RX training sequence
+
endmenu
diff --git a/cmd/mvebu/Makefile b/cmd/mvebu/Makefile
index 96829c48ebdc..79299b0814f4 100644
--- a/cmd/mvebu/Makefile
+++ b/cmd/mvebu/Makefile
@@ -4,5 +4,5 @@
#
# https://spdx.org/licenses
-
obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o
+obj-$(CONFIG_CMD_MVEBU_RX_TRAINING) += rx_training.o
diff --git a/cmd/mvebu/rx_training.c b/cmd/mvebu/rx_training.c
new file mode 100644
index 000000000000..4bae7653aca3
--- /dev/null
+++ b/cmd/mvebu/rx_training.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <dm/device-internal.h>
+#include <mvebu/comphy.h>
+
+int rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret, cp_index, comphy_index, i = 0;
+
+ if (argc != 3) {
+ printf("missing arguments\n");
+ return -1;
+ }
+
+ cp_index = simple_strtoul(argv[1], NULL, 16);
+ comphy_index = simple_strtoul(argv[2], NULL, 16);
+
+ ret = uclass_get(UCLASS_MISC, &uc);
+ if (ret) {
+ printf("Couldn't find UCLASS_MISC\n");
+ return ret;
+ }
+
+ uclass_foreach_dev(dev, uc) {
+ if (!(memcmp(dev->name, "comphy", 5))) {
+ if (i == cp_index) {
+ comphy_rx_training(dev, comphy_index);
+ return 0;
+ }
+
+ i++;
+ }
+ }
+
+ printf("Coudn't find comphy %d\n", cp_index);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ rx_training, 3, 0, rx_training_cmd,
+ "rx_training <cp id> <comphy id>\n",
+ "\n\tRun RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)"
+);
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index ffe8e029050f..96baea76fc1c 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -32,6 +32,7 @@ CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_MVEBU_RX_TRAINING=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_OVERWRITE=y
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index d8df7ac949a3..b29decd82693 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -71,6 +71,16 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg,
}
}
+int comphy_rx_training(struct udevice *dev, u32 lane)
+{
+ struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
+
+ if (chip_cfg->rx_training)
+ return chip_cfg->rx_training(chip_cfg, lane);
+
+ return 0;
+}
+
__weak int comphy_update_map(struct comphy_map *serdes_map, int count)
{
return 0;
@@ -114,11 +124,15 @@ static int comphy_probe(struct udevice *dev)
fdtdec_locate_array(blob, node, "mux-lane-order",
chip_cfg->comphy_lanes_count);
- if (device_is_compatible(dev, "marvell,comphy-armada-3700"))
+ if (device_is_compatible(dev, "marvell,comphy-armada-3700")) {
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
+ chip_cfg->rx_training = NULL;
+ }
- if (device_is_compatible(dev, "marvell,comphy-cp110"))
+ if (device_is_compatible(dev, "marvell,comphy-cp110")) {
chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
+ chip_cfg->rx_training = comphy_cp110_sfi_rx_training;
+ }
/*
* Bail out if no chip_init function is defined, e.g. no
diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h
index c08677e56d2e..32895dc4aa3d 100644
--- a/drivers/phy/marvell/comphy_core.h
+++ b/drivers/phy/marvell/comphy_core.h
@@ -84,6 +84,7 @@ struct chip_serdes_phy_config {
struct comphy_mux_data *mux_data;
int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
struct comphy_map *);
+ int (*rx_training)(struct chip_serdes_phy_config *, u32);
void __iomem *comphy_base_addr;
void __iomem *hpipe3_base_addr;
u32 comphy_lanes_count;
@@ -151,6 +152,8 @@ static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
#ifdef CONFIG_ARMADA_8K
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map);
+int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane);
#else
static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
@@ -161,6 +164,17 @@ static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
*/
return -1;
}
+
+static inline int comphy_cp110_sfi_rx_training(
+ struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
#endif
void comphy_dedicated_phys_init(void);
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 72563f8bc1c5..11dc46b28a63 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -133,6 +133,196 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val,
return 0;
}
+/* This function performs RX training for single FFE value.
+ * The result of the RX training is located in:
+ * Saved DFE values Register[10:15].
+ *
+ * The result is returned to the caller using *result
+ *
+ * Return '1' on succsess.
+ * Return '0' on failure.
+ */
+static int comphy_cp110_test_single_ffe(
+ struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane, u32 ffe, u32 *result)
+{
+ u32 mask, data, timeout;
+ void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
+ void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane);
+ void __iomem *sd_ip_addr = SD_ADDR(hpipe_base_addr, lane);
+
+ /* Configure PRBS counters */
+ mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
+ data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
+
+ mask = HPIPE_PHY_TEST_DATA_MASK;
+ data = 0x64 << HPIPE_PHY_TEST_DATA_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
+
+ mask = HPIPE_PHY_TEST_EN_MASK;
+ data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
+
+ mdelay(50);
+
+ /* Set the FFE value */
+ mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
+ data = ffe << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
+
+ /* Start RX training */
+ mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK;
+ data = 1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask);
+
+ /* Check the result of RX training */
+ timeout = RX_TRAINING_TIMEOUT;
+ while (timeout) {
+ data = readl(sd_ip_addr + SD_EXTERNAL_STATUS1_REG);
+ if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK)
+ break;
+ mdelay(1);
+ timeout--;
+ }
+
+ if (timeout == 0)
+ return 0;
+
+ if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK)
+ return 0;
+
+ /* Stop RX training */
+ mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK;
+ data = 0 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask);
+
+ /* Read the result */
+ data = readl(hpipe_addr + HPIPE_SAVED_DFE_VALUES_REG);
+ data &= HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK;
+ data >>= HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET;
+ *result = data;
+
+ printf("FFE = %d, result = 0x%x\n", ffe, *result);
+
+ /* Clear the PRBS counters */
+ mask = HPIPE_PHY_TEST_RESET_MASK;
+ data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET;
+ mask |= HPIPE_PHY_TEST_EN_MASK;
+ data |= 0x0 << HPIPE_PHY_TEST_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
+
+ mask = HPIPE_PHY_TEST_RESET_MASK;
+ data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
+
+ return 1;
+}
+
+/* This function performs RX training for all FFE possible values.
+ * We get the result for each FFE and eventually the best FFE will
+ * be used and set to the HW.
+ *
+ * Return '1' on succsess.
+ * Return '0' on failure.
+ */
+int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane)
+{
+ u32 mask, data, i, rx_train_result;
+ u32 max_rx_train = 0, max_rx_train_index = 0;
+ void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
+ void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane);
+ int ret;
+
+ debug_enter();
+
+ if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
+ pr_err("Comphy %d isn't configured to SFI\n", lane);
+ return 0;
+ }
+
+ /* Configure SQ threshold and CDR lock */
+ mask = HPIPE_SQUELCH_THRESH_IN_MASK;
+ data = 0xc << HPIPE_SQUELCH_THRESH_IN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG, data, mask);
+
+ mask = HPIPE_SQ_DEGLITCH_WIDTH_P_MASK;
+ data = 0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET;
+ mask |= HPIPE_SQ_DEGLITCH_WIDTH_N_MASK;
+ data |= 0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET;
+ mask |= HPIPE_SQ_DEGLITCH_EN_MASK;
+ data |= 0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_SQ_GLITCH_FILTER_CTRL, data, mask);
+
+ mask = HPIPE_CDR_LOCK_DET_EN_MASK;
+ data = 0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
+
+ udelay(100);
+
+ /* Determine if we have a cable attached to this comphy, if not,
+ * we can't perform RX training.
+ */
+ data = readl(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG);
+ if (data & HPIPE_SQUELCH_DETECTED_MASK) {
+ pr_err("Squelsh is not detected, can't perform RX training\n");
+ return 0;
+ }
+
+ data = readl(hpipe_addr + HPIPE_LOOPBACK_REG);
+ if (!(data & HPIPE_CDR_LOCK_MASK)) {
+ pr_err("CDR is not locked, can't perform RX training\n");
+ return 0;
+ }
+
+ /* Do preparations for RX training */
+ mask = HPIPE_DFE_RES_FORCE_MASK;
+ data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
+
+ mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
+ data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
+ mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
+ data |= 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
+
+ /* Performs RX training for all possible FFE (Feed Forward
+ * Equalization, possible values are 0-7).
+ * We update the best value reached and the FFE which gave this value.
+ */
+ for (i = 0; i < MAX_NUM_OF_FFE; i++) {
+ rx_train_result = 0;
+ ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane,
+ i, &rx_train_result);
+
+ if (ret && (rx_train_result > max_rx_train)) {
+ max_rx_train = rx_train_result;
+ max_rx_train_index = i;
+ }
+ }
+
+ /* If we were able to determine which FFE gives the best value,
+ * now we need to set it and run RX training again (only for this
+ * FFE).
+ */
+ if (max_rx_train) {
+ ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane,
+ max_rx_train_index,
+ &rx_train_result);
+ if (ret == 1)
+ printf("RX Training passed(FFE = %d, result = 0x%x)\n",
+ max_rx_train_index, rx_train_result);
+ } else {
+ pr_err("RX training failed\n");
+ ret = 0;
+ }
+
+ debug_exit();
+
+ return ret;
+}
+
static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
void __iomem *comphy_base)
{
diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
index a692035c9417..cf2f986281ea 100644
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ b/drivers/phy/marvell/comphy_hpipe.h
@@ -6,6 +6,9 @@
#ifndef _COMPHY_HPIPE_H_
#define _COMPHY_HPIPE_H_
+#define MAX_NUM_OF_FFE 8
+#define RX_TRAINING_TIMEOUT 500
+
/* SerDes IP register */
#define SD_EXTERNAL_CONFIG0_REG 0
#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
@@ -52,6 +55,11 @@
#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
(0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
+#define SD_EXTERNAL_STATUS_REG 0xc
+#define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7
+#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \
+ (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET)
+
#define SD_EXTERNAL_STATUS0_REG 0x18
#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
@@ -66,6 +74,14 @@
#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
(0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
+#define SD_EXTERNAL_STATUS1_REG 0x1c
+#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET 0
+#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK \
+ (1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET)
+#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET 1
+#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK \
+ (1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET)
+
/* HPIPE register */
#define HPIPE_PWR_PLL_REG 0x4
#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
@@ -88,7 +104,13 @@
#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
(0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
-#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
+#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18
+#define HPIPE_SQUELCH_THRESH_IN_OFFSET 8
+#define HPIPE_SQUELCH_THRESH_IN_MASK \
+ (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET)
+#define HPIPE_SQUELCH_DETECTED_OFFSET 14
+#define HPIPE_SQUELCH_DETECTED_MASK \
+ (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET)
#define HPIPE_DFE_REG0 0x01C
#define HPIPE_DFE_RES_FORCE_OFFSET 15
@@ -215,10 +237,32 @@
#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
(0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
+#define HPIPE_PHY_TEST_CONTROL_REG 0x54
+#define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4
+#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \
+ (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET)
+#define HPIPE_PHY_TEST_RESET_OFFSET 14
+#define HPIPE_PHY_TEST_RESET_MASK \
+ (0x1 << HPIPE_PHY_TEST_RESET_OFFSET)
+#define HPIPE_PHY_TEST_EN_OFFSET 15
+#define HPIPE_PHY_TEST_EN_MASK \
+ (0x1 << HPIPE_PHY_TEST_EN_OFFSET)
+
+#define HPIPE_PHY_TEST_DATA_REG 0x6c
+#define HPIPE_PHY_TEST_DATA_OFFSET 0
+#define HPIPE_PHY_TEST_DATA_MASK \
+ (0xffff << HPIPE_PHY_TEST_DATA_OFFSET)
+
#define HPIPE_LOOPBACK_REG 0x08c
#define HPIPE_LOOPBACK_SEL_OFFSET 1
#define HPIPE_LOOPBACK_SEL_MASK \
(0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
+#define HPIPE_CDR_LOCK_OFFSET 7
+#define HPIPE_CDR_LOCK_MASK \
+ (0x1 << HPIPE_CDR_LOCK_OFFSET)
+#define HPIPE_CDR_LOCK_DET_EN_OFFSET 8
+#define HPIPE_CDR_LOCK_DET_EN_MASK \
+ (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)
#define HPIPE_SYNC_PATTERN_REG 0x090
#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10
@@ -382,6 +426,17 @@
#define HPIPE_OS_PH_VALID_MASK \
(0x1 << HPIPE_OS_PH_VALID_OFFSET)
+#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8
+#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0
+#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \
+ (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET)
+#define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4
+#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \
+ (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET)
+#define HPIPE_SQ_DEGLITCH_EN_OFFSET 8
+#define HPIPE_SQ_DEGLITCH_EN_MASK \
+ (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET)
+
#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
#define HPIPE_TRAIN_PAT_NUM_MASK \
@@ -452,6 +507,11 @@
#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
(0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
+#define HPIPE_SAVED_DFE_VALUES_REG 0x328
+#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10
+#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \
+ (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET)
+
#define HPIPE_CDR_CONTROL_REG 0x418
#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
diff --git a/include/mvebu/comphy.h b/include/mvebu/comphy.h
index cde7a022af1c..4d1b70393b20 100644
--- a/include/mvebu/comphy.h
+++ b/include/mvebu/comphy.h
@@ -16,7 +16,7 @@ struct comphy_map {
bool end_point;
};
+int comphy_rx_training(struct udevice *dev, u32 lane);
int comphy_update_map(struct comphy_map *serdes_map, int count);
#endif /* _MVEBU_COMPHY_H_ */
-
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 08/23] phy: marvell: add RX training command
2021-03-24 14:06 ` [PATCH v1 08/23] phy: marvell: add RX training command Stefan Roese
@ 2021-03-24 17:46 ` Marek Behun
2021-04-08 8:46 ` Stefan Roese
0 siblings, 1 reply; 39+ messages in thread
From: Marek Behun @ 2021-03-24 17:46 UTC (permalink / raw)
To: u-boot
On Wed, 24 Mar 2021 15:06:34 +0100
Stefan Roese <sr@denx.de> wrote:
> From: Igal Liberman <igall@marvell.com>
>
> This patch adds support for running RX training using new command called
> "rx_training"
> Usage:
> rx_training - rx_training <cp id> <comphy id>
>
> RX training allows to improve link quality (for SFI mode)
> by running training sequence between us and the link partner,
> this allows to reach better link quality then using static configuration.
PLEASE do not add another vendor specific command. PLEASE !
Create a generic command, with name 'ddr' or something, with API and
documentation.
Also the name "rx_training" is the worst thing ever. It could be
interpreted as training for RX on ethernet PHY, or even on UART.
Maybe people from Marvell could work more on their cooperation with
community. It is not terrible, but it is bad. There are hundreds if not
thousand of patches in their SDKs for both U-Boot and Linux. It is a
nightmare.
Marek
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 08/23] phy: marvell: add RX training command
2021-03-24 17:46 ` Marek Behun
@ 2021-04-08 8:46 ` Stefan Roese
0 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-04-08 8:46 UTC (permalink / raw)
To: u-boot
Hi Marek,
On 24.03.21 18:46, Marek Behun wrote:
> On Wed, 24 Mar 2021 15:06:34 +0100
> Stefan Roese <sr@denx.de> wrote:
>
>> From: Igal Liberman <igall@marvell.com>
>>
>> This patch adds support for running RX training using new command called
>> "rx_training"
>> Usage:
>> rx_training - rx_training <cp id> <comphy id>
>>
>> RX training allows to improve link quality (for SFI mode)
>> by running training sequence between us and the link partner,
>> this allows to reach better link quality then using static configuration.
>
> PLEASE do not add another vendor specific command. PLEASE !
Why not? We have many vendor specific commands in U-Boot. We also have
board specific commands as well.
I agree that generic / common commands should be implemented in a way,
that they can be used by all platforms. But this is not possible or
for all commands. And this command does not look very "generic" at least
not to me.
> Create a generic command, with name 'ddr' or something, with API and
> documentation.
>
> Also the name "rx_training" is the worst thing ever. It could be
> interpreted as training for RX on ethernet PHY, or even on UART.
"RX" is of course not very specific, I agree. AFAICT, only
comphy_cp110_sfi_rx_training() is supported (right now). Not sure if
this will be extended at a later time. Perhaps using something like
"comphy_rx_training" would be more suitable?
Thanks,
Stefan
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 09/23] phy: marvell: enable comphy info prints for all devices
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (7 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 08/23] phy: marvell: add RX training command Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 10/23] phy: marvell: cp110: remove unused definitions Stefan Roese
` (14 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index b29decd82693..45dba738662c 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -186,8 +186,7 @@ static int comphy_probe(struct udevice *dev)
/* PHY power UP sequence */
chip_cfg->ptr_comphy_chip_init(chip_cfg, chip_cfg->comphy_map_data);
/* PHY print SerDes status */
- if (of_machine_is_compatible("marvell,armada8040"))
- printf("Comphy chip #%d:\n", chip_cfg->cp_index);
+ printf("Comphy chip #%d:\n", chip_cfg->cp_index);
comphy_print(chip_cfg, chip_cfg->comphy_map_data);
/*
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 10/23] phy: marvell: cp110: remove unused definitions
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (8 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 09/23] phy: marvell: enable comphy info prints for all devices Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 11/23] phy: marvell: cp110: let the firmware configure comphy for RXAUI Stefan Roese
` (13 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Marcin Wojtas <mw@semihalf.com>
Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of
1.5G/3G/6.25G were referenced in the driver non configuration (dts)
was using it.
This patch removes unused definitions.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/arm/dts/armada-8040-mcbin.dts | 2 +-
drivers/phy/marvell/comphy_core.c | 14 +++----
drivers/phy/marvell/comphy_cp110.c | 3 --
include/dt-bindings/comphy/comphy_data.h | 50 ++++++++++--------------
4 files changed, 27 insertions(+), 42 deletions(-)
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index 98a582df26fe..a6ef40138da3 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -302,7 +302,7 @@
phy-type = <COMPHY_TYPE_SFI>;
};
phy5 {
- phy-type = <COMPHY_TYPE_SGMII3>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
phy-speed = <COMPHY_SPEED_3_125G>;
};
};
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 45dba738662c..929360792630 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -24,9 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
static const char *get_speed_string(u32 speed)
{
static const char * const speed_strings[] = {
- "1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
- "3.0 Gbps", "3.125 Gbps", "5 Gbps",
- "5.125 Gpbs", "6 Gbps", "6.25 Gbps",
+ "1.25 Gbps", "2.5 Gbps", "3.125 Gbps",
+ "5 Gbps", "5.125 Gpbs", "6 Gbps",
"10.3125 Gbps"
};
@@ -40,11 +39,10 @@ static const char *get_type_string(u32 type)
{
static const char * const type_strings[] = {
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
- "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
- "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3"
- "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
- "XAUI0", "XAUI1", "XAUI2", "XAUI3",
- "RXAUI0", "RXAUI1", "SFI", "IGNORE"
+ "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
+ "USB3", "USB3_HOST0", "USB3_HOST1",
+ "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP",
+ "IGNORE"
};
if (type < 0 || type > COMPHY_TYPE_MAX)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 11dc46b28a63..620a749bb1f8 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -1130,8 +1130,6 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
break;
case COMPHY_TYPE_SATA0:
case COMPHY_TYPE_SATA1:
- case COMPHY_TYPE_SATA2:
- case COMPHY_TYPE_SATA3:
mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
ret = comphy_sata_power_up(lane, hpipe_base_addr,
comphy_base_addr,
@@ -1166,7 +1164,6 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
mode);
break;
case COMPHY_TYPE_SGMII2:
- case COMPHY_TYPE_SGMII3:
if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
lane);
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
index 7d62dcf7fa51..8e9270598924 100644
--- a/include/dt-bindings/comphy/comphy_data.h
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -7,16 +7,13 @@
#define _COMPHY_DATA_H_
#define COMPHY_SPEED_1_25G 0
-#define COMPHY_SPEED_1_5G 1
-#define COMPHY_SPEED_2_5G 2
-#define COMPHY_SPEED_3G 3
-#define COMPHY_SPEED_3_125G 4
-#define COMPHY_SPEED_5G 5
-#define COMPHY_SPEED_5_15625G 6
-#define COMPHY_SPEED_6G 7
-#define COMPHY_SPEED_6_25G 8
-#define COMPHY_SPEED_10_3125G 9
-#define COMPHY_SPEED_MAX 10
+#define COMPHY_SPEED_2_5G 1
+#define COMPHY_SPEED_3_125G 2
+#define COMPHY_SPEED_5G 3
+#define COMPHY_SPEED_5_15625G 4
+#define COMPHY_SPEED_6G 5
+#define COMPHY_SPEED_10_3125G 6
+#define COMPHY_SPEED_MAX 7
#define COMPHY_SPEED_INVALID 0xff
#define COMPHY_TYPE_UNCONNECTED 0
@@ -26,26 +23,19 @@
#define COMPHY_TYPE_PEX3 4
#define COMPHY_TYPE_SATA0 5
#define COMPHY_TYPE_SATA1 6
-#define COMPHY_TYPE_SATA2 7
-#define COMPHY_TYPE_SATA3 8
-#define COMPHY_TYPE_SGMII0 9
-#define COMPHY_TYPE_SGMII1 10
-#define COMPHY_TYPE_SGMII2 11
-#define COMPHY_TYPE_SGMII3 12
-#define COMPHY_TYPE_QSGMII 13
-#define COMPHY_TYPE_USB3 14
-#define COMPHY_TYPE_USB3_HOST0 15
-#define COMPHY_TYPE_USB3_HOST1 16
-#define COMPHY_TYPE_USB3_DEVICE 17
-#define COMPHY_TYPE_XAUI0 18
-#define COMPHY_TYPE_XAUI1 19
-#define COMPHY_TYPE_XAUI2 20
-#define COMPHY_TYPE_XAUI3 21
-#define COMPHY_TYPE_RXAUI0 22
-#define COMPHY_TYPE_RXAUI1 23
-#define COMPHY_TYPE_SFI 24
-#define COMPHY_TYPE_IGNORE 25
-#define COMPHY_TYPE_MAX 26
+#define COMPHY_TYPE_SGMII0 7
+#define COMPHY_TYPE_SGMII1 8
+#define COMPHY_TYPE_SGMII2 9
+#define COMPHY_TYPE_USB3 10
+#define COMPHY_TYPE_USB3_HOST0 11
+#define COMPHY_TYPE_USB3_HOST1 12
+#define COMPHY_TYPE_USB3_DEVICE 13
+#define COMPHY_TYPE_RXAUI0 14
+#define COMPHY_TYPE_RXAUI1 15
+#define COMPHY_TYPE_SFI 16
+#define COMPHY_TYPE_AP 17
+#define COMPHY_TYPE_IGNORE 18
+#define COMPHY_TYPE_MAX 19
#define COMPHY_TYPE_INVALID 0xff
#define COMPHY_POLARITY_NO_INVERT 0
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 11/23] phy: marvell: cp110: let the firmware configure comphy for RXAUI
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (9 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 10/23] phy: marvell: cp110: remove unused definitions Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 12/23] phy: marvell: cp110: let the firmware configure comphy for USB Stefan Roese
` (12 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Replace the comphy initialization for RXAUI with appropriate SMC call,
so the firmware will execute required serdes configuration.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 184 +----------------------------
1 file changed, 4 insertions(+), 180 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 620a749bb1f8..9f80a3fda4b1 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -559,184 +559,6 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
return ret;
}
-static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
-
- debug_enter();
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- if (lane == 2) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
- COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
- }
- if (lane == 4) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
- COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
- }
-
- /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
- mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
- data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
- data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
-
- /* release from hard reset */
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
-
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* set reference clock */
- reg_set(hpipe_addr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
- /* Power and PLL Control */
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
- /* Loopback register */
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
- /* rx control 1 */
- mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
- data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
- mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
- data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
- /* DTL Control */
- reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
- 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
- HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
-
- /* Set analog paramters from ETP(HW) */
- debug("stage: Analog paramters from ETP(HW)\n");
- /* SERDES External Configuration 2 */
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
- 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
- SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
- /* 0x7-DFE Resolution control */
- reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
- HPIPE_DFE_RES_FORCE_MASK);
- /* 0xd-G1_Setting_0 */
- reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
- 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
- HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
- /* 0xE-G1_Setting_1 */
- mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
- data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
- /* 0xA-DFE_Reg3 */
- mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
- data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
- mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
- data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
- reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
-
- /* 0x111-G1_Setting_4 */
- mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
- data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
-
- debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
- /* SERDES External Configuration */
- mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
-
-
- /* check PLL rx & tx ready */
- addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
- data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
- SD_EXTERNAL_STATUS0_PLL_TX_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
- pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
- (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
- (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
- ret = 0;
- }
-
- /* RX init */
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
- 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
- SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
-
- /* check that RX init done */
- addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
- data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 100);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
- pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
- ret = 0;
- }
-
- debug("stage: RF Reset\n");
- /* RF Reset */
- mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- debug_exit();
- return ret;
-}
-
static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr,
@@ -1187,8 +1009,10 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
break;
case COMPHY_TYPE_RXAUI0:
case COMPHY_TYPE_RXAUI1:
- ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane,
+ mode);
break;
default:
debug("Unknown SerDes type, skip initialize SerDes %d\n",
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 12/23] phy: marvell: cp110: let the firmware configure comphy for USB
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (10 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 11/23] phy: marvell: cp110: let the firmware configure comphy for RXAUI Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 13/23] phy: marvell: cp110: let the firmware perform training for XFI Stefan Roese
` (11 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Replace the comphy initialization for USB with appropriate SMC call,
so the firmware will execute required serdes configuration.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 133 ++---------------------------
1 file changed, 9 insertions(+), 124 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 9f80a3fda4b1..cbfc89cb0c36 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -323,128 +323,6 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
return ret;
}
-static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
-
- debug_enter();
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- mask |= COMMON_PHY_PHY_MODE_MASK;
- data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* release from hard reset */
- mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
-
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* Set PIPE soft reset */
- mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
- data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
- /* Set PHY datapath width mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
- /* Set Data bus width USB mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
- /* Set CORE_CLK output frequency for 250Mhz */
- mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
- /* Set PLL ready delay for 0x2 */
- reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
- 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
- HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
- /* Set reference clock to come from group 1 - 25Mhz */
- reg_set(hpipe_addr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
- /* Set reference frequcency select - 0x2 */
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- /* Set PHY mode to USB - 0x5 */
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
- /* Set the amount of time spent in the LoZ state - set for 0x7 */
- reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
- 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
- HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
- /* Set max PHY generation setting - 5Gbps */
- reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
- 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
- HPIPE_INTERFACE_GEN_MAX_MASK);
- /* Set select data width 20Bit (SEL_BITS[2:0]) */
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
- HPIPE_LOOPBACK_SEL_MASK);
- /* select de-emphasize 3.5db */
- reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
- 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
- HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
- /* override tx margining from the MAC */
- reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
- 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
- HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
-
- /* Start analog paramters from ETP(HW) */
- debug("stage: Analog paramters from ETP(HW)\n");
- /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
- mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
- data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
- /* Set Override PHY DFE control pins for 0x1 */
- mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
- data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
- /* Set Spread Spectrum Clock Enable fot 0x1 */
- mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
- data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
- /* End of analog parameters */
-
- debug("stage: Comphy power up\n");
- /* Release from PIPE soft reset */
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
- 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
-
- /* wait 15ms - for comphy calibration done */
- debug("stage: Check PLL\n");
- /* Read lane status */
- addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
- data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
- pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
- ret = 0;
- }
-
- debug_exit();
- return ret;
-}
-
static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
u32 lane, u32 mode)
{
@@ -960,9 +838,16 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
break;
case COMPHY_TYPE_USB3_HOST0:
case COMPHY_TYPE_USB3_HOST1:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane,
+ mode);
+ break;
case COMPHY_TYPE_USB3_DEVICE:
- ret = comphy_usb3_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane,
+ mode);
break;
case COMPHY_TYPE_SGMII0:
case COMPHY_TYPE_SGMII1:
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 13/23] phy: marvell: cp110: let the firmware perform training for XFI
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (11 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 12/23] phy: marvell: cp110: let the firmware configure comphy for USB Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 14/23] phy: marvell: cp110: remove both phy and pipe selector configuration Stefan Roese
` (10 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Replace the XFI training with appropriate SMC call, so the firmware will
perform exact initialization.
Update Stefan 2021-03-23:
Move comphy_smc() function to an earlier place - necessary for the
mainline merge.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Igal Liberman <igall@marvell.com>
---
drivers/phy/marvell/comphy_cp110.c | 197 +++--------------------------
1 file changed, 18 insertions(+), 179 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index cbfc89cb0c36..e71b70428464 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -28,6 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define MV_SIP_COMPHY_POWER_ON 0x82000001
#define MV_SIP_COMPHY_POWER_OFF 0x82000002
#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
+#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
/* Used to distinguish between different possible callers (U-boot/Linux) */
#define COMPHY_CALLER_UBOOT (0x1 << 21)
@@ -133,90 +134,24 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val,
return 0;
}
-/* This function performs RX training for single FFE value.
- * The result of the RX training is located in:
- * Saved DFE values Register[10:15].
- *
- * The result is returned to the caller using *result
- *
- * Return '1' on succsess.
- * Return '0' on failure.
- */
-static int comphy_cp110_test_single_ffe(
- struct chip_serdes_phy_config *ptr_chip_cfg,
- u32 lane, u32 ffe, u32 *result)
+static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
+ u32 lane, u32 mode)
{
- u32 mask, data, timeout;
- void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane);
- void __iomem *sd_ip_addr = SD_ADDR(hpipe_base_addr, lane);
-
- /* Configure PRBS counters */
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_DATA_MASK;
- data = 0x64 << HPIPE_PHY_TEST_DATA_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_EN_MASK;
- data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mdelay(50);
-
- /* Set the FFE value */
- mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
- data = ffe << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
-
- /* Start RX training */
- mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK;
- data = 1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask);
-
- /* Check the result of RX training */
- timeout = RX_TRAINING_TIMEOUT;
- while (timeout) {
- data = readl(sd_ip_addr + SD_EXTERNAL_STATUS1_REG);
- if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK)
- break;
- mdelay(1);
- timeout--;
- }
-
- if (timeout == 0)
- return 0;
-
- if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK)
- return 0;
-
- /* Stop RX training */
- mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK;
- data = 0 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask);
-
- /* Read the result */
- data = readl(hpipe_addr + HPIPE_SAVED_DFE_VALUES_REG);
- data &= HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK;
- data >>= HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET;
- *result = data;
-
- printf("FFE = %d, result = 0x%x\n", ffe, *result);
+ struct pt_regs pregs = {0};
- /* Clear the PRBS counters */
- mask = HPIPE_PHY_TEST_RESET_MASK;
- data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET;
- mask |= HPIPE_PHY_TEST_EN_MASK;
- data |= 0x0 << HPIPE_PHY_TEST_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
+ pregs.regs[0] = function_id;
+ pregs.regs[1] = (unsigned long)comphy_base_addr;
+ pregs.regs[2] = lane;
+ pregs.regs[3] = mode;
- mask = HPIPE_PHY_TEST_RESET_MASK;
- data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
+ smc_call(&pregs);
- return 1;
+ /*
+ * TODO: Firmware return 0 on success, temporary map it to u-boot
+ * convention, but after all comphy will be reworked the convention in
+ * u-boot should be change and this conversion removed
+ */
+ return pregs.regs[0] ? 0 : 1;
}
/* This function performs RX training for all FFE possible values.
@@ -229,10 +164,6 @@ static int comphy_cp110_test_single_ffe(
int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
u32 lane)
{
- u32 mask, data, i, rx_train_result;
- u32 max_rx_train = 0, max_rx_train_index = 0;
- void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane);
int ret;
debug_enter();
@@ -242,107 +173,15 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
return 0;
}
- /* Configure SQ threshold and CDR lock */
- mask = HPIPE_SQUELCH_THRESH_IN_MASK;
- data = 0xc << HPIPE_SQUELCH_THRESH_IN_OFFSET;
- reg_set(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG, data, mask);
-
- mask = HPIPE_SQ_DEGLITCH_WIDTH_P_MASK;
- data = 0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET;
- mask |= HPIPE_SQ_DEGLITCH_WIDTH_N_MASK;
- data |= 0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET;
- mask |= HPIPE_SQ_DEGLITCH_EN_MASK;
- data |= 0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_SQ_GLITCH_FILTER_CTRL, data, mask);
-
- mask = HPIPE_CDR_LOCK_DET_EN_MASK;
- data = 0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
-
- udelay(100);
-
- /* Determine if we have a cable attached to this comphy, if not,
- * we can't perform RX training.
- */
- data = readl(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG);
- if (data & HPIPE_SQUELCH_DETECTED_MASK) {
- pr_err("Squelsh is not detected, can't perform RX training\n");
- return 0;
- }
-
- data = readl(hpipe_addr + HPIPE_LOOPBACK_REG);
- if (!(data & HPIPE_CDR_LOCK_MASK)) {
- pr_err("CDR is not locked, can't perform RX training\n");
- return 0;
- }
-
- /* Do preparations for RX training */
- mask = HPIPE_DFE_RES_FORCE_MASK;
- data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
- reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
-
- mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
- data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
- mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
- data |= 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
-
- /* Performs RX training for all possible FFE (Feed Forward
- * Equalization, possible values are 0-7).
- * We update the best value reached and the FFE which gave this value.
- */
- for (i = 0; i < MAX_NUM_OF_FFE; i++) {
- rx_train_result = 0;
- ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane,
- i, &rx_train_result);
-
- if (ret && (rx_train_result > max_rx_train)) {
- max_rx_train = rx_train_result;
- max_rx_train_index = i;
- }
- }
-
- /* If we were able to determine which FFE gives the best value,
- * now we need to set it and run RX training again (only for this
- * FFE).
- */
- if (max_rx_train) {
- ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane,
- max_rx_train_index,
- &rx_train_result);
- if (ret == 1)
- printf("RX Training passed(FFE = %d, result = 0x%x)\n",
- max_rx_train_index, rx_train_result);
- } else {
- pr_err("RX training failed\n");
- ret = 0;
- }
+ /* Mode is not relevant for xfi training */
+ ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN,
+ ptr_chip_cfg->comphy_base_addr, lane, 0);
debug_exit();
return ret;
}
-static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
- u32 lane, u32 mode)
-{
- struct pt_regs pregs = {0};
-
- pregs.regs[0] = function_id;
- pregs.regs[1] = (unsigned long)comphy_base_addr;
- pregs.regs[2] = lane;
- pregs.regs[3] = mode;
-
- smc_call(&pregs);
-
- /*
- * TODO: Firmware return 0 on success, temporary map it to u-boot
- * convention, but after all comphy will be reworked the convention in
- * u-boot should be change and this conversion removed
- */
- return pregs.regs[0] ? 0 : 1;
-}
-
static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
void __iomem *comphy_base_addr, int cp_index,
u32 type)
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 14/23] phy: marvell: cp110: remove both phy and pipe selector configuration
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (12 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 13/23] phy: marvell: cp110: let the firmware perform training for XFI Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 15/23] phy: marvell: cp110: clean up driver after it was moved to atf Stefan Roese
` (9 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Now the comphy configuration is handled in atf, therefore there is no
need to configure phy or pipe selector in u-boot, it is configured by
atf for each particular pair: lane and mode.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 94 ------------------------------
1 file changed, 94 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index e71b70428464..195b455241fa 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -66,58 +66,6 @@ struct utmi_phy_data {
u32 utmi_phy_port;
};
-/*
- * For CP-110 we have 2 Selector registers "PHY Selectors",
- * and "PIPE Selectors".
- * PIPE selector include USB and PCIe options.
- * PHY selector include the Ethernet and SATA options, every Ethernet
- * option has different options, for example: serdes lane2 had option
- * Eth_port_0 that include (SGMII0, RXAUI0, SFI)
- */
-struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
- /* Lane 0 */
- {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1},
- {COMPHY_TYPE_SATA1, 0x4} } },
- /* Lane 1 */
- {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
- {COMPHY_TYPE_SATA0, 0x4} } },
- /* Lane 2 */
- {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1},
- {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1},
- {COMPHY_TYPE_SATA0, 0x4} } },
- /* Lane 3 */
- {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1},
- {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } },
- /* Lane 4 */
- {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2},
- {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2},
- {COMPHY_TYPE_SGMII1, 0x1} } },
- /* Lane 5 */
- {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
- {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } },
-};
-
-struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
- /* Lane 0 */
- {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX0, 0x4} } },
- /* Lane 1 */
- {4, {{COMPHY_TYPE_UNCONNECTED, 0x0},
- {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_USB3_DEVICE, 0x2},
- {COMPHY_TYPE_PEX0, 0x4} } },
- /* Lane 2 */
- {3, {{COMPHY_TYPE_UNCONNECTED, 0x0},
- {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } },
- /* Lane 3 */
- {3, {{COMPHY_TYPE_UNCONNECTED, 0x0},
- {COMPHY_TYPE_USB3_HOST1, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } },
- /* Lane 4 */
- {4, {{COMPHY_TYPE_UNCONNECTED, 0x0},
- {COMPHY_TYPE_USB3_HOST1, 0x1},
- {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PEX1, 0x4} } },
- /* Lane 5 */
- {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX2, 0x4} } },
-};
-
static u32 polling_with_timeout(void __iomem *addr, u32 val,
u32 mask, unsigned long usec_timout)
{
@@ -574,45 +522,6 @@ void comphy_dedicated_phys_init(void)
debug_exit();
}
-static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map)
-{
- void __iomem *comphy_base_addr;
- struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
- struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
- u32 lane, comphy_max_count;
-
- comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
- comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
-
- /*
- * Copy the SerDes map configuration for PIPE map and PHY map
- * the comphy_mux_init modify the type of the lane if the type
- * is not valid because we have 2 selectores run the
- * comphy_mux_init twice and after that update the original
- * serdes_map
- */
- for (lane = 0; lane < comphy_max_count; lane++) {
- comphy_map_pipe_data[lane].type = serdes_map[lane].type;
- comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
- comphy_map_phy_data[lane].type = serdes_map[lane].type;
- comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
- }
- ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
- comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
- comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
-
- ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
- comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
- comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
- /* Fix the type after check the PHY and PIPE configuration */
- for (lane = 0; lane < comphy_max_count; lane++) {
- if ((comphy_map_pipe_data[lane].type == COMPHY_TYPE_UNCONNECTED) &&
- (comphy_map_phy_data[lane].type == COMPHY_TYPE_UNCONNECTED))
- serdes_map[lane].type = COMPHY_TYPE_UNCONNECTED;
- }
-}
-
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
{
@@ -628,9 +537,6 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
- /* Config Comphy mux configuration */
- comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
-
/* Check if the first 4 lanes configured as By-4 */
for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
lane++, ptr_comphy_map++) {
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 15/23] phy: marvell: cp110: clean up driver after it was moved to atf
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (13 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 14/23] phy: marvell: cp110: remove both phy and pipe selector configuration Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 16/23] phy: marvell: pass sgmii id to firmware Stefan Roese
` (8 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_a3700.h | 1 -
drivers/phy/marvell/comphy_core.h | 50 --
drivers/phy/marvell/comphy_cp110.c | 5 -
drivers/phy/marvell/comphy_hpipe.h | 720 -----------------------------
drivers/phy/marvell/comphy_mux.c | 1 -
5 files changed, 777 deletions(-)
delete mode 100644 drivers/phy/marvell/comphy_hpipe.h
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index b0941ffb37fb..8748c6c84ae6 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -7,7 +7,6 @@
#define _COMPHY_A3700_H_
#include "comphy_core.h"
-#include "comphy_hpipe.h"
#define MVEBU_REG(offs) \
((void __iomem *)(ulong)MVEBU_REGISTER(offs))
diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h
index 32895dc4aa3d..3ac4985e7976 100644
--- a/drivers/phy/marvell/comphy_core.h
+++ b/drivers/phy/marvell/comphy_core.h
@@ -17,56 +17,6 @@
#define debug_exit()
#endif
-/* COMPHY registers */
-#define COMMON_PHY_CFG1_REG 0x0
-#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
-#define COMMON_PHY_CFG1_PWR_UP_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
-#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
-#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
- (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
-#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
-#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
-#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
-#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
- (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
-#define COMMON_PHY_PHY_MODE_OFFSET 15
-#define COMMON_PHY_PHY_MODE_MASK \
- (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
-
-#define COMMON_PHY_CFG6_REG 0x14
-#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
-#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
- (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
-
-#define COMMON_SELECTOR_PHY_OFFSET 0x140
-#define COMMON_SELECTOR_PIPE_OFFSET 0x144
-
-#define COMMON_PHY_SD_CTRL1 0x148
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
-#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
-#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
-
-/* ToDo: Get this address via DT */
-#define MVEBU_CP0_REGS_BASE 0xF2000000UL
-
-#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
-#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
-#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
- (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
-
#define MAX_LANE_OPTIONS 10
#define MAX_UTMI_PHY_COUNT 3
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 195b455241fa..2a22a67a4656 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -14,16 +14,11 @@
#include <linux/delay.h>
#include "comphy_core.h"
-#include "comphy_hpipe.h"
#include "sata.h"
#include "utmi_phy.h"
DECLARE_GLOBAL_DATA_PTR;
-#define SD_ADDR(base, lane) (base + 0x1000 * lane)
-#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
-#define COMPHY_ADDR(base, lane) (base + 0x28 * lane)
-
/* Firmware related definitions used for SMC calls */
#define MV_SIP_COMPHY_POWER_ON 0x82000001
#define MV_SIP_COMPHY_POWER_OFF 0x82000002
diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
deleted file mode 100644
index cf2f986281ea..000000000000
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ /dev/null
@@ -1,720 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Marvell International Ltd.
- */
-
-#ifndef _COMPHY_HPIPE_H_
-#define _COMPHY_HPIPE_H_
-
-#define MAX_NUM_OF_FFE 8
-#define RX_TRAINING_TIMEOUT 500
-
-/* SerDes IP register */
-#define SD_EXTERNAL_CONFIG0_REG 0
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
- (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
- (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
- (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
-
-#define SD_EXTERNAL_CONFIG1_REG 0x4
-#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
-#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
-
-#define SD_EXTERNAL_CONFIG2_REG 0x8
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
-
-#define SD_EXTERNAL_STATUS_REG 0xc
-#define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7
-#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \
- (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET)
-
-#define SD_EXTERNAL_STATUS0_REG 0x18
-#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
-#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
-#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
-#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
-#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
-
-#define SD_EXTERNAL_STATUS1_REG 0x1c
-#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET 0
-#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK \
- (1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET)
-#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET 1
-#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK \
- (1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET)
-
-/* HPIPE register */
-#define HPIPE_PWR_PLL_REG 0x4
-#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
-#define HPIPE_PWR_PLL_REF_FREQ_MASK \
- (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
-#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
-#define HPIPE_PWR_PLL_PHY_MODE_MASK \
- (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
-
-#define HPIPE_KVCO_CALIB_CTRL_REG 0x8
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
- (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
-
-#define HPIPE_CAL_REG1_REG 0xc
-#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
-#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
- (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
- (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
-
-#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18
-#define HPIPE_SQUELCH_THRESH_IN_OFFSET 8
-#define HPIPE_SQUELCH_THRESH_IN_MASK \
- (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET)
-#define HPIPE_SQUELCH_DETECTED_OFFSET 14
-#define HPIPE_SQUELCH_DETECTED_MASK \
- (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET)
-
-#define HPIPE_DFE_REG0 0x01C
-#define HPIPE_DFE_RES_FORCE_OFFSET 15
-#define HPIPE_DFE_RES_FORCE_MASK \
- (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
-
-#define HPIPE_DFE_F3_F5_REG 0x028
-#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
-#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
- (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
-#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
-#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
- (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
-
-#define HPIPE_G1_SET_0_REG 0x034
-#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
-#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
- (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
- (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
-
-#define HPIPE_G1_SET_1_REG 0x038
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
-#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
-#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
-
-#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
-
-#define HPIPE_G2_SET_0_REG 0x3c
-#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
-#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
- (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
- (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
-
-#define HPIPE_G2_SET_1_REG 0x040
-#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
-#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
-#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
-#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
-#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
-
-#define HPIPE_G3_SET_0_REG 0x44
-#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
-#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
- (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
- (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
-#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
- (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
-#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
-
-#define HPIPE_G3_SET_1_REG 0x048
-#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
-#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
-#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
- (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
-#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
-#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
-#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
-#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
-#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
- (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
-
-#define HPIPE_PHY_TEST_CONTROL_REG 0x54
-#define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4
-#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \
- (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET)
-#define HPIPE_PHY_TEST_RESET_OFFSET 14
-#define HPIPE_PHY_TEST_RESET_MASK \
- (0x1 << HPIPE_PHY_TEST_RESET_OFFSET)
-#define HPIPE_PHY_TEST_EN_OFFSET 15
-#define HPIPE_PHY_TEST_EN_MASK \
- (0x1 << HPIPE_PHY_TEST_EN_OFFSET)
-
-#define HPIPE_PHY_TEST_DATA_REG 0x6c
-#define HPIPE_PHY_TEST_DATA_OFFSET 0
-#define HPIPE_PHY_TEST_DATA_MASK \
- (0xffff << HPIPE_PHY_TEST_DATA_OFFSET)
-
-#define HPIPE_LOOPBACK_REG 0x08c
-#define HPIPE_LOOPBACK_SEL_OFFSET 1
-#define HPIPE_LOOPBACK_SEL_MASK \
- (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
-#define HPIPE_CDR_LOCK_OFFSET 7
-#define HPIPE_CDR_LOCK_MASK \
- (0x1 << HPIPE_CDR_LOCK_OFFSET)
-#define HPIPE_CDR_LOCK_DET_EN_OFFSET 8
-#define HPIPE_CDR_LOCK_DET_EN_MASK \
- (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)
-
-#define HPIPE_SYNC_PATTERN_REG 0x090
-#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10
-#define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \
- (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET)
-#define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11
-#define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \
- (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET)
-
-#define HPIPE_INTERFACE_REG 0x94
-#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
-#define HPIPE_INTERFACE_GEN_MAX_MASK \
- (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
-#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
-#define HPIPE_INTERFACE_DET_BYPASS_MASK \
- (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
-#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
-#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
- (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
-
-#define HPIPE_ISOLATE_MODE_REG 0x98
-#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
-#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
- (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
-#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
-#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
- (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
-
-#define HPIPE_G1_SET_2_REG 0xf4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
- (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
- (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
-
-#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
-
-#define HPIPE_VDD_CAL_CTRL_REG 0x114
-#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
-#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
- (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
-
-#define HPIPE_VDD_CAL_0_REG 0x108
-#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
-#define HPIPE_CAL_VDD_CONT_MODE_MASK \
- (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
-
-#define HPIPE_PCIE_REG0 0x120
-#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
-#define HPIPE_PCIE_IDLE_SYNC_MASK \
- (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
-#define HPIPE_PCIE_SEL_BITS_OFFSET 13
-#define HPIPE_PCIE_SEL_BITS_MASK \
- (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
-
-#define HPIPE_LANE_ALIGN_REG 0x124
-#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
-#define HPIPE_LANE_ALIGN_OFF_MASK \
- (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
-
-#define HPIPE_MISC_REG 0x13C
-#define HPIPE_MISC_CLK100M_125M_OFFSET 4
-#define HPIPE_MISC_CLK100M_125M_MASK \
- (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
-#define HPIPE_MISC_ICP_FORCE_OFFSET 5
-#define HPIPE_MISC_ICP_FORCE_MASK \
- (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
-#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
-#define HPIPE_MISC_TXDCLK_2X_MASK \
- (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
-#define HPIPE_MISC_CLK500_EN_OFFSET 7
-#define HPIPE_MISC_CLK500_EN_MASK \
- (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
-#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
-#define HPIPE_MISC_REFCLK_SEL_MASK \
- (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
-
-#define HPIPE_RX_CONTROL_1_REG 0x140
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
- (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
- (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_REG 0x148
-#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
-#define HPIPE_PWR_CTR_RST_DFE_MASK \
- (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
-#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
-#define HPIPE_PWR_CTR_SFT_RST_MASK \
- (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
-
-#define HPIPE_SPD_DIV_FORCE_REG 0x154
-#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
-#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
- (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
- (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
- (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
- (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
- (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
-
-#define HPIPE_PLLINTP_REG1 0x150
-
-#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
-#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
-#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
- (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
-#define HPIPE_SMAPLER_OFFSET 12
-#define HPIPE_SMAPLER_MASK \
- (0x1 << HPIPE_SMAPLER_OFFSET)
-
-#define HPIPE_TX_REG1_REG 0x174
-#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
-#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
- (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
-#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
-#define HPIPE_TX_REG1_SLC_EN_MASK \
- (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_DTL_REG 0x184
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
- (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
- (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
- (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
-
-#define HPIPE_PHASE_CONTROL_REG 0x188
-#define HPIPE_OS_PH_OFFSET_OFFSET 0
-#define HPIPE_OS_PH_OFFSET_MASK \
- (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
-#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
-#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
- (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
-#define HPIPE_OS_PH_VALID_OFFSET 8
-#define HPIPE_OS_PH_VALID_MASK \
- (0x1 << HPIPE_OS_PH_VALID_OFFSET)
-
-#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8
-#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0
-#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \
- (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET)
-#define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4
-#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \
- (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET)
-#define HPIPE_SQ_DEGLITCH_EN_OFFSET 8
-#define HPIPE_SQ_DEGLITCH_EN_MASK \
- (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
-#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
-#define HPIPE_TRAIN_PAT_NUM_MASK \
- (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
- (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
-
-#define HPIPE_DME_REG 0x228
-#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
-#define HPIPE_DME_ETHERNET_MODE_MASK \
- (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
-#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
-#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
- (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
-#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
-#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
-#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
-#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
-#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_TRX_TRAIN_TIMER_MASK \
- (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
-
-#define HPIPE_PCIE_REG1 0x288
-#define HPIPE_PCIE_REG3 0x290
-
-#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
-#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_RX_TRAIN_TIMER_MASK \
- (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
-#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
-#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
-
-#define HPIPE_TX_TRAIN_REG 0x31C
-#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
-#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
- (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
- (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
-#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
-#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
- (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
-
-#define HPIPE_SAVED_DFE_VALUES_REG 0x328
-#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10
-#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \
- (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET)
-
-#define HPIPE_CDR_CONTROL_REG 0x418
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
- (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
-#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
-#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
- (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
-#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
-#define HPIPE_TX_NUM_OF_PRESET_MASK \
- (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
-#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
-#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
- (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
-
-#define HPIPE_G1_SETTINGS_3_REG 0x440
-#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
- (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
-#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
- (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
- (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
- (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
- (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
- (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G1_SETTINGS_4_REG 0x444
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
- (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
-
-#define HPIPE_G2_SETTINGS_3_REG 0x448
-
-#define HPIPE_G2_SETTINGS_4_REG 0x44c
-#define HPIPE_G2_DFE_RES_OFFSET 8
-#define HPIPE_G2_DFE_RES_MASK \
- (0x3 << HPIPE_G2_DFE_RES_OFFSET)
-
-#define HPIPE_G3_SETTING_3_REG 0x450
-#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_G3_FFE_CAP_SEL_MASK \
- (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
-#define HPIPE_G3_FFE_RES_SEL_MASK \
- (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
-#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
- (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
- (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
- (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G3_SETTING_4_REG 0x454
-#define HPIPE_G3_DFE_RES_OFFSET 8
-#define HPIPE_G3_DFE_RES_MASK \
- (0x3 << HPIPE_G3_DFE_RES_OFFSET)
-
-#define HPIPE_TX_PRESET_INDEX_REG 0x468
-#define HPIPE_TX_PRESET_INDEX_OFFSET 0
-#define HPIPE_TX_PRESET_INDEX_MASK \
- (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
-
-#define HPIPE_DFE_CONTROL_REG 0x470
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
- (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
-
-#define HPIPE_DFE_CTRL_28_REG 0x49C
-#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
-#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
- (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
-
-#define HPIPE_G1_SETTING_5_REG 0x538
-#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
-#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
- (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
-
-#define HPIPE_G3_SETTING_5_REG 0x548
-#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
-#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
- (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
-
-#define HPIPE_LANE_CONFIG0_REG 0x600
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
- (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
-
-#define HPIPE_LANE_CONFIG1_REG 0x604
-#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
-#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
- (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
- (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
-
-#define HPIPE_LANE_STATUS1_REG 0x60C
-#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
-#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
- (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
-
-#define HPIPE_LANE_CFG4_REG 0x620
-#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
-#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
- (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
- (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
-#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
- (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
-#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
-#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
- (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
-
-#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
-#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
-#define HPIPE_CFG_PHY_RC_EP_MASK \
- (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
-
-#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
-#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
-#define HPIPE_CFG_UPDATE_POLARITY_MASK \
- (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
-
-#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
- (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
- (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
- (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
-
-#define HPIPE_RST_CLK_CTRL_REG 0x704
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
-
-#define HPIPE_TST_MODE_CTRL_REG 0x708
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
- (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
-
-#define HPIPE_CLK_SRC_LO_REG 0x70c
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
- (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
- (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
- (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
-
-#define HPIPE_CLK_SRC_HI_REG 0x710
-#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
-#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
-
-#define HPIPE_GLOBAL_MISC_CTRL 0x718
-#define HPIPE_GLOBAL_PM_CTRL 0x740
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
- (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
-
-#endif /* _COMPHY_HPIPE_H_ */
-
diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c
index aaef736b75dd..10981d25ec95 100644
--- a/drivers/phy/marvell/comphy_mux.c
+++ b/drivers/phy/marvell/comphy_mux.c
@@ -8,7 +8,6 @@
#include <asm/io.h>
#include "comphy_core.h"
-#include "comphy_hpipe.h"
/*
* comphy_mux_check_config()
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 16/23] phy: marvell: pass sgmii id to firmware
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (14 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 15/23] phy: marvell: cp110: clean up driver after it was moved to atf Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 17/23] phy: marvell: fix handling of unconnected comphy Stefan Roese
` (7 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
Currently, we don't pass id for SGMII 0/1.
A bug in comphy selector configuration was found (in comphy
firmware), after fixing it, SGMII0/1 have different configuration,
so we need to pass the ID the firmware.
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 27 +++++----------------------
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 2a22a67a4656..55202888194d 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -522,7 +522,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
{
struct comphy_map *ptr_comphy_map;
void __iomem *comphy_base_addr, *hpipe_base_addr;
- u32 comphy_max_count, lane, ret = 0;
+ u32 comphy_max_count, lane, id, ret = 0;
u32 pcie_width = 0;
u32 mode;
@@ -591,34 +591,17 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
break;
case COMPHY_TYPE_SGMII0:
case COMPHY_TYPE_SGMII1:
- if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
- debug("Warning: ");
- debug("SGMII PHY speed in lane %d is invalid,",
- lane);
- debug(" set PHY speed to 1.25G\n");
- ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
- }
-
- /*
- * UINIT_ID not relevant for SGMII0 and SGMII1 - will be
- * ignored by firmware
- */
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID0,
- ptr_comphy_map->speed);
- ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
- ptr_chip_cfg->comphy_base_addr, lane,
- mode);
- break;
case COMPHY_TYPE_SGMII2:
+ /* Calculate SGMII ID */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0;
+
if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
lane);
ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
}
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID2,
+ mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 17/23] phy: marvell: fix handling of unconnected comphy
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (15 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 16/23] phy: marvell: pass sgmii id to firmware Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 18/23] phy: marvell: cp110: mark u-boot power-off calls Stefan Roese
` (6 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Christine Gharzuzi <chrisg@marvell.com>
- the default value of comphy pipe selector is set to PCIe (x4)
in case of unconnected comphy the default value remains 0x4
which may lead to several issues with comphy initialization.
- this patch adds SMC call that powers off the comphy lane in case of
unconnected comphy.
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 55202888194d..d9a94f9d0d09 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -553,6 +553,10 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
}
switch (ptr_comphy_map->type) {
case COMPHY_TYPE_UNCONNECTED:
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF,
+ ptr_chip_cfg->comphy_base_addr,
+ lane,
+ ptr_comphy_map->type);
case COMPHY_TYPE_IGNORE:
continue;
break;
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 18/23] phy: marvell: cp110: mark u-boot power-off calls
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (16 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 17/23] phy: marvell: fix handling of unconnected comphy Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 19/23] phy: marvell: allow to initialize up to 6 USB ports Stefan Roese
` (5 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
It helps ATF to determine who called power off
function (U-boot/Linux) and act accordingly
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index d9a94f9d0d09..489a17c76f42 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -553,10 +553,10 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
}
switch (ptr_comphy_map->type) {
case COMPHY_TYPE_UNCONNECTED:
+ mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT;
ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF,
ptr_chip_cfg->comphy_base_addr,
- lane,
- ptr_comphy_map->type);
+ lane, mode);
case COMPHY_TYPE_IGNORE:
continue;
break;
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 19/23] phy: marvell: allow to initialize up to 6 USB ports
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (17 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 18/23] phy: marvell: cp110: mark u-boot power-off calls Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 20/23] phy: marvell: fix pll initialization for second utmi port Stefan Roese
` (4 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Grzegorz Jaszczyk <jaz@semihalf.com>
New products can contain up to 6 usb ports, therefore allow to initialize
all relevant UTMI PHYs.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_core.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h
index 3ac4985e7976..ba64491dfe11 100644
--- a/drivers/phy/marvell/comphy_core.h
+++ b/drivers/phy/marvell/comphy_core.h
@@ -18,7 +18,7 @@
#endif
#define MAX_LANE_OPTIONS 10
-#define MAX_UTMI_PHY_COUNT 3
+#define MAX_UTMI_PHY_COUNT 6
struct comphy_mux_options {
u32 type;
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 20/23] phy: marvell: fix pll initialization for second utmi port
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (18 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 19/23] phy: marvell: allow to initialize up to 6 USB ports Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 21/23] phy: marvell: add support for SFI1 Stefan Roese
` (3 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Grzegorz Jaszczyk <jaz@semihalf.com>
According to Design Reference Specification the PHY PLL and Calibration
register from PHY0 are shared for multi-port PHY. PLL control registers
inside other PHY channels are not used.
This commit reworks utmi device tree nodes in a way that common PHY PLL
registers are moved to main utmi node. Accordingly both child nodes
utmi-unit range is reduced and register offsets in utmi_phy.h are updated
to this change.
This fixes issues in scenarios when only utmi port1 was in use, which
resulted with lack of correct pll initialization.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/arm/dts/armada-cp110.dtsi | 36 +++++++++++++++++-------------
drivers/phy/marvell/comphy_cp110.c | 35 ++++++++++++++++++++++-------
drivers/phy/marvell/utmi_phy.h | 10 ++++-----
3 files changed, 53 insertions(+), 28 deletions(-)
diff --git a/arch/arm/dts/armada-cp110.dtsi b/arch/arm/dts/armada-cp110.dtsi
index d9c445601266..e9440a3368cd 100644
--- a/arch/arm/dts/armada-cp110.dtsi
+++ b/arch/arm/dts/armada-cp110.dtsi
@@ -192,22 +192,28 @@
max-lanes = <6>;
};
- CP110_LABEL(utmi0): utmi at 580000 {
- compatible = "marvell,mvebu-utmi-2.6.0";
- reg = <0x580000 0x1000>, /* utmi-unit */
- <0x440420 0x4>, /* usb-cfg */
- <0x440440 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
- status = "disabled";
- };
+ CP110_LABEL(utmi): utmi at 580000 {
+ compatible = "marvell,mvebu-utmi";
+ reg = <0x580000 0xc>; /* utmi-common-pll */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ CP110_LABEL(utmi0): utmi at 58000c {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x58000c 0x100>,/* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440440 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
+ status = "disabled";
+ };
- CP110_LABEL(utmi1): utmi at 581000 {
- compatible = "marvell,mvebu-utmi-2.6.0";
- reg = <0x581000 0x1000>, /* utmi-unit */
- <0x440420 0x4>, /* usb-cfg */
- <0x440444 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
- status = "disabled";
+ CP110_LABEL(utmi1): utmi at 58100c {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x58100c 0x100>,/* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440444 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
+ status = "disabled";
+ };
};
CP110_LABEL(sdhci0): sdhci at 780000 {
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 489a17c76f42..349109b6dc08 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -55,6 +55,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define COMPHY_UNIT_ID3 3
struct utmi_phy_data {
+ void __iomem *utmi_pll_addr;
void __iomem *utmi_base_addr;
void __iomem *usb_cfg_addr;
void __iomem *utmi_cfg_addr;
@@ -264,7 +265,8 @@ static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
return;
}
-static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
+static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
+ void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr,
u32 utmi_phy_port)
@@ -282,10 +284,10 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
/* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
- reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
+ reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
/* Impedance Calibration Threshold Setting */
- reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG,
0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
@@ -322,7 +324,8 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
return;
}
-static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
+static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr,
+ void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
{
@@ -341,7 +344,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
UTMI_CTRL_STATUS0_TEST_SEL_MASK);
debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
- addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
+ addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG;
data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 100);
@@ -360,7 +363,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
ret = 0;
}
- addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
+ addr = utmi_pll_addr + UTMI_PLL_CTRL_REG;
data = UTMI_PLL_CTRL_PLL_RDY_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 100);
@@ -411,14 +414,16 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count,
}
/* UTMI configure */
for (i = 0; i < utmi_phy_count; i++) {
- comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
+ comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr,
+ cp110_utmi_data[i].utmi_base_addr,
cp110_utmi_data[i].usb_cfg_addr,
cp110_utmi_data[i].utmi_cfg_addr,
cp110_utmi_data[i].utmi_phy_port);
}
/* UTMI Power up */
for (i = 0; i < utmi_phy_count; i++) {
- if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
+ if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr,
+ cp110_utmi_data[i].utmi_base_addr,
cp110_utmi_data[i].usb_cfg_addr,
cp110_utmi_data[i].utmi_cfg_addr,
cp110_utmi_data[i].utmi_phy_port)) {
@@ -453,6 +458,7 @@ void comphy_dedicated_phys_init(void)
struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
int node = -1;
int node_idx;
+ int parent = -1;
debug_enter();
debug("Initialize USB UTMI PHYs\n");
@@ -468,6 +474,19 @@ void comphy_dedicated_phys_init(void)
if (!fdtdec_get_is_enabled(gd->fdt_blob, node))
continue;
+ parent = fdt_parent_offset(gd->fdt_blob, node);
+ if (parent <= 0)
+ break;
+
+ /* get base address of UTMI PLL */
+ cp110_utmi_data[node_idx].utmi_pll_addr =
+ (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, parent, "reg", 0, NULL, true);
+ if (!cp110_utmi_data[node_idx].utmi_pll_addr) {
+ pr_err("UTMI PHY PLL address is invalid\n");
+ continue;
+ }
+
/* get base address of UTMI phy */
cp110_utmi_data[node_idx].utmi_base_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h
index fa6bf3c9141e..d1cad07cf50f 100644
--- a/drivers/phy/marvell/utmi_phy.h
+++ b/drivers/phy/marvell/utmi_phy.h
@@ -45,7 +45,7 @@
#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
-#define UTMI_TX_CH_CTRL_REG 0xC
+#define UTMI_TX_CH_CTRL_REG 0x0
#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12
#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
@@ -56,7 +56,7 @@
#define UTMI_TX_CH_CTRL_AMP_MASK \
(0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
-#define UTMI_RX_CH_CTRL0_REG 0x14
+#define UTMI_RX_CH_CTRL0_REG 0x8
#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
@@ -64,7 +64,7 @@
#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
-#define UTMI_RX_CH_CTRL1_REG 0x18
+#define UTMI_RX_CH_CTRL1_REG 0xc
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \
(0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
@@ -72,7 +72,7 @@
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \
(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
-#define UTMI_CTRL_STATUS0_REG 0x24
+#define UTMI_CTRL_STATUS0_REG 0x18
#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22
#define UTMI_CTRL_STATUS0_SUSPENDM_MASK \
(0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
@@ -80,7 +80,7 @@
#define UTMI_CTRL_STATUS0_TEST_SEL_MASK \
(0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
-#define UTMI_CHGDTC_CTRL_REG 0x38
+#define UTMI_CHGDTC_CTRL_REG 0x2c
#define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8
#define UTMI_CHGDTC_CTRL_VDAT_MASK \
(0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 21/23] phy: marvell: add support for SFI1
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (19 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 20/23] phy: marvell: fix pll initialization for second utmi port Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 22/23] phy: marvell: utmi: update utmi config which fixes usb2.0 instability Stefan Roese
` (2 subsequent siblings)
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.
In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0
No functional change for exsiting configuration.
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/arm/dts/armada-7040-db.dts | 3 ++-
arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 4 ++--
arch/arm/dts/armada-8040-db.dts | 4 ++--
arch/arm/dts/armada-8040-mcbin.dts | 4 ++--
arch/arm/dts/armada-8040-puzzle-m801.dts | 4 ++--
arch/arm/dts/cn9130-crb-A.dts | 2 +-
arch/arm/dts/cn9130-crb-B.dts | 2 +-
drivers/phy/marvell/comphy_core.c | 2 +-
drivers/phy/marvell/comphy_cp110.c | 14 ++++++++------
include/dt-bindings/comphy/comphy_data.h | 9 +++++----
10 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index f475fb361071..b158f9234917 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -132,7 +132,8 @@
};
phy2 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy3 {
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index ce5832c2fbd7..6a586dbbba12 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -154,7 +154,7 @@
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: Not connected
- * Lane 2: SFI (10G)
+ * Lane 2: SFI0 (10G)
* Lane 3: Not connected
* Lane 4: USB 3.0 host port1 (can be PCIe)
* Lane 5: Not connected
@@ -166,7 +166,7 @@
phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_UNCONNECTED>;
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 1edfaab682eb..51c2f23f4dbf 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -95,7 +95,7 @@
phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_SATA1>;
@@ -194,7 +194,7 @@
phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_SATA1>;
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index a6ef40138da3..218464831863 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -183,7 +183,7 @@
phy-type = <COMPHY_TYPE_PEX0>;
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
@@ -299,7 +299,7 @@
phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SGMII2>;
diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts
index 0becc4ff0d34..510fb84d5a95 100644
--- a/arch/arm/dts/armada-8040-puzzle-m801.dts
+++ b/arch/arm/dts/armada-8040-puzzle-m801.dts
@@ -234,7 +234,7 @@
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
@@ -380,7 +380,7 @@
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SGMII2>;
diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts
index 5c5e0fb2eb1e..fcfcd15d8de6 100644
--- a/arch/arm/dts/cn9130-crb-A.dts
+++ b/arch/arm/dts/cn9130-crb-A.dts
@@ -31,7 +31,7 @@
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};
diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts
index 6041084a2c87..b681b6032d69 100644
--- a/arch/arm/dts/cn9130-crb-B.dts
+++ b/arch/arm/dts/cn9130-crb-B.dts
@@ -31,7 +31,7 @@
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 929360792630..2c9d7b2288d7 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -41,7 +41,7 @@ static const char *get_type_string(u32 type)
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
"SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
"USB3", "USB3_HOST0", "USB3_HOST1",
- "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP",
+ "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
"IGNORE"
};
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 349109b6dc08..576538feb706 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -109,10 +109,11 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
u32 lane)
{
int ret;
+ u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
debug_enter();
- if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
+ if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
pr_err("Comphy %d isn't configured to SFI\n", lane);
return 0;
}
@@ -630,13 +631,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case COMPHY_TYPE_SFI:
- mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
- COMPHY_UNIT_ID0,
+ case COMPHY_TYPE_SFI0:
+ case COMPHY_TYPE_SFI1:
+ /* Calculate SFI id */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
+ mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
- ptr_chip_cfg->comphy_base_addr, lane,
- mode);
+ ptr_chip_cfg->comphy_base_addr, lane, mode);
break;
case COMPHY_TYPE_RXAUI0:
case COMPHY_TYPE_RXAUI1:
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
index 8e9270598924..8353a7874050 100644
--- a/include/dt-bindings/comphy/comphy_data.h
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -32,10 +32,11 @@
#define COMPHY_TYPE_USB3_DEVICE 13
#define COMPHY_TYPE_RXAUI0 14
#define COMPHY_TYPE_RXAUI1 15
-#define COMPHY_TYPE_SFI 16
-#define COMPHY_TYPE_AP 17
-#define COMPHY_TYPE_IGNORE 18
-#define COMPHY_TYPE_MAX 19
+#define COMPHY_TYPE_SFI0 16
+#define COMPHY_TYPE_SFI1 17
+#define COMPHY_TYPE_AP 18
+#define COMPHY_TYPE_IGNORE 19
+#define COMPHY_TYPE_MAX 20
#define COMPHY_TYPE_INVALID 0xff
#define COMPHY_POLARITY_NO_INVERT 0
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 22/23] phy: marvell: utmi: update utmi config which fixes usb2.0 instability
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (20 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 21/23] phy: marvell: add support for SFI1 Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-03-24 14:06 ` [PATCH v1 23/23] doc: dt-bindings: add Marvell comphy binding Stefan Roese
2021-04-29 6:46 ` [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Grzegorz Jaszczyk <jaz@semihalf.com>
- Add additional step which enables the Impedance and PLL calibration.
- Enable old squelch detector instead of the new analog squelch detector
circuit and update host disconnect threshold value.
- Update LS TX driver strength coarse and fine adjustment values.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/phy/marvell/comphy_cp110.c | 23 ++++++++++++++++++-----
drivers/phy/marvell/utmi_phy.h | 9 +++++++++
2 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 576538feb706..418318d12f6b 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -288,21 +288,34 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
/* Impedance Calibration Threshold Setting */
- reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG,
- 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
- UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
+ mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK;
+ data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET;
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
+
+ /* Start Impedance and PLL Calibration */
+ mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK;
+ data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET);
+ mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK;
+ data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET);
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
/* Set LS TX driver strength coarse control */
mask = UTMI_TX_CH_CTRL_AMP_MASK;
data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
+ mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
+ data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
+ mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
+ data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
/* Enable SQ */
mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
- data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
+ data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
/* Enable analog squelch detect */
mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
- data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK;
+ data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET;
reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
/* Set External squelch calibration number */
diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h
index d1cad07cf50f..8a570bae7390 100644
--- a/drivers/phy/marvell/utmi_phy.h
+++ b/drivers/phy/marvell/utmi_phy.h
@@ -38,6 +38,12 @@
#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
+#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13
+#define UTMI_CALIB_CTRL_IMPCAL_START_MASK \
+ (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET)
+#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22
+#define UTMI_CALIB_CTRL_PLLCAL_START_MASK \
+ (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET)
#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
@@ -57,6 +63,9 @@
(0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
#define UTMI_RX_CH_CTRL0_REG 0x8
+#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8
+#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK \
+ (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET)
#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 23/23] doc: dt-bindings: add Marvell comphy binding
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (21 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 22/23] phy: marvell: utmi: update utmi config which fixes usb2.0 instability Stefan Roese
@ 2021-03-24 14:06 ` Stefan Roese
2021-04-29 6:46 ` [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
23 siblings, 0 replies; 39+ messages in thread
From: Stefan Roese @ 2021-03-24 14:06 UTC (permalink / raw)
To: u-boot
From: Igal Liberman <igall@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
doc/device-tree-bindings/phy/mvebu_comphy.txt | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 doc/device-tree-bindings/phy/mvebu_comphy.txt
diff --git a/doc/device-tree-bindings/phy/mvebu_comphy.txt b/doc/device-tree-bindings/phy/mvebu_comphy.txt
new file mode 100644
index 000000000000..65b83848596b
--- /dev/null
+++ b/doc/device-tree-bindings/phy/mvebu_comphy.txt
@@ -0,0 +1,68 @@
+Marvell COMPHY SerDes lane bindings
+=====================================
+
+The COMPHY node includes a description of the COMPHY SerDes lane configuration.
+The COMPHY driver initializes the MUX of the SerDes lanes, and powers up the SerDes
+by dependencies on the FDT blob configurations
+
+Mandatory properties:
+SoC specific:
+ - compatible:
+ The compatible should include "marvell,mvebu-comphy"
+ and the COMPHY per chip compatible:
+ "marvell,comphy-cp110" for CP110 available in Aramda70x0/80x0.
+ The COMPHY per chip used to set which MUX configuration to use, and COMPHY power-up revision.
+ - reg: Base address and size of the COMPHY and hpipe units.
+ - max-lanes: Maximum number of comphy lanes.
+ - mux-bitcount: Number of bits that are allocated for every MUX in the COMPHY-selector register.
+Board specific:
+ - PHY: Entry that include the configuration of the PHY.
+ Every PHY should have the below parameters:
+ - phy-type: the mode of the PHY
+ Possible modes located in include/dt-bindings/comphy/comphy_data.h
+ Optional properties:
+ - phy-speed: the speed of the PHY
+ Possible speeds values located in include/dt-bindings/comphy/comphy_data.h
+ - phy-invert: Polarity invert (COMPHY_POLARITY_TXD_INVERT/COMPHY_POLARITY_RXD_INVERT)
+ the possible bits under include/dt-bindings/comphy/comphy_data.h
+ - clk-src: Set the clock source of PCIe, if configured to PCIe clock output
+ This relevant for SerDes lane 5 only (by default, lane 4 is the clock source)
+ for Armada-7040 boards.
+ - endpoint: Optional boolean specifying this SerDes should be configured as PCIe endpoint.
+
+Example:
+ cpm_comphy: comphy at 441000 {
+ compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+ reg = <0x441000 0x8>, <0x120000 0x8>;
+ mux-bitcount = <4>;
+ max-lanes = <6>;
+
+ /*
+ * CP110 Serdes Configuration:
+ * Lane 0: SGMII1
+ * Lane 1: SATA 0
+ * Lane 2: USB HOST 0
+ * Lane 3: SATA1
+ * Lane 4: SFI (10G)
+ * Lane 5: SGMII2
+ */
+ phy0 {
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+ phy1 {
+ phy-type = <COMPHY_TYPE_SATA0>;
+ };
+ phy2 {
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ };
+ phy3 {
+ phy-type = <COMPHY_TYPE_SATA1>;
+ };
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI>;
+ };
+ phy5 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ };
+ };
--
2.31.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
2021-03-24 14:06 [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
` (22 preceding siblings ...)
2021-03-24 14:06 ` [PATCH v1 23/23] doc: dt-bindings: add Marvell comphy binding Stefan Roese
@ 2021-04-29 6:46 ` Stefan Roese
2021-04-29 8:27 ` Marek Behun
23 siblings, 1 reply; 39+ messages in thread
From: Stefan Roese @ 2021-04-29 6:46 UTC (permalink / raw)
To: u-boot
On 24.03.21 15:06, Stefan Roese wrote:
>
> This patchset adds the missing SERDES patches from the Marvell U-Boot
> SDK U-Boot version. This is done in preparation for the integration
> of the Octeon TX2 CN913x support, which uses the updated version of
> this code.
>
> Thanks,
> Stefan
>
>
> Christine Gharzuzi (1):
> phy: marvell: fix handling of unconnected comphy
>
> Grzegorz Jaszczyk (8):
> phy: marvell: cp110: let the firmware configure comphy for RXAUI
> phy: marvell: cp110: let the firmware configure comphy for USB
> phy: marvell: cp110: let the firmware perform training for XFI
> phy: marvell: cp110: remove both phy and pipe selector configuration
> phy: marvell: cp110: clean up driver after it was moved to atf
> phy: marvell: allow to initialize up to 6 USB ports
> phy: marvell: fix pll initialization for second utmi port
> phy: marvell: utmi: update utmi config which fixes usb2.0 instability
>
> Igal Liberman (11):
> phy: marvell: rename comphy related definitions to COMPHY_XX
> phy: marvell: add missing speed during info prints
> phy: marvell: cp110: utmi: update analog parameters according to
> latest ETP
> phy: marvell: fix several minor bugs in comphy_probe
> phy: marvell: save comphy_map_data priv structure
> phy: marvell: add RX training command
> phy: marvell: enable comphy info prints for all devices
> phy: marvell: pass sgmii id to firmware
> phy: marvell: cp110: mark u-boot power-off calls
> phy: marvell: add support for SFI1
> doc: dt-bindings: add Marvell comphy binding
>
> Marcin Wojtas (1):
> phy: marvell: cp110: remove unused definitions
>
> Omri Itach (1):
> phy: marvell: cp110: initialize only enabled UTMI units
>
> jinghua (1):
> phy: marvell: add comphy type PHY_TYPE_USB3
>
> arch/arm/dts/armada-3720-db.dts | 8 +-
> arch/arm/dts/armada-3720-espressobin.dts | 12 +-
> arch/arm/dts/armada-3720-turris-mox.dts | 12 +-
> arch/arm/dts/armada-3720-uDPU.dts | 23 +-
> arch/arm/dts/armada-7040-db-nand.dts | 24 +-
> arch/arm/dts/armada-7040-db.dts | 23 +-
> arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 32 +-
> arch/arm/dts/armada-8040-db.dts | 24 +-
> arch/arm/dts/armada-8040-mcbin.dts | 27 +-
> arch/arm/dts/armada-8040-puzzle-m801.dts | 32 +-
> arch/arm/dts/armada-cp110.dtsi | 36 +-
> arch/arm/dts/cn9130-crb-A.dts | 16 +-
> arch/arm/dts/cn9130-crb-B.dts | 16 +-
> board/CZ.NIC/turris_mox/turris_mox.c | 8 +-
> cmd/mvebu/Kconfig | 7 +
> cmd/mvebu/Makefile | 2 +-
> cmd/mvebu/rx_training.c | 57 ++
> configs/mvebu_db_armada8k_defconfig | 1 +
> doc/device-tree-bindings/phy/mvebu_comphy.txt | 68 ++
> drivers/phy/marvell/comphy_a3700.c | 70 +-
> drivers/phy/marvell/comphy_a3700.h | 1 -
> drivers/phy/marvell/comphy_core.c | 81 ++-
> drivers/phy/marvell/comphy_core.h | 67 +-
> drivers/phy/marvell/comphy_cp110.c | 621 ++++------------
> drivers/phy/marvell/comphy_hpipe.h | 660 ------------------
> drivers/phy/marvell/comphy_mux.c | 11 +-
> drivers/phy/marvell/utmi_phy.h | 24 +-
> include/dt-bindings/comphy/comphy_data.h | 80 +--
> include/mvebu/comphy.h | 2 +-
> 29 files changed, 591 insertions(+), 1454 deletions(-)
> create mode 100644 cmd/mvebu/rx_training.c
> create mode 100644 doc/device-tree-bindings/phy/mvebu_comphy.txt
> delete mode 100644 drivers/phy/marvell/comphy_hpipe.h
>
Applied to u-boot-marvell/master
Thanks,
Stefan
^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
2021-04-29 6:46 ` [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version Stefan Roese
@ 2021-04-29 8:27 ` Marek Behun
2021-04-29 9:00 ` Stefan Roese
0 siblings, 1 reply; 39+ messages in thread
From: Marek Behun @ 2021-04-29 8:27 UTC (permalink / raw)
To: u-boot
On Thu, 29 Apr 2021 08:46:36 +0200
Stefan Roese <sr@denx.de> wrote:
> > phy: marvell: add RX training command
>
> Applied to u-boot-marvell/master
>
> Thanks,
> Stefan
Stefan, do you think it would make sense to at least create a special
mechanism for these platform commands? For example via a top-level
command "plat", i.e. instead of
> rx_training params
we would call
> plat rx_training params
The plat command could list all registered platform specific commands...
Marek
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
2021-04-29 8:27 ` Marek Behun
@ 2021-04-29 9:00 ` Stefan Roese
2021-05-04 22:28 ` Pali Rohár
0 siblings, 1 reply; 39+ messages in thread
From: Stefan Roese @ 2021-04-29 9:00 UTC (permalink / raw)
To: u-boot
Hi Marek,
(Added Tom and Simon to Cc)
On 29.04.21 10:27, Marek Behun wrote:
> On Thu, 29 Apr 2021 08:46:36 +0200
> Stefan Roese <sr@denx.de> wrote:
>
>>> phy: marvell: add RX training command
>>
>> Applied to u-boot-marvell/master
>>
>> Thanks,
>> Stefan
>
> Stefan, do you think it would make sense to at least create a special
> mechanism for these platform commands? For example via a top-level
> command "plat", i.e. instead of
> > rx_training params
> we would call
> > plat rx_training params
>
> The plat command could list all registered platform specific commands...
Not sure. If you want to split it up, then we would perhaps also
need to add a mechanism for board specific commands as well. E.g. for
commands not common for a platform but only for specific boards. My
feeling is that this makes things overly complex. And I also don't see
a real problem with the current "flat" structure of these commands
being "global". Again, I mention the many already existing board and
platform specific commands in current mainline.
Perhaps other people can comment on this use / introduction of
platform specific U-Boot commands?
BTW: Again, we can definitely rename this specific "rx_training"
command, if you feel this is absolutely misleading. IIRC, then I already
made a suggestion for this.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
2021-04-29 9:00 ` Stefan Roese
@ 2021-05-04 22:28 ` Pali Rohár
2021-05-05 7:00 ` Stefan Roese
0 siblings, 1 reply; 39+ messages in thread
From: Pali Rohár @ 2021-05-04 22:28 UTC (permalink / raw)
To: u-boot
On Thursday 29 April 2021 11:00:17 Stefan Roese wrote:
> Hi Marek,
>
> (Added Tom and Simon to Cc)
>
> On 29.04.21 10:27, Marek Behun wrote:
> > On Thu, 29 Apr 2021 08:46:36 +0200
> > Stefan Roese <sr@denx.de> wrote:
> >
> > > > phy: marvell: add RX training command
> > >
> > > Applied to u-boot-marvell/master
> > >
> > > Thanks,
> > > Stefan
> >
> > Stefan, do you think it would make sense to at least create a special
> > mechanism for these platform commands? For example via a top-level
> > command "plat", i.e. instead of
> > > rx_training params
> > we would call
> > > plat rx_training params
> >
> > The plat command could list all registered platform specific commands...
>
> Not sure. If you want to split it up, then we would perhaps also
> need to add a mechanism for board specific commands as well. E.g. for
> commands not common for a platform but only for specific boards. My
> feeling is that this makes things overly complex. And I also don't see
> a real problem with the current "flat" structure of these commands
> being "global". Again, I mention the many already existing board and
> platform specific commands in current mainline.
>
> Perhaps other people can comment on this use / introduction of
> platform specific U-Boot commands?
>
> BTW: Again, we can definitely rename this specific "rx_training"
> command, if you feel this is absolutely misleading. IIRC, then I already
> made a suggestion for this.
Hello! "rx_training" is definitely ambiguous and I strongly suggest to
rename this command (if is going to be merged in current form).
My first impression was that this command is suppose to do some DDR3/4
training sequence but it is doing something totally different.
I'm also not a big fan of these custom vendor specific/proprietary
commands. And I rather would like to see generic command with an API so
other boards and vendors could implement it too.
But if this comphy rx training code is something specific to Marvell
platforms and there is no other platform which needs such abstraction
then lets have it as custom vendor specific command.
I hope that Tom or Simon have better knowledge of U-Boot code and
hardware on which is U-Boot running and can say if there are other
platforms for such command or not.
And if "plat" command is too complex for this, what about renaming this
command to something like "mvebu_comphy_rx_training" or something
similar? To express that it is Marvell specific and also mention that it
is for comphy. And not for ddr, uart or ethernet phy.
Same applies for Marvell command "bubt" which is already present in
U-Boot codebase. It has totally insane name as abbreviation of Burn
UBooT and moreover on A3720 is does not even work with U-Boot image but
rather with "big" image in specific custom format which contains
concatenation of Cortex-M3 Secure Firmware, Cortex-A53 Trusted Firmware
and U-Boot. And I think this "bubt" is example of command which should
not be vendor specific but rather generic U-Boot command as its purpose
is to update vendor specific boot image stored in nand/eMMC either via
TFTP or from uSD card. So this command could have been called "fwupdate"
or similar to express that is updated vendor specific firmware or U-Boot
bootloader in vendor specific format (if U-Boot needs to have some
encapsulation) for current board to current "boot device/partition".
> Thanks,
> Stefan
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
2021-05-04 22:28 ` Pali Rohár
@ 2021-05-05 7:00 ` Stefan Roese
2021-05-05 9:19 ` Pali Rohár
0 siblings, 1 reply; 39+ messages in thread
From: Stefan Roese @ 2021-05-05 7:00 UTC (permalink / raw)
To: u-boot
Hi Pali,
On 05.05.21 00:28, Pali Roh?r wrote:
> On Thursday 29 April 2021 11:00:17 Stefan Roese wrote:
>> Hi Marek,
>>
>> (Added Tom and Simon to Cc)
>>
>> On 29.04.21 10:27, Marek Behun wrote:
>>> On Thu, 29 Apr 2021 08:46:36 +0200
>>> Stefan Roese <sr@denx.de> wrote:
>>>
>>>>> phy: marvell: add RX training command
>>>>
>>>> Applied to u-boot-marvell/master
>>>>
>>>> Thanks,
>>>> Stefan
>>>
>>> Stefan, do you think it would make sense to at least create a special
>>> mechanism for these platform commands? For example via a top-level
>>> command "plat", i.e. instead of
>>> > rx_training params
>>> we would call
>>> > plat rx_training params
>>>
>>> The plat command could list all registered platform specific commands...
>>
>> Not sure. If you want to split it up, then we would perhaps also
>> need to add a mechanism for board specific commands as well. E.g. for
>> commands not common for a platform but only for specific boards. My
>> feeling is that this makes things overly complex. And I also don't see
>> a real problem with the current "flat" structure of these commands
>> being "global". Again, I mention the many already existing board and
>> platform specific commands in current mainline.
>>
>> Perhaps other people can comment on this use / introduction of
>> platform specific U-Boot commands?
>>
>> BTW: Again, we can definitely rename this specific "rx_training"
>> command, if you feel this is absolutely misleading. IIRC, then I already
>> made a suggestion for this.
>
> Hello! "rx_training" is definitely ambiguous and I strongly suggest to
> rename this command (if is going to be merged in current form).
It's already in mainline. I'll probably send a patch to rename it,
please see below...
> My first impression was that this command is suppose to do some DDR3/4
> training sequence but it is doing something totally different.
>
> I'm also not a big fan of these custom vendor specific/proprietary
> commands. And I rather would like to see generic command with an API so
> other boards and vendors could implement it too.
>
> But if this comphy rx training code is something specific to Marvell
> platforms and there is no other platform which needs such abstraction
> then lets have it as custom vendor specific command.
>
> I hope that Tom or Simon have better knowledge of U-Boot code and
> hardware on which is U-Boot running and can say if there are other
> platforms for such command or not.
>
> And if "plat" command is too complex for this, what about renaming this
> command to something like "mvebu_comphy_rx_training" or something
> similar? To express that it is Marvell specific and also mention that it
> is for comphy. And not for ddr, uart or ethernet phy.
No other platform than "MVEBU" can select this command. So adding
"mvebu" seems superflous to me. But it would make it clear that it's
platform specific never the less. I agree that "comphy" makes
perfect sense to avoid confusion (mixup with DDR3/4) here.
> Same applies for Marvell command "bubt" which is already present in
> U-Boot codebase.
"bubt" is special and cannot be changed easily without breaking update
scripts using it AFAICT. As it's pretty old and used in the Marvell code
base for quite some time - including all the documentation about
updating.
> It has totally insane name as abbreviation of Burn
> UBooT and moreover on A3720 is does not even work with U-Boot image but
> rather with "big" image in specific custom format which contains
> concatenation of Cortex-M3 Secure Firmware, Cortex-A53 Trusted Firmware
> and U-Boot. And I think this "bubt" is example of command which should
> not be vendor specific but rather generic U-Boot command as its purpose
> is to update vendor specific boot image stored in nand/eMMC either via
> TFTP or from uSD card. So this command could have been called "fwupdate"
> or similar to express that is updated vendor specific firmware or U-Boot
> bootloader in vendor specific format (if U-Boot needs to have some
> encapsulation) for current board to current "boot device/partition".
Yes, it would be nice to have a common / generic command for such an
update process with multiple options (storage device etc).
Thanks,
Stefan
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
2021-05-05 7:00 ` Stefan Roese
@ 2021-05-05 9:19 ` Pali Rohár
2021-05-05 16:38 ` Marek Behun
0 siblings, 1 reply; 39+ messages in thread
From: Pali Rohár @ 2021-05-05 9:19 UTC (permalink / raw)
To: u-boot
On Wednesday 05 May 2021 09:00:57 Stefan Roese wrote:
> Hi Pali,
>
> On 05.05.21 00:28, Pali Roh?r wrote:
> > On Thursday 29 April 2021 11:00:17 Stefan Roese wrote:
> > > Hi Marek,
> > >
> > > (Added Tom and Simon to Cc)
> > >
> > > On 29.04.21 10:27, Marek Behun wrote:
> > > > On Thu, 29 Apr 2021 08:46:36 +0200
> > > > Stefan Roese <sr@denx.de> wrote:
> > > >
> > > > > > phy: marvell: add RX training command
> > > > >
> > > > > Applied to u-boot-marvell/master
> > > > >
> > > > > Thanks,
> > > > > Stefan
> > > >
> > > > Stefan, do you think it would make sense to at least create a special
> > > > mechanism for these platform commands? For example via a top-level
> > > > command "plat", i.e. instead of
> > > > > rx_training params
> > > > we would call
> > > > > plat rx_training params
> > > >
> > > > The plat command could list all registered platform specific commands...
> > >
> > > Not sure. If you want to split it up, then we would perhaps also
> > > need to add a mechanism for board specific commands as well. E.g. for
> > > commands not common for a platform but only for specific boards. My
> > > feeling is that this makes things overly complex. And I also don't see
> > > a real problem with the current "flat" structure of these commands
> > > being "global". Again, I mention the many already existing board and
> > > platform specific commands in current mainline.
> > >
> > > Perhaps other people can comment on this use / introduction of
> > > platform specific U-Boot commands?
> > >
> > > BTW: Again, we can definitely rename this specific "rx_training"
> > > command, if you feel this is absolutely misleading. IIRC, then I already
> > > made a suggestion for this.
> >
> > Hello! "rx_training" is definitely ambiguous and I strongly suggest to
> > rename this command (if is going to be merged in current form).
>
> It's already in mainline. I'll probably send a patch to rename it,
> please see below...
>
> > My first impression was that this command is suppose to do some DDR3/4
> > training sequence but it is doing something totally different.
> >
> > I'm also not a big fan of these custom vendor specific/proprietary
> > commands. And I rather would like to see generic command with an API so
> > other boards and vendors could implement it too.
> >
> > But if this comphy rx training code is something specific to Marvell
> > platforms and there is no other platform which needs such abstraction
> > then lets have it as custom vendor specific command.
> >
> > I hope that Tom or Simon have better knowledge of U-Boot code and
> > hardware on which is U-Boot running and can say if there are other
> > platforms for such command or not.
> >
> > And if "plat" command is too complex for this, what about renaming this
> > command to something like "mvebu_comphy_rx_training" or something
> > similar? To express that it is Marvell specific and also mention that it
> > is for comphy. And not for ddr, uart or ethernet phy.
>
> No other platform than "MVEBU" can select this command. So adding
> "mvebu" seems superflous to me. But it would make it clear that it's
> platform specific never the less. I agree that "comphy" makes
> perfect sense to avoid confusion (mixup with DDR3/4) here.
I mean if there is another platform for which such command could be
implemented in future (not what is currently implemented/supported) or
if comphy rx training "feature" is a8k specific.
> > Same applies for Marvell command "bubt" which is already present in
> > U-Boot codebase.
>
> "bubt" is special and cannot be changed easily without breaking update
> scripts using it AFAICT. As it's pretty old and used in the Marvell code
> base for quite some time - including all the documentation about
> updating.
I see. This needs to say in current form.
> > It has totally insane name as abbreviation of Burn
> > UBooT and moreover on A3720 is does not even work with U-Boot image but
> > rather with "big" image in specific custom format which contains
> > concatenation of Cortex-M3 Secure Firmware, Cortex-A53 Trusted Firmware
> > and U-Boot. And I think this "bubt" is example of command which should
> > not be vendor specific but rather generic U-Boot command as its purpose
> > is to update vendor specific boot image stored in nand/eMMC either via
> > TFTP or from uSD card. So this command could have been called "fwupdate"
> > or similar to express that is updated vendor specific firmware or U-Boot
> > bootloader in vendor specific format (if U-Boot needs to have some
> > encapsulation) for current board to current "boot device/partition".
>
> Yes, it would be nice to have a common / generic command for such an
> update process with multiple options (storage device etc).
>
> Thanks,
> Stefan
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 00/23] phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version
2021-05-05 9:19 ` Pali Rohár
@ 2021-05-05 16:38 ` Marek Behun
0 siblings, 0 replies; 39+ messages in thread
From: Marek Behun @ 2021-05-05 16:38 UTC (permalink / raw)
To: u-boot
On Wed, 5 May 2021 11:19:13 +0200
Pali Roh?r <pali@kernel.org> wrote:
> > "bubt" is special and cannot be changed easily without breaking update
> > scripts using it AFAICT. As it's pretty old and used in the Marvell code
> > base for quite some time - including all the documentation about
> > updating.
>
> I see. This needs to say in current form.
bubt can theoretically be implemented for other platforms. Its purpose
is to update u-boot. This is useful for other platforms.
Marek
^ permalink raw reply [flat|nested] 39+ messages in thread