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From: Jonas Bonn <jonas@norrbonn.se>
To: Geert Uytterhoeven <geert@linux-m68k.org>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>
Cc: MTD Maling List <linux-mtd@lists.infradead.org>,
	Marek Vasut <marek.vasut+renesas@gmail.com>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v4 2/3] spi-nor: s25fl512s supports region locking
Date: Tue, 7 May 2019 13:13:55 +0200	[thread overview]
Message-ID: <fac5fa6d-95e9-cfb0-4d5a-6b16d4470190@norrbonn.se> (raw)
In-Reply-To: <CAMuHMdU83vLeVSqMZuJwR4yd382mau-OE1saMAOC2+6HodsHvg@mail.gmail.com>

Hi Geert,

On 07/05/2019 12:50, Geert Uytterhoeven wrote:
> Hi Tudor,
> 
> On Tue, May 7, 2019 at 12:42 PM <Tudor.Ambarus@microchip.com> wrote:
>> On 05/07/2019 12:53 PM, Geert Uytterhoeven wrote:
>>> On Wed, Mar 20, 2019 at 8:16 AM Jonas Bonn <jonas@norrbonn.se> wrote:
>>>> Both the BP[0-2] bits and the TBPROT bit are supported on this chip.
>>>> Tested and verified on a Cypress s25fl512s.
>>>>
>>>> Signed-off-by: Jonas Bonn <jonas@norrbonn.se>
>>>
>>> This is now commit dcb4b22eeaf44f91 ("spi-nor: s25fl512s supports region
>>> locking") in mtd/next.
>>>
>>>> --- a/drivers/mtd/spi-nor/spi-nor.c
>>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>>>> @@ -1898,7 +1898,9 @@ static const struct flash_info spi_nor_ids[] = {
>>>>                          SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>>>>          { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
>>>>          { "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>>>> -       { "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>>>> +       { "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
>>>> +                       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>>>> +                       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | USE_CLSR) },
>>>
>>> Setting SPI_NOR_HAS_LOCK causes the QSPI FLASH on r8a7791/koelsch to fail
>>> probing.
>>>
>>> Before/after:
>>>
>>>      -m25p80 spi0.0: s25fl512s (65536 Kbytes)
>>>      -3 fixed-partitions partitions found on MTD device spi0.0
>>>      -Creating 3 MTD partitions on "spi0.0":
>>>      -0x000000000000-0x000000080000 : "loader"
>>>      -0x000000080000-0x000000600000 : "user"
>>>      -0x000000600000-0x000004000000 : "flash"
>>>      +m25p80 spi0.0: Erase Error occurred
>>>      +m25p80 spi0.0: Erase Error occurred
>>>      +m25p80 spi0.0: timeout while writing configuration register
>>>      +m25p80 spi0.0: quad mode not supported
>>>      +m25p80: probe of spi0.0 failed with error -5
>>>

In drivers/mtd/spi-nor/spi-nor.c you have:

static int spi_nor_init(struct spi_nor *nor)
{
         int err;

         /*
          * Atmel, SST, Intel/Numonyx, and others serial NOR tend to 
power up
          * with the software protection bits set
          */
         if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
             JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
             JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
             nor->info->flags & SPI_NOR_HAS_LOCK) {
                 write_enable(nor);
                 write_sr(nor, 0);
                 spi_nor_wait_till_ready(nor);
         }

         if (nor->quad_enable) {
                 err = nor->quad_enable(nor);
                 if (err) {
                         dev_err(nor->dev, "quad mode not supported\n");
                         return err;
                 }
         }

This is the only meaningful thing that I can see may have changed with 
this flag.  We now have an additional write_enable before quad_enable. 
What happens if you swap those two blocks above so that quad_enable is 
called first?

If it's not that, I can't see how the extra flags can have any effect.

Regards,
Jonas

WARNING: multiple messages have this Message-ID (diff)
From: Jonas Bonn <jonas@norrbonn.se>
To: Geert Uytterhoeven <geert@linux-m68k.org>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>
Cc: Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	MTD Maling List <linux-mtd@lists.infradead.org>,
	Marek Vasut <marek.vasut+renesas@gmail.com>
Subject: Re: [PATCH v4 2/3] spi-nor: s25fl512s supports region locking
Date: Tue, 7 May 2019 13:13:55 +0200	[thread overview]
Message-ID: <fac5fa6d-95e9-cfb0-4d5a-6b16d4470190@norrbonn.se> (raw)
In-Reply-To: <CAMuHMdU83vLeVSqMZuJwR4yd382mau-OE1saMAOC2+6HodsHvg@mail.gmail.com>

Hi Geert,

On 07/05/2019 12:50, Geert Uytterhoeven wrote:
> Hi Tudor,
> 
> On Tue, May 7, 2019 at 12:42 PM <Tudor.Ambarus@microchip.com> wrote:
>> On 05/07/2019 12:53 PM, Geert Uytterhoeven wrote:
>>> On Wed, Mar 20, 2019 at 8:16 AM Jonas Bonn <jonas@norrbonn.se> wrote:
>>>> Both the BP[0-2] bits and the TBPROT bit are supported on this chip.
>>>> Tested and verified on a Cypress s25fl512s.
>>>>
>>>> Signed-off-by: Jonas Bonn <jonas@norrbonn.se>
>>>
>>> This is now commit dcb4b22eeaf44f91 ("spi-nor: s25fl512s supports region
>>> locking") in mtd/next.
>>>
>>>> --- a/drivers/mtd/spi-nor/spi-nor.c
>>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>>>> @@ -1898,7 +1898,9 @@ static const struct flash_info spi_nor_ids[] = {
>>>>                          SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>>>>          { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
>>>>          { "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>>>> -       { "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
>>>> +       { "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
>>>> +                       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>>>> +                       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | USE_CLSR) },
>>>
>>> Setting SPI_NOR_HAS_LOCK causes the QSPI FLASH on r8a7791/koelsch to fail
>>> probing.
>>>
>>> Before/after:
>>>
>>>      -m25p80 spi0.0: s25fl512s (65536 Kbytes)
>>>      -3 fixed-partitions partitions found on MTD device spi0.0
>>>      -Creating 3 MTD partitions on "spi0.0":
>>>      -0x000000000000-0x000000080000 : "loader"
>>>      -0x000000080000-0x000000600000 : "user"
>>>      -0x000000600000-0x000004000000 : "flash"
>>>      +m25p80 spi0.0: Erase Error occurred
>>>      +m25p80 spi0.0: Erase Error occurred
>>>      +m25p80 spi0.0: timeout while writing configuration register
>>>      +m25p80 spi0.0: quad mode not supported
>>>      +m25p80: probe of spi0.0 failed with error -5
>>>

In drivers/mtd/spi-nor/spi-nor.c you have:

static int spi_nor_init(struct spi_nor *nor)
{
         int err;

         /*
          * Atmel, SST, Intel/Numonyx, and others serial NOR tend to 
power up
          * with the software protection bits set
          */
         if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
             JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
             JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
             nor->info->flags & SPI_NOR_HAS_LOCK) {
                 write_enable(nor);
                 write_sr(nor, 0);
                 spi_nor_wait_till_ready(nor);
         }

         if (nor->quad_enable) {
                 err = nor->quad_enable(nor);
                 if (err) {
                         dev_err(nor->dev, "quad mode not supported\n");
                         return err;
                 }
         }

This is the only meaningful thing that I can see may have changed with 
this flag.  We now have an additional write_enable before quad_enable. 
What happens if you swap those two blocks above so that quad_enable is 
called first?

If it's not that, I can't see how the extra flags can have any effect.

Regards,
Jonas

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  reply	other threads:[~2019-05-07 11:14 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-20  7:16 [PATCH v4 0/3] spi-nor block protection Jonas Bonn
2019-03-20  7:16 ` [PATCH v4 1/3] spi-nor: always respect write-protect input Jonas Bonn
2019-03-20  7:16 ` [PATCH v4 2/3] spi-nor: s25fl512s supports region locking Jonas Bonn
2019-03-20  7:39   ` Tudor.Ambarus
2019-03-21 16:48   ` Tudor.Ambarus
2019-05-07  9:53   ` Geert Uytterhoeven
2019-05-07  9:53     ` Geert Uytterhoeven
2019-05-07 10:42     ` Tudor.Ambarus
2019-05-07 10:42       ` Tudor.Ambarus
2019-05-07 10:50       ` Geert Uytterhoeven
2019-05-07 10:50         ` Geert Uytterhoeven
2019-05-07 11:13         ` Jonas Bonn [this message]
2019-05-07 11:13           ` Jonas Bonn
2019-05-07 12:52           ` Geert Uytterhoeven
2019-05-07 12:52             ` Geert Uytterhoeven
2019-05-07 13:15             ` Tudor.Ambarus
2019-05-07 13:15               ` Tudor.Ambarus
2019-05-07 13:18               ` Tudor.Ambarus
2019-05-07 13:18                 ` Tudor.Ambarus
2019-05-07 13:25               ` Tudor.Ambarus
2019-05-07 13:25                 ` Tudor.Ambarus
2019-05-07 14:33                 ` Geert Uytterhoeven
2019-05-07 14:33                   ` Geert Uytterhoeven
2019-05-08 10:44                   ` Tudor.Ambarus
2019-05-08 10:44                     ` Tudor.Ambarus
2019-05-08 13:11                     ` Geert Uytterhoeven
2019-05-08 13:11                       ` Geert Uytterhoeven
2019-05-08 14:23                       ` Tudor.Ambarus
2019-05-08 14:23                         ` Tudor.Ambarus
2019-05-08 17:00                         ` Geert Uytterhoeven
2019-05-08 17:00                           ` Geert Uytterhoeven
2019-05-09  6:55                           ` Tudor.Ambarus
2019-05-09  6:55                             ` Tudor.Ambarus
2019-05-09  9:11                             ` Geert Uytterhoeven
2019-05-09  9:11                               ` Geert Uytterhoeven
2019-05-09 10:31                               ` Tudor.Ambarus
2019-05-09 10:31                                 ` Tudor.Ambarus
2019-05-09 11:12                                 ` Geert Uytterhoeven
2019-05-09 11:12                                   ` Geert Uytterhoeven
2019-05-22 15:49                                   ` Tudor.Ambarus
2019-05-22 15:49                                     ` Tudor.Ambarus
2019-06-10  6:24                                     ` [PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes Tudor.Ambarus
2019-06-10  6:24                                       ` Tudor.Ambarus
2019-06-10  9:28                                       ` Jonas Bonn
2019-06-10  9:28                                         ` Jonas Bonn
2019-06-11  8:35                                       ` Geert Uytterhoeven
2019-06-11  8:35                                         ` Geert Uytterhoeven
2019-06-19 15:47                                         ` Tudor.Ambarus
2019-06-19 15:47                                           ` Tudor.Ambarus
2019-06-19 17:26                                           ` [PATCH v2 1/2] " Tudor.Ambarus
2019-06-19 17:26                                             ` Tudor.Ambarus
2019-06-19 17:26                                             ` [PATCH v2 2/2] mtd: spi-nor: fix description for int (*flash_is_locked)() Tudor.Ambarus
2019-06-19 17:26                                               ` Tudor.Ambarus
2019-06-19 18:51                                           ` [PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes Geert Uytterhoeven
2019-06-19 18:51                                             ` Geert Uytterhoeven
2019-06-12 16:46                                       ` Vignesh Raghavendra
2019-06-12 16:46                                         ` Vignesh Raghavendra
2019-05-09 15:57                                 ` [PATCH v4 2/3] spi-nor: s25fl512s supports region locking Vignesh Raghavendra
2019-05-09 15:57                                   ` Vignesh Raghavendra
2019-03-20  7:16 ` [PATCH v4 3/3] spi-nor: allow setting the BPNV (default locked) bit Jonas Bonn
2019-04-02  5:27   ` Vignesh Raghavendra
2019-05-01  4:42     ` [PATCH v5 1/1] spi-nor: allow setting the BPNV (powerup lock) bit Jonas Bonn

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