From: Weiwei Li <liweiwei@iscas.ac.cn>
To: ~eopxd <yueh.ting.chen@gmail.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: WeiWei Li <liweiwei@iscas.ac.cn>,
Frank Chang <frank.chang@sifive.com>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
eop Chen <eop.chen@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH qemu v4 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions
Date: Fri, 25 Mar 2022 18:51:32 +0800 [thread overview]
Message-ID: <fc5d83fe-3fe1-7c7a-a384-ef76d2fbed21@iscas.ac.cn> (raw)
In-Reply-To: <164814860220.28290.11643334198417094464-14@git.sr.ht>
在 2022/3/7 下午11:59, ~eopxd 写道:
> From: eopXD <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++
> target/riscv/vector_helper.c | 68 ++++++++++++++++++++++---
> 2 files changed, 82 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 8b24570e22..f037d1875c 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3724,6 +3724,15 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
> }
>
> if (a->vm && s->vl_eq_vlmax) {
> + if (s->vta && s->lmul < 0) {
> + /* tail elements may pass vlmax when lmul < 0
> + * set tail elements to 1s
> + */
> + uint32_t vlenb = s->cfg_ptr->vlen >> 3;
> + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
> + vreg_ofs(s, a->rd), -1,
> + vlenb, vlenb);
> + }
> int scale = s->lmul - (s->sew + 3);
> int vlmax = scale < 0 ?
> s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> @@ -3757,6 +3766,15 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
> }
>
> if (a->vm && s->vl_eq_vlmax) {
> + if (s->vta && s->lmul < 0) {
> + /* tail elements may pass vlmax when lmul < 0
> + * set tail elements to 1s
> + */
> + uint32_t vlenb = s->cfg_ptr->vlen >> 3;
> + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
> + vreg_ofs(s, a->rd), -1,
> + vlenb, vlenb);
> + }
> int scale = s->lmul - (s->sew + 3);
> int vlmax = scale < 0 ?
> s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> @@ -3809,6 +3827,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, VTA, s->vta);
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
> cpu_env, s->cfg_ptr->vlen / 8,
> @@ -3914,6 +3933,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
> }
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> + data = FIELD_DP32(data, VDATA, VTA, s->vta);
>
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs2), cpu_env,
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 0670489679..6e13d6bdcf 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4944,6 +4944,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> { \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = \
> + vext_get_total_elems(env_archcpu(env), env->vtype); \
> + uint32_t vta = vext_vta(desc); \
> target_ulong offset = s1, i_min, i; \
> \
> i_min = MAX(env->vstart, offset); \
> @@ -4953,6 +4957,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> } \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
> } \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
> + total_elems * esz); \
> }
>
> /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
> @@ -4965,12 +4972,16 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8)
> void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
> + uint32_t max_elem = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
This change seems unnecessary. It's truely vlmax here.
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = \
> + vext_get_total_elems(env_archcpu(env), env->vtype); \
> + uint32_t vta = vext_vta(desc); \
> target_ulong i_max, i; \
> \
> - i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \
> + i_max = MAX(MIN(s1 < max_elem ? max_elem - s1 : 0, vl), env->vstart); \
> for (i = env->vstart; i < i_max; ++i) { \
> if (vm || vext_elem_mask(v0, i)) { \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
> @@ -4984,6 +4995,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> } \
> \
> env->vstart = 0; \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
> + total_elems * esz); \
> }
>
> /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
> @@ -4999,6 +5013,10 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> typedef uint##BITWIDTH##_t ETYPE; \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = \
> + vext_get_total_elems(env_archcpu(env), env->vtype); \
> + uint32_t vta = vext_vta(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> @@ -5012,6 +5030,9 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> } \
> } \
> env->vstart = 0; \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
> + total_elems * esz); \
> }
>
> GEN_VEXT_VSLIE1UP(8, H1)
> @@ -5039,6 +5060,10 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> typedef uint##BITWIDTH##_t ETYPE; \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = \
> + vext_get_total_elems(env_archcpu(env), env->vtype); \
> + uint32_t vta = vext_vta(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> @@ -5052,6 +5077,9 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> } \
> } \
> env->vstart = 0; \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
> + total_elems * esz); \
> }
>
> GEN_VEXT_VSLIDE1DOWN(8, H1)
> @@ -5102,9 +5130,13 @@ GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64)
> void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2))); \
> + uint32_t max_elem = vext_max_elems(desc, ctzl(sizeof(TS2))); \
similar to above.
Regards,
Weiwei Li
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn>
To: ~eopxd <yueh.ting.chen@gmail.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: WeiWei Li <liweiwei@iscas.ac.cn>,
Frank Chang <frank.chang@sifive.com>,
eop Chen <eop.chen@sifive.com>, Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH qemu v4 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions
Date: Fri, 25 Mar 2022 18:51:32 +0800 [thread overview]
Message-ID: <fc5d83fe-3fe1-7c7a-a384-ef76d2fbed21@iscas.ac.cn> (raw)
In-Reply-To: <164814860220.28290.11643334198417094464-14@git.sr.ht>
在 2022/3/7 下午11:59, ~eopxd 写道:
> From: eopXD <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++
> target/riscv/vector_helper.c | 68 ++++++++++++++++++++++---
> 2 files changed, 82 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 8b24570e22..f037d1875c 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3724,6 +3724,15 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
> }
>
> if (a->vm && s->vl_eq_vlmax) {
> + if (s->vta && s->lmul < 0) {
> + /* tail elements may pass vlmax when lmul < 0
> + * set tail elements to 1s
> + */
> + uint32_t vlenb = s->cfg_ptr->vlen >> 3;
> + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
> + vreg_ofs(s, a->rd), -1,
> + vlenb, vlenb);
> + }
> int scale = s->lmul - (s->sew + 3);
> int vlmax = scale < 0 ?
> s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> @@ -3757,6 +3766,15 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
> }
>
> if (a->vm && s->vl_eq_vlmax) {
> + if (s->vta && s->lmul < 0) {
> + /* tail elements may pass vlmax when lmul < 0
> + * set tail elements to 1s
> + */
> + uint32_t vlenb = s->cfg_ptr->vlen >> 3;
> + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
> + vreg_ofs(s, a->rd), -1,
> + vlenb, vlenb);
> + }
> int scale = s->lmul - (s->sew + 3);
> int vlmax = scale < 0 ?
> s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> @@ -3809,6 +3827,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, VTA, s->vta);
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
> cpu_env, s->cfg_ptr->vlen / 8,
> @@ -3914,6 +3933,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
> }
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> + data = FIELD_DP32(data, VDATA, VTA, s->vta);
>
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs2), cpu_env,
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 0670489679..6e13d6bdcf 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4944,6 +4944,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> { \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = \
> + vext_get_total_elems(env_archcpu(env), env->vtype); \
> + uint32_t vta = vext_vta(desc); \
> target_ulong offset = s1, i_min, i; \
> \
> i_min = MAX(env->vstart, offset); \
> @@ -4953,6 +4957,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> } \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
> } \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
> + total_elems * esz); \
> }
>
> /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
> @@ -4965,12 +4972,16 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8)
> void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
> + uint32_t max_elem = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
This change seems unnecessary. It's truely vlmax here.
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = \
> + vext_get_total_elems(env_archcpu(env), env->vtype); \
> + uint32_t vta = vext_vta(desc); \
> target_ulong i_max, i; \
> \
> - i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \
> + i_max = MAX(MIN(s1 < max_elem ? max_elem - s1 : 0, vl), env->vstart); \
> for (i = env->vstart; i < i_max; ++i) { \
> if (vm || vext_elem_mask(v0, i)) { \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
> @@ -4984,6 +4995,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> } \
> \
> env->vstart = 0; \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
> + total_elems * esz); \
> }
>
> /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
> @@ -4999,6 +5013,10 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> typedef uint##BITWIDTH##_t ETYPE; \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = \
> + vext_get_total_elems(env_archcpu(env), env->vtype); \
> + uint32_t vta = vext_vta(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> @@ -5012,6 +5030,9 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> } \
> } \
> env->vstart = 0; \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
> + total_elems * esz); \
> }
>
> GEN_VEXT_VSLIE1UP(8, H1)
> @@ -5039,6 +5060,10 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> typedef uint##BITWIDTH##_t ETYPE; \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = \
> + vext_get_total_elems(env_archcpu(env), env->vtype); \
> + uint32_t vta = vext_vta(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> @@ -5052,6 +5077,9 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> } \
> } \
> env->vstart = 0; \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
> + total_elems * esz); \
> }
>
> GEN_VEXT_VSLIDE1DOWN(8, H1)
> @@ -5102,9 +5130,13 @@ GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64)
> void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
> CPURISCVState *env, uint32_t desc) \
> { \
> - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2))); \
> + uint32_t max_elem = vext_max_elems(desc, ctzl(sizeof(TS2))); \
similar to above.
Regards,
Weiwei Li
next prev parent reply other threads:[~2022-03-25 10:52 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 19:03 [PATCH qemu v4 00/14] Add tail agnostic behavior for rvv instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-01 9:07 ` [PATCH qemu v4 04/14] target/riscv: rvv: Add tail agnostic for vv instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-25 9:10 ` Weiwei Li
2022-03-25 9:10 ` Weiwei Li
2022-03-07 7:10 ` [PATCH qemu v4 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-07 7:32 ` [PATCH qemu v4 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-25 10:32 ` Weiwei Li
2022-03-25 10:32 ` Weiwei Li
2022-03-07 9:38 ` [PATCH qemu v4 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-07 9:43 ` [PATCH qemu v4 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-07 9:53 ` [PATCH qemu v4 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-25 10:38 ` Weiwei Li
2022-03-25 10:38 ` Weiwei Li
2022-03-07 10:04 ` [PATCH qemu v4 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-07 10:05 ` [PATCH qemu v4 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-25 10:42 ` Weiwei Li
2022-03-25 10:42 ` Weiwei Li
2022-03-07 12:21 ` [PATCH qemu v4 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-25 10:47 ` Weiwei Li
2022-03-25 10:47 ` Weiwei Li
2022-03-07 15:26 ` [PATCH qemu v4 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-07 15:59 ` [PATCH qemu v4 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-25 10:51 ` Weiwei Li [this message]
2022-03-25 10:51 ` Weiwei Li
2022-03-09 8:34 ` [PATCH qemu v4 02/14] target/riscv: rvv: Rename ambiguous esz ~eopxd
2022-03-24 19:03 ` ~eopxd
2022-03-12 6:28 ` [PATCH qemu v4 03/14] target/riscv: rvv: Early exit when vstart >= vl ~eopxd
2022-03-12 6:28 ` ~eopxd
2022-03-14 7:38 ` [PATCH qemu v4 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed ~eopxd
2022-03-14 7:38 ` ~eopxd
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