[PATCH 1/3] arm64/dts: Add SMMUs to Juno

[PATCH 1/3] arm64/dts: Add SMMUs to Juno

[Robin Murphy]

Juno has seperate MMU-401 instances in front of the DMA-330, both HDLCD
controllers, the USB host controller, the PCIe root complex, and the
CoreSight ETR. Since there is still work to do to make all the relevant
subsystems interact nicely with the presence of an IOMMU, add the nodes
to aid develompent and testing but leave them disabled by default to
avoid nasty surprises.

CC: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
CC: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
CC: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 80 ++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 334271a25f70..100810a8b929 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -29,6 +29,28 @@
 		clock-names = "apb_pclk";
 	};
 
+	smmu_pcie: iommu@2b500000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x2b500000 0x0 0x10000>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		dma-coherent;
+		status = "disabled";
+	};
+
+	smmu_etr: iommu@2b600000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x2b600000 0x0 0x10000>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		dma-coherent;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@2c010000 {
 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
 		reg = <0x0 0x2c010000 0 0x1000>,
@@ -146,6 +168,7 @@
 	etr@20070000 {
 		compatible = "arm,coresight-tmc", "arm,primecell";
 		reg = <0 0x20070000 0 0x1000>;
+		iommus = <&smmu_etr 0>;
 
 		clocks = <&soc_smc50mhz>;
 		clock-names = "apb_pclk";
@@ -404,6 +427,8 @@
 				<0 0 0 4 &gic 0 0 0 139 4>;
 		msi-parent = <&v2m_0>;
 		status = "disabled";
+		iommu-map-mask = <0x0>;	/* RC has no means to output PCI RID */
+		iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
 	};
 
 	scpi {
@@ -484,6 +509,48 @@
 
 	/include/ "juno-clocks.dtsi"
 
+	smmu_dma: iommu@7fb00000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x7fb00000 0x0 0x10000>;
+		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		dma-coherent;
+		status = "disabled";
+	};
+
+	smmu_hdlcd1: iommu@7fb10000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x7fb10000 0x0 0x10000>;
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		status = "disabled";
+	};
+
+	smmu_hdlcd0: iommu@7fb20000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x7fb20000 0x0 0x10000>;
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		status = "disabled";
+	};
+
+	smmu_usb: iommu@7fb30000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x7fb30000 0x0 0x10000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		dma-coherent;
+		status = "disabled";
+	};
+
 	dma@7ff00000 {
 		compatible = "arm,pl330", "arm,primecell";
 		reg = <0x0 0x7ff00000 0 0x1000>;
@@ -499,6 +566,15 @@
 			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_dma 0>,
+			 <&smmu_dma 1>,
+			 <&smmu_dma 2>,
+			 <&smmu_dma 3>,
+			 <&smmu_dma 4>,
+			 <&smmu_dma 5>,
+			 <&smmu_dma 6>,
+			 <&smmu_dma 7>,
+			 <&smmu_dma 8>;
 		clocks = <&soc_faxiclk>;
 		clock-names = "apb_pclk";
 	};
@@ -507,6 +583,7 @@
 		compatible = "arm,hdlcd";
 		reg = <0 0x7ff50000 0 0x1000>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_hdlcd1 0>;
 		clocks = <&scpi_clk 3>;
 		clock-names = "pxlclk";
 
@@ -521,6 +598,7 @@
 		compatible = "arm,hdlcd";
 		reg = <0 0x7ff60000 0 0x1000>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_hdlcd0 0>;
 		clocks = <&scpi_clk 3>;
 		clock-names = "pxlclk";
 
@@ -574,6 +652,7 @@
 		compatible = "generic-ohci";
 		reg = <0x0 0x7ffb0000 0x0 0x10000>;
 		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_usb 0>;
 		clocks = <&soc_usb48mhz>;
 	};
 
@@ -581,6 +660,7 @@
 		compatible = "generic-ehci";
 		reg = <0x0 0x7ffc0000 0x0 0x10000>;
 		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_usb 0>;
 		clocks = <&soc_usb48mhz>;
 	};
 
-- 
1.9.1

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[PATCH 1/3] arm64/dts: Add SMMUs to Juno

[Robin Murphy]

Juno has seperate MMU-401 instances in front of the DMA-330, both HDLCD
controllers, the USB host controller, the PCIe root complex, and the
CoreSight ETR. Since there is still work to do to make all the relevant
subsystems interact nicely with the presence of an IOMMU, add the nodes
to aid develompent and testing but leave them disabled by default to
avoid nasty surprises.

CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Sudeep Holla <sudeep.holla@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 80 ++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 334271a25f70..100810a8b929 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -29,6 +29,28 @@
 		clock-names = "apb_pclk";
 	};
 
+	smmu_pcie: iommu at 2b500000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x2b500000 0x0 0x10000>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		dma-coherent;
+		status = "disabled";
+	};
+
+	smmu_etr: iommu at 2b600000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x2b600000 0x0 0x10000>;
+		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		dma-coherent;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller at 2c010000 {
 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
 		reg = <0x0 0x2c010000 0 0x1000>,
@@ -146,6 +168,7 @@
 	etr at 20070000 {
 		compatible = "arm,coresight-tmc", "arm,primecell";
 		reg = <0 0x20070000 0 0x1000>;
+		iommus = <&smmu_etr 0>;
 
 		clocks = <&soc_smc50mhz>;
 		clock-names = "apb_pclk";
@@ -404,6 +427,8 @@
 				<0 0 0 4 &gic 0 0 0 139 4>;
 		msi-parent = <&v2m_0>;
 		status = "disabled";
+		iommu-map-mask = <0x0>;	/* RC has no means to output PCI RID */
+		iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
 	};
 
 	scpi {
@@ -484,6 +509,48 @@
 
 	/include/ "juno-clocks.dtsi"
 
+	smmu_dma: iommu at 7fb00000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x7fb00000 0x0 0x10000>;
+		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		dma-coherent;
+		status = "disabled";
+	};
+
+	smmu_hdlcd1: iommu at 7fb10000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x7fb10000 0x0 0x10000>;
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		status = "disabled";
+	};
+
+	smmu_hdlcd0: iommu at 7fb20000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x7fb20000 0x0 0x10000>;
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		status = "disabled";
+	};
+
+	smmu_usb: iommu at 7fb30000 {
+		compatible = "arm,mmu-401", "arm,smmu-v1";
+		reg = <0x0 0x7fb30000 0x0 0x10000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		#iommu-cells = <1>;
+		#global-interrupts = <1>;
+		dma-coherent;
+		status = "disabled";
+	};
+
 	dma at 7ff00000 {
 		compatible = "arm,pl330", "arm,primecell";
 		reg = <0x0 0x7ff00000 0 0x1000>;
@@ -499,6 +566,15 @@
 			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_dma 0>,
+			 <&smmu_dma 1>,
+			 <&smmu_dma 2>,
+			 <&smmu_dma 3>,
+			 <&smmu_dma 4>,
+			 <&smmu_dma 5>,
+			 <&smmu_dma 6>,
+			 <&smmu_dma 7>,
+			 <&smmu_dma 8>;
 		clocks = <&soc_faxiclk>;
 		clock-names = "apb_pclk";
 	};
@@ -507,6 +583,7 @@
 		compatible = "arm,hdlcd";
 		reg = <0 0x7ff50000 0 0x1000>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_hdlcd1 0>;
 		clocks = <&scpi_clk 3>;
 		clock-names = "pxlclk";
 
@@ -521,6 +598,7 @@
 		compatible = "arm,hdlcd";
 		reg = <0 0x7ff60000 0 0x1000>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_hdlcd0 0>;
 		clocks = <&scpi_clk 3>;
 		clock-names = "pxlclk";
 
@@ -574,6 +652,7 @@
 		compatible = "generic-ohci";
 		reg = <0x0 0x7ffb0000 0x0 0x10000>;
 		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_usb 0>;
 		clocks = <&soc_usb48mhz>;
 	};
 
@@ -581,6 +660,7 @@
 		compatible = "generic-ehci";
 		reg = <0x0 0x7ffc0000 0x0 0x10000>;
 		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu_usb 0>;
 		clocks = <&soc_usb48mhz>;
 	};
 
-- 
1.9.1

[PATCH 2/3] arm64: dts: Update AMD Seattle to generic IOMMU binding

[Robin Murphy]

MMU-401 supports stream matching, so with the SMMU implementation of
the generic "iommus" binding we can use masks to nicely simplify the
XGBE's blocks of contiguous stream IDs.

CC: Tom Lendacky <thomas.lendacky-5C7GfCeVMHo@public.gmane.org>
CC: Suravee Suthikulpanit <suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
CC: Brijesh Singh <brijeshkumar.singh-5C7GfCeVMHo@public.gmane.org>
Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
index 8e8631952497..4cd0a443d4f6 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
@@ -54,8 +54,8 @@
 		clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
 		clock-names = "dma_clk", "ptp_clk";
 		phy-mode = "xgmii";
-		#stream-id-cells = <16>;
 		dma-coherent;
+		iommus = <&xgmac0_smmu 0x00 0x17>;
 	};
 
 	xgmac1: xgmac@e0900000 {
@@ -80,8 +80,8 @@
 		clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
 		clock-names = "dma_clk", "ptp_clk";
 		phy-mode = "xgmii";
-		#stream-id-cells = <16>;
 		dma-coherent;
+		iommus = <&xgmac1_smmu 0x00 0x17>;
 	};
 
 	xgmac0_smmu: smmu@e0600000 {
@@ -93,11 +93,7 @@
 			       */
 			      <0 336 4>,
 			      <0 336 4>;
-
-		 mmu-masters = <&xgmac0
-			  0  1  2  3  4  5  6  7
-			 16 17 18 19 20 21 22 23
-		 >;
+		#iommu-cells = <2>;
 	 };
 
 	 xgmac1_smmu: smmu@e0800000 {
@@ -109,9 +105,5 @@
 			       */
 			      <0 335 4>,
 			      <0 335 4>;
-
-		 mmu-masters = <&xgmac1
-			  0  1  2  3  4  5  6  7
-			 16 17 18 19 20 21 22 23
-		 >;
+		#iommu-cells = <2>;
 	 };
-- 
1.9.1

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[PATCH 2/3] arm64: dts: Update AMD Seattle to generic IOMMU binding

[Robin Murphy]

MMU-401 supports stream matching, so with the SMMU implementation of
the generic "iommus" binding we can use masks to nicely simplify the
XGBE's blocks of contiguous stream IDs.

CC: Tom Lendacky <thomas.lendacky@amd.com>
CC: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
CC: Brijesh Singh <brijeshkumar.singh@amd.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
index 8e8631952497..4cd0a443d4f6 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
@@ -54,8 +54,8 @@
 		clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
 		clock-names = "dma_clk", "ptp_clk";
 		phy-mode = "xgmii";
-		#stream-id-cells = <16>;
 		dma-coherent;
+		iommus = <&xgmac0_smmu 0x00 0x17>;
 	};
 
 	xgmac1: xgmac at e0900000 {
@@ -80,8 +80,8 @@
 		clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
 		clock-names = "dma_clk", "ptp_clk";
 		phy-mode = "xgmii";
-		#stream-id-cells = <16>;
 		dma-coherent;
+		iommus = <&xgmac1_smmu 0x00 0x17>;
 	};
 
 	xgmac0_smmu: smmu at e0600000 {
@@ -93,11 +93,7 @@
 			       */
 			      <0 336 4>,
 			      <0 336 4>;
-
-		 mmu-masters = <&xgmac0
-			  0  1  2  3  4  5  6  7
-			 16 17 18 19 20 21 22 23
-		 >;
+		#iommu-cells = <2>;
 	 };
 
 	 xgmac1_smmu: smmu at e0800000 {
@@ -109,9 +105,5 @@
 			       */
 			      <0 335 4>,
 			      <0 335 4>;
-
-		 mmu-masters = <&xgmac1
-			  0  1  2  3  4  5  6  7
-			 16 17 18 19 20 21 22 23
-		 >;
+		#iommu-cells = <2>;
 	 };
-- 
1.9.1

[PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Robin Murphy]

With the "mmu-masters" property now deprecated and optional, the
generic binding offers a more efficient way to specify no masters.

CC: Ray Jui <rjui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
CC: Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
CC: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index d95dc408629a..65530e193e8a 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -248,7 +248,7 @@
 				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
-			mmu-masters;
+			#iommu-cells = <1>;
 		};
 
 		pinctrl: pinctrl@6501d130 {
-- 
1.9.1

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[PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Robin Murphy]

With the "mmu-masters" property now deprecated and optional, the
generic binding offers a more efficient way to specify no masters.

CC: Ray Jui <rjui@broadcom.com>
CC: Scott Branden <sbranden@broadcom.com>
CC: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index d95dc408629a..65530e193e8a 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -248,7 +248,7 @@
 				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
-			mmu-masters;
+			#iommu-cells = <1>;
 		};
 
 		pinctrl: pinctrl at 6501d130 {
-- 
1.9.1

Re: [PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Ray Jui]

Hi Robin,

On 10/17/2016 5:13 AM, Robin Murphy wrote:
> With the "mmu-masters" property now deprecated and optional, the
> generic binding offers a more efficient way to specify no masters.
>
> CC: Ray Jui <rjui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> CC: Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> CC: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
> ---
>  arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
> index d95dc408629a..65530e193e8a 100644
> --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
> @@ -248,7 +248,7 @@
>  				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
> -			mmu-masters;
> +			#iommu-cells = <1>;
>  		};
>
>  		pinctrl: pinctrl@6501d130 {
>

Thanks!

Acked-by: Ray Jui <ray.jui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
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[PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Ray Jui]

Hi Robin,

On 10/17/2016 5:13 AM, Robin Murphy wrote:
> With the "mmu-masters" property now deprecated and optional, the
> generic binding offers a more efficient way to specify no masters.
>
> CC: Ray Jui <rjui@broadcom.com>
> CC: Scott Branden <sbranden@broadcom.com>
> CC: Jon Mason <jonmason@broadcom.com>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
> index d95dc408629a..65530e193e8a 100644
> --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
> @@ -248,7 +248,7 @@
>  				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
> -			mmu-masters;
> +			#iommu-cells = <1>;
>  		};
>
>  		pinctrl: pinctrl at 6501d130 {
>

Thanks!

Acked-by: Ray Jui <ray.jui@broadcom.com>

Re: [PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Scott Branden]

Florian,

Could you add this to the queue?

On 16-10-17 02:50 PM, Ray Jui wrote:
> Hi Robin,
>
> On 10/17/2016 5:13 AM, Robin Murphy wrote:
>> With the "mmu-masters" property now deprecated and optional, the
>> generic binding offers a more efficient way to specify no masters.
>>
>> CC: Ray Jui <rjui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> CC: Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> CC: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
>> ---
>>  arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> index d95dc408629a..65530e193e8a 100644
>> --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> @@ -248,7 +248,7 @@
>>                       <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
>>                       <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
>>                       <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
>> -            mmu-masters;
>> +            #iommu-cells = <1>;
>>          };
>>
>>          pinctrl: pinctrl@6501d130 {
>>
>
> Thanks!
>
> Acked-by: Ray Jui <ray.jui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>

Thanks,
  Scott
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[PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Scott Branden]

Florian,

Could you add this to the queue?

On 16-10-17 02:50 PM, Ray Jui wrote:
> Hi Robin,
>
> On 10/17/2016 5:13 AM, Robin Murphy wrote:
>> With the "mmu-masters" property now deprecated and optional, the
>> generic binding offers a more efficient way to specify no masters.
>>
>> CC: Ray Jui <rjui@broadcom.com>
>> CC: Scott Branden <sbranden@broadcom.com>
>> CC: Jon Mason <jonmason@broadcom.com>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>>  arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> index d95dc408629a..65530e193e8a 100644
>> --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
>> @@ -248,7 +248,7 @@
>>                       <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
>>                       <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
>>                       <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
>> -            mmu-masters;
>> +            #iommu-cells = <1>;
>>          };
>>
>>          pinctrl: pinctrl at 6501d130 {
>>
>
> Thanks!
>
> Acked-by: Ray Jui <ray.jui@broadcom.com>

Thanks,
  Scott

Re: [PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Florian Fainelli]

On 10/17/2016 05:13 AM, Robin Murphy wrote:
> With the "mmu-masters" property now deprecated and optional, the
> generic binding offers a more efficient way to specify no masters.
> 
> CC: Ray Jui <rjui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> CC: Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> CC: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>

Applied, did you use get_maintainers.pl for this file? It did not land
in bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org and as such did not get picked
by the patchwork instance behind..
-- 
Florian
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[PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Florian Fainelli]

On 10/17/2016 05:13 AM, Robin Murphy wrote:
> With the "mmu-masters" property now deprecated and optional, the
> generic binding offers a more efficient way to specify no masters.
> 
> CC: Ray Jui <rjui@broadcom.com>
> CC: Scott Branden <sbranden@broadcom.com>
> CC: Jon Mason <jonmason@broadcom.com>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

Applied, did you use get_maintainers.pl for this file? It did not land
in bcm-kernel-feedback-list at broadcom.com and as such did not get picked
by the patchwork instance behind..
-- 
Florian

Re: [PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Robin Murphy]

On 18/10/16 01:58, Florian Fainelli wrote:
> On 10/17/2016 05:13 AM, Robin Murphy wrote:
>> With the "mmu-masters" property now deprecated and optional, the
>> generic binding offers a more efficient way to specify no masters.
>>
>> CC: Ray Jui <rjui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> CC: Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> CC: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
> 
> Applied, did you use get_maintainers.pl for this file? It did not land
> in bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org and as such did not get picked
> by the patchwork instance behind..

Oops, sorry! I somehow managed to overlook that - I'll try paying closer
attention in future :)

Thanks,
Robin.
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[PATCH 3/3] arm64: dts: Update Broadcom NS2 to generic IOMMU binding

[Robin Murphy]

On 18/10/16 01:58, Florian Fainelli wrote:
> On 10/17/2016 05:13 AM, Robin Murphy wrote:
>> With the "mmu-masters" property now deprecated and optional, the
>> generic binding offers a more efficient way to specify no masters.
>>
>> CC: Ray Jui <rjui@broadcom.com>
>> CC: Scott Branden <sbranden@broadcom.com>
>> CC: Jon Mason <jonmason@broadcom.com>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> 
> Applied, did you use get_maintainers.pl for this file? It did not land
> in bcm-kernel-feedback-list at broadcom.com and as such did not get picked
> by the patchwork instance behind..

Oops, sorry! I somehow managed to overlook that - I'll try paying closer
attention in future :)

Thanks,
Robin.

Re: [PATCH 1/3] arm64/dts: Add SMMUs to Juno

[Sudeep Holla]

On 17/10/16 13:13, Robin Murphy wrote:
> Juno has seperate MMU-401 instances in front of the DMA-330, both HDLCD
> controllers, the USB host controller, the PCIe root complex, and the
> CoreSight ETR. Since there is still work to do to make all the relevant
> subsystems interact nicely with the presence of an IOMMU, add the nodes
> to aid develompent and testing but leave them disabled by default to
> avoid nasty surprises.
>
> CC: Liviu Dudau <liviu.dudau-5wv7dgnIgG8@public.gmane.org>
> CC: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>

Applied to [1] with $subject reformatted and typos fixed

-- 
Regards,
Sudeep

[1] git.kernel.org/sudeep.holla/linux/h/juno-dt/for-next
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[PATCH 1/3] arm64/dts: Add SMMUs to Juno

[Sudeep Holla]

On 17/10/16 13:13, Robin Murphy wrote:
> Juno has seperate MMU-401 instances in front of the DMA-330, both HDLCD
> controllers, the USB host controller, the PCIe root complex, and the
> CoreSight ETR. Since there is still work to do to make all the relevant
> subsystems interact nicely with the presence of an IOMMU, add the nodes
> to aid develompent and testing but leave them disabled by default to
> avoid nasty surprises.
>
> CC: Liviu Dudau <liviu.dudau@arm.com>
> CC: Sudeep Holla <sudeep.holla@arm.com>

Applied to [1] with $subject reformatted and typos fixed

-- 
Regards,
Sudeep

[1] git.kernel.org/sudeep.holla/linux/h/juno-dt/for-next