* [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-06-24 13:44 ` Cédric Le Goater
2022-07-27 17:29 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 02/12] ppc/pnv: add PnvPHB base/proxy device Daniel Henrique Barboza
` (11 subsequent siblings)
12 siblings, 2 replies; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
regions, registering it via pci_register_root_bus() and then setup the
iommu.
We'll want to init the bus from outside pnv_phb3.c when the bus is
removed from the PnvPHB3 device and put into a new parent PnvPHB device.
The new pnv_phb3_bus_init() helper will be used by the parent to init
the bus when using the PHB3 backend.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb3.c | 39 ++++++++++++++++++++--------------
include/hw/pci-host/pnv_phb3.h | 1 +
2 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index d58d3c1701..058cbab555 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -986,6 +986,28 @@ static void pnv_phb3_instance_init(Object *obj)
}
+void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
+{
+ PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+
+ /*
+ * PHB3 doesn't support IO space. However, qemu gets very upset if
+ * we don't have an IO region to anchor IO BARs onto so we just
+ * initialize one which we never hook up to anything
+ */
+ memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
+ memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
+ PCI_MMIO_TOTAL_SIZE);
+
+ pci->bus = pci_register_root_bus(dev,
+ dev->id ? dev->id : NULL,
+ pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
+ &phb->pci_mmio, &phb->pci_io,
+ 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
+
+ pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
+}
+
static void pnv_phb3_realize(DeviceState *dev, Error **errp)
{
PnvPHB3 *phb = PNV_PHB3(dev);
@@ -1035,22 +1057,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
"phb3-regs", 0x1000);
- /*
- * PHB3 doesn't support IO space. However, qemu gets very upset if
- * we don't have an IO region to anchor IO BARs onto so we just
- * initialize one which we never hook up to anything
- */
- memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
- memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
- PCI_MMIO_TOTAL_SIZE);
-
- pci->bus = pci_register_root_bus(dev,
- dev->id ? dev->id : NULL,
- pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
- &phb->pci_mmio, &phb->pci_io,
- 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
-
- pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
+ pnv_phb3_bus_init(dev, phb);
pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
phb->phb_id, phb->chip_id);
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index af6ec83cf6..1375f18fc1 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -164,5 +164,6 @@ uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
void pnv_phb3_update_regions(PnvPHB3 *phb);
void pnv_phb3_remap_irqs(PnvPHB3 *phb);
+void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb);
#endif /* PCI_HOST_PNV_PHB3_H */
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper
2022-06-24 8:49 ` [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper Daniel Henrique Barboza
@ 2022-06-24 13:44 ` Cédric Le Goater
2022-06-27 17:09 ` Daniel Henrique Barboza
2022-07-27 17:29 ` Frederic Barrat
1 sibling, 1 reply; 30+ messages in thread
From: Cédric Le Goater @ 2022-06-24 13:44 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-ppc, fbarrat, Michael S. Tsirkin, Gerd Hoffmann
(Adding people who could help making the right change)
On 6/24/22 10:49, Daniel Henrique Barboza wrote:
> The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
> regions, registering it via pci_register_root_bus() and then setup the
> iommu.
>
> We'll want to init the bus from outside pnv_phb3.c when the bus is
> removed from the PnvPHB3 device and put into a new parent PnvPHB device.
> The new pnv_phb3_bus_init() helper will be used by the parent to init
> the bus when using the PHB3 backend.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
> hw/pci-host/pnv_phb3.c | 39 ++++++++++++++++++++--------------
> include/hw/pci-host/pnv_phb3.h | 1 +
> 2 files changed, 24 insertions(+), 16 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
> index d58d3c1701..058cbab555 100644
> --- a/hw/pci-host/pnv_phb3.c
> +++ b/hw/pci-host/pnv_phb3.c
> @@ -986,6 +986,28 @@ static void pnv_phb3_instance_init(Object *obj)
>
> }
>
> +void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
> +{
> + PCIHostState *pci = PCI_HOST_BRIDGE(dev);
> +
> + /*
> + * PHB3 doesn't support IO space. However, qemu gets very upset if
> + * we don't have an IO region to anchor IO BARs onto so we just
> + * initialize one which we never hook up to anything
> + */
> + memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
> + memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
> + PCI_MMIO_TOTAL_SIZE);
Could we change the root port settings with io-reserve=0 to remove
the IO range ?
Thanks,
C.
> + pci->bus = pci_register_root_bus(dev,
> + dev->id ? dev->id : NULL,
> + pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
> + &phb->pci_mmio, &phb->pci_io,
> + 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
> +
> + pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
> +}
> +
> static void pnv_phb3_realize(DeviceState *dev, Error **errp)
> {
> PnvPHB3 *phb = PNV_PHB3(dev);
> @@ -1035,22 +1057,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
> memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
> "phb3-regs", 0x1000);
>
> - /*
> - * PHB3 doesn't support IO space. However, qemu gets very upset if
> - * we don't have an IO region to anchor IO BARs onto so we just
> - * initialize one which we never hook up to anything
> - */
> - memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
> - memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
> - PCI_MMIO_TOTAL_SIZE);
> -
> - pci->bus = pci_register_root_bus(dev,
> - dev->id ? dev->id : NULL,
> - pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
> - &phb->pci_mmio, &phb->pci_io,
> - 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
> -
> - pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
> + pnv_phb3_bus_init(dev, phb);
>
> pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
> phb->phb_id, phb->chip_id);
> diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
> index af6ec83cf6..1375f18fc1 100644
> --- a/include/hw/pci-host/pnv_phb3.h
> +++ b/include/hw/pci-host/pnv_phb3.h
> @@ -164,5 +164,6 @@ uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
> void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
> void pnv_phb3_update_regions(PnvPHB3 *phb);
> void pnv_phb3_remap_irqs(PnvPHB3 *phb);
> +void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb);
>
> #endif /* PCI_HOST_PNV_PHB3_H */
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper
2022-06-24 13:44 ` Cédric Le Goater
@ 2022-06-27 17:09 ` Daniel Henrique Barboza
0 siblings, 0 replies; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-27 17:09 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel
Cc: qemu-ppc, fbarrat, Michael S. Tsirkin, Gerd Hoffmann
On 6/24/22 10:44, Cédric Le Goater wrote:
> (Adding people who could help making the right change)
>
> On 6/24/22 10:49, Daniel Henrique Barboza wrote:
>> The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
>> regions, registering it via pci_register_root_bus() and then setup the
>> iommu.
>>
>> We'll want to init the bus from outside pnv_phb3.c when the bus is
>> removed from the PnvPHB3 device and put into a new parent PnvPHB device.
>> The new pnv_phb3_bus_init() helper will be used by the parent to init
>> the bus when using the PHB3 backend.
>>
>> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>> ---
>> hw/pci-host/pnv_phb3.c | 39 ++++++++++++++++++++--------------
>> include/hw/pci-host/pnv_phb3.h | 1 +
>> 2 files changed, 24 insertions(+), 16 deletions(-)
>>
>> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
>> index d58d3c1701..058cbab555 100644
>> --- a/hw/pci-host/pnv_phb3.c
>> +++ b/hw/pci-host/pnv_phb3.c
>> @@ -986,6 +986,28 @@ static void pnv_phb3_instance_init(Object *obj)
>> }
>> +void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
>> +{
>> + PCIHostState *pci = PCI_HOST_BRIDGE(dev);
>> +
>> + /*
>> + * PHB3 doesn't support IO space. However, qemu gets very upset if
>> + * we don't have an IO region to anchor IO BARs onto so we just
>> + * initialize one which we never hook up to anything
>> + */
>> + memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
>> + memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
>> + PCI_MMIO_TOTAL_SIZE);
>
>
> Could we change the root port settings with io-reserve=0 to remove
> the IO range ?
I don't think so, and I think this is what the comment right before refers to. Even
with io-reserve=0 I can't remove phb->pci_io. The code breaks in the middle of
the root port realize core code, pci_bridge_initfn(), when trying to create the
bridge windows via
br->windows = pci_bridge_region_init(br);
There's no verification of io-reserve value (via res_reserve.io) influencing the
init of those regions. What I can see related to io-reserve, for example, is this
piece of code from gen_rp_realize() in gen_pcie_root_port.c:
if (!grp->res_reserve.io) {
pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
PCI_COMMAND_IO);
d->wmask[PCI_IO_BASE] = 0;
d->wmask[PCI_IO_LIMIT] = 0;
}
Of course that this piece of code does nothing to avoid the segfault described
below.
I think this might be worth a investigation later on as a follow up. For now
I'd like to focus on pnv-phb changes (including the user created support)
before the freeze.
Thanks,
Daniel
>
>
> Thanks,
>
> C.
>
>
>
>> + pci->bus = pci_register_root_bus(dev,
>> + dev->id ? dev->id : NULL,
>> + pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
>> + &phb->pci_mmio, &phb->pci_io,
>> + 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
>> +
>> + pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
>> +}
>> +
>> static void pnv_phb3_realize(DeviceState *dev, Error **errp)
>> {
>> PnvPHB3 *phb = PNV_PHB3(dev);
>> @@ -1035,22 +1057,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
>> memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
>> "phb3-regs", 0x1000);
>> - /*
>> - * PHB3 doesn't support IO space. However, qemu gets very upset if
>> - * we don't have an IO region to anchor IO BARs onto so we just
>> - * initialize one which we never hook up to anything
>> - */
>> - memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
>> - memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
>> - PCI_MMIO_TOTAL_SIZE);
>> -
>> - pci->bus = pci_register_root_bus(dev,
>> - dev->id ? dev->id : NULL,
>> - pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
>> - &phb->pci_mmio, &phb->pci_io,
>> - 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
>> -
>> - pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
>> + pnv_phb3_bus_init(dev, phb);
>> pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
>> phb->phb_id, phb->chip_id);
>> diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
>> index af6ec83cf6..1375f18fc1 100644
>> --- a/include/hw/pci-host/pnv_phb3.h
>> +++ b/include/hw/pci-host/pnv_phb3.h
>> @@ -164,5 +164,6 @@ uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
>> void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
>> void pnv_phb3_update_regions(PnvPHB3 *phb);
>> void pnv_phb3_remap_irqs(PnvPHB3 *phb);
>> +void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb);
>> #endif /* PCI_HOST_PNV_PHB3_H */
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper
2022-06-24 8:49 ` [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper Daniel Henrique Barboza
2022-06-24 13:44 ` Cédric Le Goater
@ 2022-07-27 17:29 ` Frederic Barrat
1 sibling, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:29 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
> regions, registering it via pci_register_root_bus() and then setup the
> iommu.
>
> We'll want to init the bus from outside pnv_phb3.c when the bus is
> removed from the PnvPHB3 device and put into a new parent PnvPHB device.
> The new pnv_phb3_bus_init() helper will be used by the parent to init
> the bus when using the PHB3 backend.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb3.c | 39 ++++++++++++++++++++--------------
> include/hw/pci-host/pnv_phb3.h | 1 +
> 2 files changed, 24 insertions(+), 16 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
> index d58d3c1701..058cbab555 100644
> --- a/hw/pci-host/pnv_phb3.c
> +++ b/hw/pci-host/pnv_phb3.c
> @@ -986,6 +986,28 @@ static void pnv_phb3_instance_init(Object *obj)
>
> }
>
> +void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
> +{
> + PCIHostState *pci = PCI_HOST_BRIDGE(dev);
> +
> + /*
> + * PHB3 doesn't support IO space. However, qemu gets very upset if
> + * we don't have an IO region to anchor IO BARs onto so we just
> + * initialize one which we never hook up to anything
> + */
> + memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
> + memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
> + PCI_MMIO_TOTAL_SIZE);
> +
> + pci->bus = pci_register_root_bus(dev,
> + dev->id ? dev->id : NULL,
> + pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
> + &phb->pci_mmio, &phb->pci_io,
> + 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
> +
> + pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
> +}
> +
> static void pnv_phb3_realize(DeviceState *dev, Error **errp)
> {
> PnvPHB3 *phb = PNV_PHB3(dev);
> @@ -1035,22 +1057,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
> memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
> "phb3-regs", 0x1000);
>
> - /*
> - * PHB3 doesn't support IO space. However, qemu gets very upset if
> - * we don't have an IO region to anchor IO BARs onto so we just
> - * initialize one which we never hook up to anything
> - */
> - memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
> - memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
> - PCI_MMIO_TOTAL_SIZE);
> -
> - pci->bus = pci_register_root_bus(dev,
> - dev->id ? dev->id : NULL,
> - pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
> - &phb->pci_mmio, &phb->pci_io,
> - 0, 4, TYPE_PNV_PHB3_ROOT_BUS);
> -
> - pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
> + pnv_phb3_bus_init(dev, phb);
>
> pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
> phb->phb_id, phb->chip_id);
> diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
> index af6ec83cf6..1375f18fc1 100644
> --- a/include/hw/pci-host/pnv_phb3.h
> +++ b/include/hw/pci-host/pnv_phb3.h
> @@ -164,5 +164,6 @@ uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
> void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
> void pnv_phb3_update_regions(PnvPHB3 *phb);
> void pnv_phb3_remap_irqs(PnvPHB3 *phb);
> +void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb);
>
> #endif /* PCI_HOST_PNV_PHB3_H */
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 02/12] ppc/pnv: add PnvPHB base/proxy device
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
2022-06-24 8:49 ` [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:29 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 03/12] ppc/pnv: turn PnvPHB3 into a PnvPHB backend Daniel Henrique Barboza
` (10 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and index
properties. It also has a 'backend' pointer that will be initialized
with the PHB implementation that the device is going to use.
The initialization of the PHB backend is done by checking the PHB
version via a 'version' attribute that can be set via a global machine
property. The 'version' field will be used to make adjustments based on
the running version, e.g. PHB3 uses a 'chip' reference while PHB4 uses
'pec'. To init the PnvPHB bus we'll rely on helpers for each version.
The version 3 helper is already added (pnv_phb3_bus_init), the PHB4
helper will be added later on.
For now let's add the basic logic of the PnvPHB object, which consists
mostly of pnv_phb_realize() doing all the work of checking the
phb->version set, initializing the proper backend, passing through its
attributes to the chosen backend, finalizing the backend realize and
adding a root port in the end.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/meson.build | 3 +-
hw/pci-host/pnv_phb.c | 124 ++++++++++++++++++++++++++++++++++++++++
hw/pci-host/pnv_phb.h | 39 +++++++++++++
3 files changed, 165 insertions(+), 1 deletion(-)
create mode 100644 hw/pci-host/pnv_phb.c
create mode 100644 hw/pci-host/pnv_phb.h
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index c07596d0d1..e832babc9d 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -35,5 +35,6 @@ specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files(
'pnv_phb3_msi.c',
'pnv_phb3_pbcq.c',
'pnv_phb4.c',
- 'pnv_phb4_pec.c'
+ 'pnv_phb4_pec.c',
+ 'pnv_phb.c',
))
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
new file mode 100644
index 0000000000..6fefff7d44
--- /dev/null
+++ b/hw/pci-host/pnv_phb.c
@@ -0,0 +1,124 @@
+/*
+ * QEMU PowerPC PowerNV Proxy PHB model
+ *
+ * Copyright (c) 2022, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/visitor.h"
+#include "qapi/error.h"
+#include "hw/pci-host/pnv_phb.h"
+#include "hw/pci-host/pnv_phb3.h"
+#include "hw/pci-host/pnv_phb4.h"
+#include "hw/ppc/pnv.h"
+#include "hw/qdev-properties.h"
+#include "qom/object.h"
+
+
+static void pnv_phb_realize(DeviceState *dev, Error **errp)
+{
+ PnvPHB *phb = PNV_PHB(dev);
+ PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+ g_autofree char *phb_typename = NULL;
+ g_autofree char *phb_rootport_typename = NULL;
+
+ if (!phb->version) {
+ error_setg(errp, "version not specified");
+ return;
+ }
+
+ switch (phb->version) {
+ case 3:
+ phb_typename = g_strdup(TYPE_PNV_PHB3);
+ phb_rootport_typename = g_strdup(TYPE_PNV_PHB3_ROOT_PORT);
+ break;
+ case 4:
+ phb_typename = g_strdup(TYPE_PNV_PHB4);
+ phb_rootport_typename = g_strdup(TYPE_PNV_PHB4_ROOT_PORT);
+ break;
+ case 5:
+ phb_typename = g_strdup(TYPE_PNV_PHB5);
+ phb_rootport_typename = g_strdup(TYPE_PNV_PHB5_ROOT_PORT);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ phb->backend = object_new(phb_typename);
+ object_property_add_child(OBJECT(dev), "phb-backend", phb->backend);
+
+ /* Passthrough child device properties to the proxy device */
+ object_property_set_uint(phb->backend, "index", phb->phb_id, errp);
+ object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp);
+ object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp);
+
+ if (phb->version == 3) {
+ object_property_set_link(phb->backend, "chip",
+ OBJECT(phb->chip), errp);
+ } else {
+ object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp);
+ }
+
+ if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) {
+ return;
+ }
+
+ if (phb->version == 3) {
+ pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend));
+ }
+
+ pnv_phb_attach_root_port(pci, phb_rootport_typename,
+ phb->phb_id, phb->chip_id);
+}
+
+static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
+ PCIBus *rootbus)
+{
+ PnvPHB *phb = PNV_PHB(host_bridge);
+
+ snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
+ phb->chip_id, phb->phb_id);
+ return phb->bus_path;
+}
+
+static Property pnv_phb_properties[] = {
+ DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0),
+ DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0),
+ DEFINE_PROP_UINT32("version", PnvPHB, version, 0),
+
+ DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *),
+
+ DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC,
+ PnvPhb4PecState *),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pnv_phb_class_init(ObjectClass *klass, void *data)
+{
+ PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ hc->root_bus_path = pnv_phb_root_bus_path;
+ dc->realize = pnv_phb_realize;
+ device_class_set_props(dc, pnv_phb_properties);
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->user_creatable = false;
+}
+
+static void pnv_phb_register_type(void)
+{
+ static const TypeInfo pnv_phb_type_info = {
+ .name = TYPE_PNV_PHB,
+ .parent = TYPE_PCIE_HOST_BRIDGE,
+ .instance_size = sizeof(PnvPHB),
+ .class_init = pnv_phb_class_init,
+ };
+
+ type_register_static(&pnv_phb_type_info);
+}
+type_init(pnv_phb_register_type)
diff --git a/hw/pci-host/pnv_phb.h b/hw/pci-host/pnv_phb.h
new file mode 100644
index 0000000000..a7cc8610e2
--- /dev/null
+++ b/hw/pci-host/pnv_phb.h
@@ -0,0 +1,39 @@
+/*
+ * QEMU PowerPC PowerNV Proxy PHB model
+ *
+ * Copyright (c) 2022, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#ifndef PCI_HOST_PNV_PHB_H
+#define PCI_HOST_PNV_PHB_H
+
+#include "hw/pci/pcie_host.h"
+#include "hw/pci/pcie_port.h"
+#include "qom/object.h"
+
+typedef struct PnvChip PnvChip;
+typedef struct PnvPhb4PecState PnvPhb4PecState;
+
+struct PnvPHB {
+ PCIExpressHost parent_obj;
+
+ uint32_t chip_id;
+ uint32_t phb_id;
+ uint32_t version;
+ char bus_path[8];
+
+ PnvChip *chip;
+
+ PnvPhb4PecState *pec;
+
+ /* The PHB backend (PnvPHB3, PnvPHB4 ...) being used */
+ Object *backend;
+};
+
+#define TYPE_PNV_PHB "pnv-phb"
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB, PNV_PHB)
+
+#endif /* PCI_HOST_PNV_PHB_H */
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 02/12] ppc/pnv: add PnvPHB base/proxy device
2022-06-24 8:49 ` [PATCH v3 02/12] ppc/pnv: add PnvPHB base/proxy device Daniel Henrique Barboza
@ 2022-07-27 17:29 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:29 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> The PnvPHB device is going to be the base device for all other powernv
> PHBs. It consists of a device that has the same user API as the other
> PHB, namely being a PCIHostBridge and having chip-id and index
> properties. It also has a 'backend' pointer that will be initialized
> with the PHB implementation that the device is going to use.
>
> The initialization of the PHB backend is done by checking the PHB
> version via a 'version' attribute that can be set via a global machine
> property. The 'version' field will be used to make adjustments based on
> the running version, e.g. PHB3 uses a 'chip' reference while PHB4 uses
> 'pec'. To init the PnvPHB bus we'll rely on helpers for each version.
> The version 3 helper is already added (pnv_phb3_bus_init), the PHB4
> helper will be added later on.
>
> For now let's add the basic logic of the PnvPHB object, which consists
> mostly of pnv_phb_realize() doing all the work of checking the
> phb->version set, initializing the proper backend, passing through its
> attributes to the chosen backend, finalizing the backend realize and
> adding a root port in the end.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/meson.build | 3 +-
> hw/pci-host/pnv_phb.c | 124 ++++++++++++++++++++++++++++++++++++++++
> hw/pci-host/pnv_phb.h | 39 +++++++++++++
> 3 files changed, 165 insertions(+), 1 deletion(-)
> create mode 100644 hw/pci-host/pnv_phb.c
> create mode 100644 hw/pci-host/pnv_phb.h
>
> diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
> index c07596d0d1..e832babc9d 100644
> --- a/hw/pci-host/meson.build
> +++ b/hw/pci-host/meson.build
> @@ -35,5 +35,6 @@ specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files(
> 'pnv_phb3_msi.c',
> 'pnv_phb3_pbcq.c',
> 'pnv_phb4.c',
> - 'pnv_phb4_pec.c'
> + 'pnv_phb4_pec.c',
> + 'pnv_phb.c',
> ))
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> new file mode 100644
> index 0000000000..6fefff7d44
> --- /dev/null
> +++ b/hw/pci-host/pnv_phb.c
> @@ -0,0 +1,124 @@
> +/*
> + * QEMU PowerPC PowerNV Proxy PHB model
> + *
> + * Copyright (c) 2022, IBM Corporation.
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qapi/visitor.h"
> +#include "qapi/error.h"
> +#include "hw/pci-host/pnv_phb.h"
> +#include "hw/pci-host/pnv_phb3.h"
> +#include "hw/pci-host/pnv_phb4.h"
> +#include "hw/ppc/pnv.h"
> +#include "hw/qdev-properties.h"
> +#include "qom/object.h"
> +
> +
> +static void pnv_phb_realize(DeviceState *dev, Error **errp)
> +{
> + PnvPHB *phb = PNV_PHB(dev);
> + PCIHostState *pci = PCI_HOST_BRIDGE(dev);
> + g_autofree char *phb_typename = NULL;
> + g_autofree char *phb_rootport_typename = NULL;
> +
> + if (!phb->version) {
> + error_setg(errp, "version not specified");
> + return;
> + }
> +
> + switch (phb->version) {
> + case 3:
> + phb_typename = g_strdup(TYPE_PNV_PHB3);
> + phb_rootport_typename = g_strdup(TYPE_PNV_PHB3_ROOT_PORT);
> + break;
> + case 4:
> + phb_typename = g_strdup(TYPE_PNV_PHB4);
> + phb_rootport_typename = g_strdup(TYPE_PNV_PHB4_ROOT_PORT);
> + break;
> + case 5:
> + phb_typename = g_strdup(TYPE_PNV_PHB5);
> + phb_rootport_typename = g_strdup(TYPE_PNV_PHB5_ROOT_PORT);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + phb->backend = object_new(phb_typename);
> + object_property_add_child(OBJECT(dev), "phb-backend", phb->backend);
> +
> + /* Passthrough child device properties to the proxy device */
> + object_property_set_uint(phb->backend, "index", phb->phb_id, errp);
> + object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp);
> + object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp);
> +
> + if (phb->version == 3) {
> + object_property_set_link(phb->backend, "chip",
> + OBJECT(phb->chip), errp);
> + } else {
> + object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp);
> + }
> +
> + if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) {
> + return;
> + }
> +
> + if (phb->version == 3) {
> + pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend));
> + }
> +
> + pnv_phb_attach_root_port(pci, phb_rootport_typename,
> + phb->phb_id, phb->chip_id);
> +}
> +
> +static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
> + PCIBus *rootbus)
> +{
> + PnvPHB *phb = PNV_PHB(host_bridge);
> +
> + snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
> + phb->chip_id, phb->phb_id);
> + return phb->bus_path;
> +}
> +
> +static Property pnv_phb_properties[] = {
> + DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0),
> + DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0),
> + DEFINE_PROP_UINT32("version", PnvPHB, version, 0),
> +
> + DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *),
> +
> + DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC,
> + PnvPhb4PecState *),
> +
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void pnv_phb_class_init(ObjectClass *klass, void *data)
> +{
> + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + hc->root_bus_path = pnv_phb_root_bus_path;
> + dc->realize = pnv_phb_realize;
> + device_class_set_props(dc, pnv_phb_properties);
> + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
> + dc->user_creatable = false;
> +}
> +
> +static void pnv_phb_register_type(void)
> +{
> + static const TypeInfo pnv_phb_type_info = {
> + .name = TYPE_PNV_PHB,
> + .parent = TYPE_PCIE_HOST_BRIDGE,
> + .instance_size = sizeof(PnvPHB),
> + .class_init = pnv_phb_class_init,
> + };
> +
> + type_register_static(&pnv_phb_type_info);
> +}
> +type_init(pnv_phb_register_type)
> diff --git a/hw/pci-host/pnv_phb.h b/hw/pci-host/pnv_phb.h
> new file mode 100644
> index 0000000000..a7cc8610e2
> --- /dev/null
> +++ b/hw/pci-host/pnv_phb.h
> @@ -0,0 +1,39 @@
> +/*
> + * QEMU PowerPC PowerNV Proxy PHB model
> + *
> + * Copyright (c) 2022, IBM Corporation.
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
> + */
> +
> +#ifndef PCI_HOST_PNV_PHB_H
> +#define PCI_HOST_PNV_PHB_H
> +
> +#include "hw/pci/pcie_host.h"
> +#include "hw/pci/pcie_port.h"
> +#include "qom/object.h"
> +
> +typedef struct PnvChip PnvChip;
> +typedef struct PnvPhb4PecState PnvPhb4PecState;
> +
> +struct PnvPHB {
> + PCIExpressHost parent_obj;
> +
> + uint32_t chip_id;
> + uint32_t phb_id;
> + uint32_t version;
> + char bus_path[8];
> +
> + PnvChip *chip;
> +
> + PnvPhb4PecState *pec;
> +
> + /* The PHB backend (PnvPHB3, PnvPHB4 ...) being used */
> + Object *backend;
> +};
> +
> +#define TYPE_PNV_PHB "pnv-phb"
> +OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB, PNV_PHB)
> +
> +#endif /* PCI_HOST_PNV_PHB_H */
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 03/12] ppc/pnv: turn PnvPHB3 into a PnvPHB backend
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
2022-06-24 8:49 ` [PATCH v3 01/12] ppc/pnv: add PHB3 bus init helper Daniel Henrique Barboza
2022-06-24 8:49 ` [PATCH v3 02/12] ppc/pnv: add PnvPHB base/proxy device Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:31 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 04/12] ppc/pnv: add PHB4 bus init helper Daniel Henrique Barboza
` (9 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
We need a handful of changes that needs to be done in a single swoop to
turn PnvPHB3 into a PnvPHB backend.
In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a
couple of instances in pnv_phb3.c that needs to access the PCI bus, so a
phb_base pointer is added to allow access to the parent PnvPHB. The
PnvPHB3 root port will now be connected to a PnvPHB object.
In pnv.c, the powernv8 machine chip8 will now hold an array of PnvPHB
objects. pnv_get_phb3_child() needs to be adapted to return the PnvPHB3
backend from the PnvPHB child. A global property is added in
pnv_machine_power8_class_init() to ensure that all PnvPHBs are created
with phb->version = 3.
After all these changes we're still able to boot a powernv8 machine with
default settings. The real gain will come with user created PnvPHB
devices, coming up next.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb3.c | 27 +++++----------------------
hw/ppc/pnv.c | 21 +++++++++++++++------
include/hw/pci-host/pnv_phb3.h | 5 ++++-
include/hw/ppc/pnv.h | 3 ++-
4 files changed, 26 insertions(+), 30 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index 058cbab555..ad5d67a8e8 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -11,6 +11,7 @@
#include "qapi/visitor.h"
#include "qapi/error.h"
#include "hw/pci-host/pnv_phb3_regs.h"
+#include "hw/pci-host/pnv_phb.h"
#include "hw/pci-host/pnv_phb3.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pcie_port.h"
@@ -26,7 +27,7 @@
static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb)
{
- PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+ PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
uint8_t bus, devfn;
@@ -590,7 +591,7 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size)
uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size)
{
PnvPHB3 *phb = opaque;
- PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+ PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
uint64_t val;
if ((off & 0xfffc) == PHB_CONFIG_DATA) {
@@ -1011,7 +1012,6 @@ void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
static void pnv_phb3_realize(DeviceState *dev, Error **errp)
{
PnvPHB3 *phb = PNV_PHB3(dev);
- PCIHostState *pci = PCI_HOST_BRIDGE(dev);
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
@@ -1056,11 +1056,6 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
/* Controller Registers */
memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
"phb3-regs", 0x1000);
-
- pnv_phb3_bus_init(dev, phb);
-
- pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
- phb->phb_id, phb->chip_id);
}
void pnv_phb3_update_regions(PnvPHB3 *phb)
@@ -1085,38 +1080,26 @@ void pnv_phb3_update_regions(PnvPHB3 *phb)
pnv_phb3_check_all_m64s(phb);
}
-static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge,
- PCIBus *rootbus)
-{
- PnvPHB3 *phb = PNV_PHB3(host_bridge);
-
- snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
- phb->chip_id, phb->phb_id);
- return phb->bus_path;
-}
-
static Property pnv_phb3_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0),
DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *),
+ DEFINE_PROP_LINK("phb-base", PnvPHB3, phb_base, TYPE_PNV_PHB, PnvPHB *),
DEFINE_PROP_END_OF_LIST(),
};
static void pnv_phb3_class_init(ObjectClass *klass, void *data)
{
- PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- hc->root_bus_path = pnv_phb3_root_bus_path;
dc->realize = pnv_phb3_realize;
device_class_set_props(dc, pnv_phb3_properties);
- set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->user_creatable = false;
}
static const TypeInfo pnv_phb3_type_info = {
.name = TYPE_PNV_PHB3,
- .parent = TYPE_PCIE_HOST_BRIDGE,
+ .parent = TYPE_DEVICE,
.instance_size = sizeof(PnvPHB3),
.class_init = pnv_phb3_class_init,
.instance_init = pnv_phb3_instance_init,
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d3f77c8367..1df91971b8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -43,6 +43,7 @@
#include "hw/ipmi/ipmi.h"
#include "target/ppc/mmu-hash64.h"
#include "hw/pci/msi.h"
+#include "hw/pci-host/pnv_phb.h"
#include "hw/ppc/xics.h"
#include "hw/qdev-properties.h"
@@ -660,7 +661,8 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
ics_pic_print_info(&chip8->psi.ics, mon);
for (i = 0; i < chip8->num_phbs; i++) {
- PnvPHB3 *phb3 = &chip8->phbs[i];
+ PnvPHB *phb = &chip8->phbs[i];
+ PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
ics_pic_print_info(&phb3->lsis, mon);
@@ -1149,7 +1151,7 @@ static void pnv_chip_power8_instance_init(Object *obj)
chip8->num_phbs = pcc->num_phbs;
for (i = 0; i < chip8->num_phbs; i++) {
- object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
+ object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB);
}
}
@@ -1287,9 +1289,9 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
&chip8->homer.regs);
- /* PHB3 controllers */
+ /* PHB controllers */
for (i = 0; i < chip8->num_phbs; i++) {
- PnvPHB3 *phb = &chip8->phbs[i];
+ PnvPHB *phb = &chip8->phbs[i];
object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
@@ -1957,7 +1959,8 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
}
for (j = 0; j < chip8->num_phbs; j++) {
- PnvPHB3 *phb3 = &chip8->phbs[j];
+ PnvPHB *phb = &chip8->phbs[j];
+ PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
if (ics_valid_irq(&phb3->lsis, irq)) {
return &phb3->lsis;
@@ -1995,7 +1998,8 @@ static void pnv_ics_resend(XICSFabric *xi)
ics_resend(&chip8->psi.ics);
for (j = 0; j < chip8->num_phbs; j++) {
- PnvPHB3 *phb3 = &chip8->phbs[j];
+ PnvPHB *phb = &chip8->phbs[j];
+ PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
ics_resend(&phb3->lsis);
ics_resend(ICS(&phb3->msis));
@@ -2095,8 +2099,13 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
+ static GlobalProperty phb_compat[] = {
+ { TYPE_PNV_PHB, "version", "3" },
+ };
+
mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
+ compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
xic->icp_get = pnv_icp_get;
xic->ics_get = pnv_ics_get;
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index 1375f18fc1..3b9ff1096a 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -14,6 +14,7 @@
#include "hw/pci/pcie_port.h"
#include "hw/ppc/xics.h"
#include "qom/object.h"
+#include "hw/pci-host/pnv_phb.h"
typedef struct PnvPHB3 PnvPHB3;
typedef struct PnvChip PnvChip;
@@ -127,7 +128,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3)
#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
struct PnvPHB3 {
- PCIExpressHost parent_obj;
+ DeviceState parent;
+
+ PnvPHB *phb_base;
uint32_t chip_id;
uint32_t phb_id;
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index b991194223..33b7b52f45 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -32,6 +32,7 @@
#include "hw/ppc/pnv_core.h"
#include "hw/pci-host/pnv_phb3.h"
#include "hw/pci-host/pnv_phb4.h"
+#include "hw/pci-host/pnv_phb.h"
#include "qom/object.h"
#define TYPE_PNV_CHIP "pnv-chip"
@@ -80,7 +81,7 @@ struct Pnv8Chip {
PnvHomer homer;
#define PNV8_CHIP_PHB3_MAX 4
- PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
+ PnvPHB phbs[PNV8_CHIP_PHB3_MAX];
uint32_t num_phbs;
XICSFabric *xics;
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 03/12] ppc/pnv: turn PnvPHB3 into a PnvPHB backend
2022-06-24 8:49 ` [PATCH v3 03/12] ppc/pnv: turn PnvPHB3 into a PnvPHB backend Daniel Henrique Barboza
@ 2022-07-27 17:31 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:31 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> We need a handful of changes that needs to be done in a single swoop to
> turn PnvPHB3 into a PnvPHB backend.
>
> In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
> will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a
> couple of instances in pnv_phb3.c that needs to access the PCI bus, so a
> phb_base pointer is added to allow access to the parent PnvPHB. The
> PnvPHB3 root port will now be connected to a PnvPHB object.
>
> In pnv.c, the powernv8 machine chip8 will now hold an array of PnvPHB
> objects. pnv_get_phb3_child() needs to be adapted to return the PnvPHB3
> backend from the PnvPHB child. A global property is added in
> pnv_machine_power8_class_init() to ensure that all PnvPHBs are created
> with phb->version = 3.
>
> After all these changes we're still able to boot a powernv8 machine with
> default settings. The real gain will come with user created PnvPHB
> devices, coming up next.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
A very minor indentation issue below, but other than that:
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
> hw/pci-host/pnv_phb3.c | 27 +++++----------------------
> hw/ppc/pnv.c | 21 +++++++++++++++------
> include/hw/pci-host/pnv_phb3.h | 5 ++++-
> include/hw/ppc/pnv.h | 3 ++-
> 4 files changed, 26 insertions(+), 30 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
> index 058cbab555..ad5d67a8e8 100644
> --- a/hw/pci-host/pnv_phb3.c
> +++ b/hw/pci-host/pnv_phb3.c
> @@ -11,6 +11,7 @@
> #include "qapi/visitor.h"
> #include "qapi/error.h"
> #include "hw/pci-host/pnv_phb3_regs.h"
> +#include "hw/pci-host/pnv_phb.h"
> #include "hw/pci-host/pnv_phb3.h"
> #include "hw/pci/pcie_host.h"
> #include "hw/pci/pcie_port.h"
> @@ -26,7 +27,7 @@
>
> static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb)
> {
> - PCIHostState *pci = PCI_HOST_BRIDGE(phb);
> + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
> uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
> uint8_t bus, devfn;
>
> @@ -590,7 +591,7 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size)
> uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size)
> {
> PnvPHB3 *phb = opaque;
> - PCIHostState *pci = PCI_HOST_BRIDGE(phb);
> + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
> uint64_t val;
>
> if ((off & 0xfffc) == PHB_CONFIG_DATA) {
> @@ -1011,7 +1012,6 @@ void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
> static void pnv_phb3_realize(DeviceState *dev, Error **errp)
> {
> PnvPHB3 *phb = PNV_PHB3(dev);
> - PCIHostState *pci = PCI_HOST_BRIDGE(dev);
> PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
> int i;
>
> @@ -1056,11 +1056,6 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
> /* Controller Registers */
> memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
> "phb3-regs", 0x1000);
> -
> - pnv_phb3_bus_init(dev, phb);
> -
> - pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
> - phb->phb_id, phb->chip_id);
> }
>
> void pnv_phb3_update_regions(PnvPHB3 *phb)
> @@ -1085,38 +1080,26 @@ void pnv_phb3_update_regions(PnvPHB3 *phb)
> pnv_phb3_check_all_m64s(phb);
> }
>
> -static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge,
> - PCIBus *rootbus)
> -{
> - PnvPHB3 *phb = PNV_PHB3(host_bridge);
> -
> - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
> - phb->chip_id, phb->phb_id);
> - return phb->bus_path;
> -}
> -
> static Property pnv_phb3_properties[] = {
> DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0),
> DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0),
> DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *),
> + DEFINE_PROP_LINK("phb-base", PnvPHB3, phb_base, TYPE_PNV_PHB, PnvPHB *),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> static void pnv_phb3_class_init(ObjectClass *klass, void *data)
> {
> - PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> - hc->root_bus_path = pnv_phb3_root_bus_path;
> dc->realize = pnv_phb3_realize;
> device_class_set_props(dc, pnv_phb3_properties);
> - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
> dc->user_creatable = false;
> }
>
> static const TypeInfo pnv_phb3_type_info = {
> .name = TYPE_PNV_PHB3,
> - .parent = TYPE_PCIE_HOST_BRIDGE,
> + .parent = TYPE_DEVICE,
Missing spaces here ^^
Fred
> .instance_size = sizeof(PnvPHB3),
> .class_init = pnv_phb3_class_init,
> .instance_init = pnv_phb3_instance_init,
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index d3f77c8367..1df91971b8 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -43,6 +43,7 @@
> #include "hw/ipmi/ipmi.h"
> #include "target/ppc/mmu-hash64.h"
> #include "hw/pci/msi.h"
> +#include "hw/pci-host/pnv_phb.h"
>
> #include "hw/ppc/xics.h"
> #include "hw/qdev-properties.h"
> @@ -660,7 +661,8 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
> ics_pic_print_info(&chip8->psi.ics, mon);
>
> for (i = 0; i < chip8->num_phbs; i++) {
> - PnvPHB3 *phb3 = &chip8->phbs[i];
> + PnvPHB *phb = &chip8->phbs[i];
> + PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
>
> pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
> ics_pic_print_info(&phb3->lsis, mon);
> @@ -1149,7 +1151,7 @@ static void pnv_chip_power8_instance_init(Object *obj)
> chip8->num_phbs = pcc->num_phbs;
>
> for (i = 0; i < chip8->num_phbs; i++) {
> - object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
> + object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB);
> }
>
> }
> @@ -1287,9 +1289,9 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
> &chip8->homer.regs);
>
> - /* PHB3 controllers */
> + /* PHB controllers */
> for (i = 0; i < chip8->num_phbs; i++) {
> - PnvPHB3 *phb = &chip8->phbs[i];
> + PnvPHB *phb = &chip8->phbs[i];
>
> object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
> object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
> @@ -1957,7 +1959,8 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
> }
>
> for (j = 0; j < chip8->num_phbs; j++) {
> - PnvPHB3 *phb3 = &chip8->phbs[j];
> + PnvPHB *phb = &chip8->phbs[j];
> + PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
>
> if (ics_valid_irq(&phb3->lsis, irq)) {
> return &phb3->lsis;
> @@ -1995,7 +1998,8 @@ static void pnv_ics_resend(XICSFabric *xi)
> ics_resend(&chip8->psi.ics);
>
> for (j = 0; j < chip8->num_phbs; j++) {
> - PnvPHB3 *phb3 = &chip8->phbs[j];
> + PnvPHB *phb = &chip8->phbs[j];
> + PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
>
> ics_resend(&phb3->lsis);
> ics_resend(ICS(&phb3->msis));
> @@ -2095,8 +2099,13 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
> PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
> static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
>
> + static GlobalProperty phb_compat[] = {
> + { TYPE_PNV_PHB, "version", "3" },
> + };
> +
> mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
> + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
>
> xic->icp_get = pnv_icp_get;
> xic->ics_get = pnv_ics_get;
> diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
> index 1375f18fc1..3b9ff1096a 100644
> --- a/include/hw/pci-host/pnv_phb3.h
> +++ b/include/hw/pci-host/pnv_phb3.h
> @@ -14,6 +14,7 @@
> #include "hw/pci/pcie_port.h"
> #include "hw/ppc/xics.h"
> #include "qom/object.h"
> +#include "hw/pci-host/pnv_phb.h"
>
> typedef struct PnvPHB3 PnvPHB3;
> typedef struct PnvChip PnvChip;
> @@ -127,7 +128,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3)
> #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
>
> struct PnvPHB3 {
> - PCIExpressHost parent_obj;
> + DeviceState parent;
> +
> + PnvPHB *phb_base;
>
> uint32_t chip_id;
> uint32_t phb_id;
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index b991194223..33b7b52f45 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -32,6 +32,7 @@
> #include "hw/ppc/pnv_core.h"
> #include "hw/pci-host/pnv_phb3.h"
> #include "hw/pci-host/pnv_phb4.h"
> +#include "hw/pci-host/pnv_phb.h"
> #include "qom/object.h"
>
> #define TYPE_PNV_CHIP "pnv-chip"
> @@ -80,7 +81,7 @@ struct Pnv8Chip {
> PnvHomer homer;
>
> #define PNV8_CHIP_PHB3_MAX 4
> - PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
> + PnvPHB phbs[PNV8_CHIP_PHB3_MAX];
> uint32_t num_phbs;
>
> XICSFabric *xics;
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 04/12] ppc/pnv: add PHB4 bus init helper
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (2 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 03/12] ppc/pnv: turn PnvPHB3 into a PnvPHB backend Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:32 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 05/12] ppc/pnv: turn PnvPHB4 into a PnvPHB backend Daniel Henrique Barboza
` (8 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
Similar to what we already did for the PnvPHB3 device, let's add a
helper to init the bus when using a PnvPHB4. This helper will be used by
PnvPHb when PnvPHB4 turns into a backend.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb.c | 2 ++
hw/pci-host/pnv_phb4.c | 39 ++++++++++++++++++++--------------
include/hw/pci-host/pnv_phb4.h | 1 +
3 files changed, 26 insertions(+), 16 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 6fefff7d44..abcbcca445 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -69,6 +69,8 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
if (phb->version == 3) {
pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend));
+ } else {
+ pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
}
pnv_phb_attach_root_port(pci, phb_rootport_typename,
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index d225ab5b0f..a7a4519f30 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1544,30 +1544,16 @@ static void pnv_phb4_instance_init(Object *obj)
object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE);
}
-static void pnv_phb4_realize(DeviceState *dev, Error **errp)
+void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
{
- PnvPHB4 *phb = PNV_PHB4(dev);
- PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
- XiveSource *xsrc = &phb->xsrc;
- int nr_irqs;
char name[32];
- /* Set the "big_phb" flag */
- phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
-
- /* Controller Registers */
- snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id,
- phb->phb_id);
- memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
- name, 0x2000);
-
/*
* PHB4 doesn't support IO space. However, qemu gets very upset if
* we don't have an IO region to anchor IO BARs onto so we just
* initialize one which we never hook up to anything
*/
-
snprintf(name, sizeof(name), "phb4-%d.%d-pci-io", phb->chip_id,
phb->phb_id);
memory_region_init(&phb->pci_io, OBJECT(phb), name, 0x10000);
@@ -1577,12 +1563,33 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
memory_region_init(&phb->pci_mmio, OBJECT(phb), name,
PCI_MMIO_TOTAL_SIZE);
- pci->bus = pci_register_root_bus(dev, dev->id,
+ pci->bus = pci_register_root_bus(dev, dev->id ? dev->id : NULL,
pnv_phb4_set_irq, pnv_phb4_map_irq, phb,
&phb->pci_mmio, &phb->pci_io,
0, 4, TYPE_PNV_PHB4_ROOT_BUS);
pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
+}
+
+static void pnv_phb4_realize(DeviceState *dev, Error **errp)
+{
+ PnvPHB4 *phb = PNV_PHB4(dev);
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
+ PCIHostState *pci = PCI_HOST_BRIDGE(dev);
+ XiveSource *xsrc = &phb->xsrc;
+ int nr_irqs;
+ char name[32];
+
+ /* Set the "big_phb" flag */
+ phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
+
+ /* Controller Registers */
+ snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id,
+ phb->phb_id);
+ memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
+ name, 0x2000);
+
+ pnv_phb4_bus_init(dev, phb);
/* Add a single Root port if running with defaults */
pnv_phb_attach_root_port(pci, pecc->rp_model,
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 19dcbd6f87..90843ac3a9 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -157,6 +157,7 @@ struct PnvPHB4 {
void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon);
int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);
+void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb);
extern const MemoryRegionOps pnv_phb4_xscom_ops;
/*
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 04/12] ppc/pnv: add PHB4 bus init helper
2022-06-24 8:49 ` [PATCH v3 04/12] ppc/pnv: add PHB4 bus init helper Daniel Henrique Barboza
@ 2022-07-27 17:32 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:32 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> Similar to what we already did for the PnvPHB3 device, let's add a
> helper to init the bus when using a PnvPHB4. This helper will be used by
> PnvPHb when PnvPHB4 turns into a backend.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb.c | 2 ++
> hw/pci-host/pnv_phb4.c | 39 ++++++++++++++++++++--------------
> include/hw/pci-host/pnv_phb4.h | 1 +
> 3 files changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> index 6fefff7d44..abcbcca445 100644
> --- a/hw/pci-host/pnv_phb.c
> +++ b/hw/pci-host/pnv_phb.c
> @@ -69,6 +69,8 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
>
> if (phb->version == 3) {
> pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend));
> + } else {
> + pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
> }
>
> pnv_phb_attach_root_port(pci, phb_rootport_typename,
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index d225ab5b0f..a7a4519f30 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -1544,30 +1544,16 @@ static void pnv_phb4_instance_init(Object *obj)
> object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE);
> }
>
> -static void pnv_phb4_realize(DeviceState *dev, Error **errp)
> +void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
> {
> - PnvPHB4 *phb = PNV_PHB4(dev);
> - PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
> PCIHostState *pci = PCI_HOST_BRIDGE(dev);
> - XiveSource *xsrc = &phb->xsrc;
> - int nr_irqs;
> char name[32];
>
> - /* Set the "big_phb" flag */
> - phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
> -
> - /* Controller Registers */
> - snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id,
> - phb->phb_id);
> - memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
> - name, 0x2000);
> -
> /*
> * PHB4 doesn't support IO space. However, qemu gets very upset if
> * we don't have an IO region to anchor IO BARs onto so we just
> * initialize one which we never hook up to anything
> */
> -
> snprintf(name, sizeof(name), "phb4-%d.%d-pci-io", phb->chip_id,
> phb->phb_id);
> memory_region_init(&phb->pci_io, OBJECT(phb), name, 0x10000);
> @@ -1577,12 +1563,33 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
> memory_region_init(&phb->pci_mmio, OBJECT(phb), name,
> PCI_MMIO_TOTAL_SIZE);
>
> - pci->bus = pci_register_root_bus(dev, dev->id,
> + pci->bus = pci_register_root_bus(dev, dev->id ? dev->id : NULL,
> pnv_phb4_set_irq, pnv_phb4_map_irq, phb,
> &phb->pci_mmio, &phb->pci_io,
> 0, 4, TYPE_PNV_PHB4_ROOT_BUS);
> pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
> pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
> +}
> +
> +static void pnv_phb4_realize(DeviceState *dev, Error **errp)
> +{
> + PnvPHB4 *phb = PNV_PHB4(dev);
> + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
> + PCIHostState *pci = PCI_HOST_BRIDGE(dev);
> + XiveSource *xsrc = &phb->xsrc;
> + int nr_irqs;
> + char name[32];
> +
> + /* Set the "big_phb" flag */
> + phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
> +
> + /* Controller Registers */
> + snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id,
> + phb->phb_id);
> + memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
> + name, 0x2000);
> +
> + pnv_phb4_bus_init(dev, phb);
>
> /* Add a single Root port if running with defaults */
> pnv_phb_attach_root_port(pci, pecc->rp_model,
> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
> index 19dcbd6f87..90843ac3a9 100644
> --- a/include/hw/pci-host/pnv_phb4.h
> +++ b/include/hw/pci-host/pnv_phb4.h
> @@ -157,6 +157,7 @@ struct PnvPHB4 {
>
> void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon);
> int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);
> +void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb);
> extern const MemoryRegionOps pnv_phb4_xscom_ops;
>
> /*
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 05/12] ppc/pnv: turn PnvPHB4 into a PnvPHB backend
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (3 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 04/12] ppc/pnv: add PHB4 bus init helper Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:41 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 06/12] ppc/pnv: add pnv-phb-root-port device Daniel Henrique Barboza
` (7 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via the
phb4->phb_base pointer.
pnv_phb4_pec now creates a PnvPHB object.
The powernv9 machine class will create PnvPHB devices with version '4'.
powernv10 will create using version '5'. Both are using global machine
properties in their class_init() to do that.
These changes will benefit us when adding PnvPHB user creatable devices
for powernv9 and powernv10.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb4.c | 30 +++++-------------------------
hw/pci-host/pnv_phb4_pec.c | 3 +--
hw/ppc/pnv.c | 20 +++++++++++++++++++-
include/hw/pci-host/pnv_phb4.h | 5 ++++-
4 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index a7a4519f30..74cf62dc1a 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -49,7 +49,7 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb)
{
- PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+ PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
uint8_t bus, devfn;
@@ -145,7 +145,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off,
static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
unsigned size, uint64_t val)
{
- PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+ PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
PCIDevice *pdev;
if (size != 4) {
@@ -166,7 +166,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off,
unsigned size)
{
- PCIHostState *pci = PCI_HOST_BRIDGE(phb);
+ PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
PCIDevice *pdev;
uint64_t val;
@@ -1574,8 +1574,6 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
static void pnv_phb4_realize(DeviceState *dev, Error **errp)
{
PnvPHB4 *phb = PNV_PHB4(dev);
- PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
- PCIHostState *pci = PCI_HOST_BRIDGE(dev);
XiveSource *xsrc = &phb->xsrc;
int nr_irqs;
char name[32];
@@ -1589,12 +1587,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
name, 0x2000);
- pnv_phb4_bus_init(dev, phb);
-
- /* Add a single Root port if running with defaults */
- pnv_phb_attach_root_port(pci, pecc->rp_model,
- phb->phb_id, phb->chip_id);
-
/* Setup XIVE Source */
if (phb->big_phb) {
nr_irqs = PNV_PHB4_MAX_INTs;
@@ -1614,16 +1606,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
pnv_phb4_xscom_realize(phb);
}
-static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
- PCIBus *rootbus)
-{
- PnvPHB4 *phb = PNV_PHB4(host_bridge);
-
- snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
- phb->chip_id, phb->phb_id);
- return phb->bus_path;
-}
-
/*
* Address base trigger mode (POWER10)
*
@@ -1708,19 +1690,17 @@ static Property pnv_phb4_properties[] = {
DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
PnvPhb4PecState *),
+ DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, TYPE_PNV_PHB, PnvPHB *),
DEFINE_PROP_END_OF_LIST(),
};
static void pnv_phb4_class_init(ObjectClass *klass, void *data)
{
- PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
- hc->root_bus_path = pnv_phb4_root_bus_path;
dc->realize = pnv_phb4_realize;
device_class_set_props(dc, pnv_phb4_properties);
- set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->user_creatable = false;
xfc->notify = pnv_phb4_xive_notify;
@@ -1728,7 +1708,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data)
static const TypeInfo pnv_phb4_type_info = {
.name = TYPE_PNV_PHB4,
- .parent = TYPE_PCIE_HOST_BRIDGE,
+ .parent = TYPE_DEVICE,
.instance_init = pnv_phb4_instance_init,
.instance_size = sizeof(PnvPHB4),
.class_init = pnv_phb4_class_init,
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index c9aaf1c28e..4a0a9fbe8b 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
int stack_no,
Error **errp)
{
- PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
- PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type));
+ PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB));
int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb));
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 1df91971b8..b7273f386e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -672,7 +672,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
{
Monitor *mon = opaque;
- PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
+ PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
+ PnvPHB4 *phb4;
+
+ if (!phb) {
+ return 0;
+ }
+
+ phb4 = (PnvPHB4 *)phb->backend;
if (phb4) {
pnv_phb4_pic_print_info(phb4, mon);
@@ -2122,8 +2129,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
static const char compat[] = "qemu,powernv9\0ibm,powernv";
+ static GlobalProperty phb_compat[] = {
+ { TYPE_PNV_PHB, "version", "4" },
+ };
+
mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
+ compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
+
xfc->match_nvt = pnv_match_nvt;
mc->alias = "powernv";
@@ -2140,8 +2153,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
static const char compat[] = "qemu,powernv10\0ibm,powernv";
+ static GlobalProperty phb_compat[] = {
+ { TYPE_PNV_PHB, "version", "5" },
+ };
+
mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
+ compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 90843ac3a9..f22253358f 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -18,6 +18,7 @@
typedef struct PnvPhb4PecState PnvPhb4PecState;
typedef struct PnvPhb4PecStack PnvPhb4PecStack;
typedef struct PnvPHB4 PnvPHB4;
+typedef struct PnvPHB PnvPHB;
typedef struct PnvChip PnvChip;
/*
@@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
struct PnvPHB4 {
- PCIExpressHost parent_obj;
+ DeviceState parent;
+
+ PnvPHB *phb_base;
uint32_t chip_id;
uint32_t phb_id;
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 05/12] ppc/pnv: turn PnvPHB4 into a PnvPHB backend
2022-06-24 8:49 ` [PATCH v3 05/12] ppc/pnv: turn PnvPHB4 into a PnvPHB backend Daniel Henrique Barboza
@ 2022-07-27 17:41 ` Frederic Barrat
2022-07-28 13:09 ` Daniel Henrique Barboza
0 siblings, 1 reply; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:41 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 1df91971b8..b7273f386e 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -672,7 +672,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
> static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
> {
> Monitor *mon = opaque;
> - PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
> + PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
> + PnvPHB4 *phb4;
> +
> + if (!phb) {
> + return 0;
> + }
> +
> + phb4 = (PnvPHB4 *)phb->backend;
>
> if (phb4) {
> pnv_phb4_pic_print_info(phb4, mon);
The full code in pnv_chip_power9_pic_print_info_child() looks like this:
PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
PnvPHB4 *phb4;
if (!phb) {
return 0;
}
phb4 = (PnvPHB4 *)phb->backend;
if (phb4) {
pnv_phb4_pic_print_info(phb4, mon);
}
Which is correct. However, if I want to nitpick, phb->backend is defined
when the PnvPHB object is realized, so I don't think we can get here
with the pointer being null, so we could remove the second if statement
for readability. The reason I mention it is that we don't take that much
care in the pnv_chip_power8_pic_print_info() function just above, so it
looks a bit odd.
In any case:
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> @@ -2122,8 +2129,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
> PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
> static const char compat[] = "qemu,powernv9\0ibm,powernv";
>
> + static GlobalProperty phb_compat[] = {
> + { TYPE_PNV_PHB, "version", "4" },
> + };
> +
> mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
> + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
> +
> xfc->match_nvt = pnv_match_nvt;
>
> mc->alias = "powernv";
> @@ -2140,8 +2153,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
> XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
> static const char compat[] = "qemu,powernv10\0ibm,powernv";
>
> + static GlobalProperty phb_compat[] = {
> + { TYPE_PNV_PHB, "version", "5" },
> + };
> +
> mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
> + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
>
> pmc->compat = compat;
> pmc->compat_size = sizeof(compat);
> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
> index 90843ac3a9..f22253358f 100644
> --- a/include/hw/pci-host/pnv_phb4.h
> +++ b/include/hw/pci-host/pnv_phb4.h
> @@ -18,6 +18,7 @@
> typedef struct PnvPhb4PecState PnvPhb4PecState;
> typedef struct PnvPhb4PecStack PnvPhb4PecStack;
> typedef struct PnvPHB4 PnvPHB4;
> +typedef struct PnvPHB PnvPHB;
> typedef struct PnvChip PnvChip;
>
> /*
> @@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
> #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
>
> struct PnvPHB4 {
> - PCIExpressHost parent_obj;
> + DeviceState parent;
> +
> + PnvPHB *phb_base;
>
> uint32_t chip_id;
> uint32_t phb_id;
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v3 05/12] ppc/pnv: turn PnvPHB4 into a PnvPHB backend
2022-07-27 17:41 ` Frederic Barrat
@ 2022-07-28 13:09 ` Daniel Henrique Barboza
0 siblings, 0 replies; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-07-28 13:09 UTC (permalink / raw)
To: Frederic Barrat, qemu-devel; +Cc: qemu-ppc, clg
On 7/27/22 14:41, Frederic Barrat wrote:
>
>
> On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
>
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 1df91971b8..b7273f386e 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -672,7 +672,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
>> static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
>> {
>> Monitor *mon = opaque;
>> - PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
>> + PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
>> + PnvPHB4 *phb4;
>> +
>> + if (!phb) {
>> + return 0;
>> + }
>> +
>> + phb4 = (PnvPHB4 *)phb->backend;
>> if (phb4) {
>> pnv_phb4_pic_print_info(phb4, mon);
>
>
> The full code in pnv_chip_power9_pic_print_info_child() looks like this:
>
> PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
> PnvPHB4 *phb4;
>
> if (!phb) {
> return 0;
> }
>
> phb4 = (PnvPHB4 *)phb->backend;
>
> if (phb4) {
> pnv_phb4_pic_print_info(phb4, mon);
> }
>
> Which is correct. However, if I want to nitpick, phb->backend is defined when the PnvPHB object is realized, so I don't think we can get here with the pointer being null, so we could remove the second if statement for readability. The reason I mention it is that we don't take that much care in the pnv_chip_power8_pic_print_info() function just above, so it looks a bit odd.
Good point. I changed it to look like this:
static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
{
Monitor *mon = opaque;
PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
if (!phb) {
return 0;
}
pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
return 0;
}
phb->backend being either NULL or not a PHB4 object is serious enough to assert
out, so the PNV_PHB4() macro seems justified.
Thanks,
Daniel
>
> In any case:
> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
>
> Fred
>
>
>
>
>> @@ -2122,8 +2129,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
>> PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
>> static const char compat[] = "qemu,powernv9\0ibm,powernv";
>> + static GlobalProperty phb_compat[] = {
>> + { TYPE_PNV_PHB, "version", "4" },
>> + };
>> +
>> mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
>> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
>> + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
>> +
>> xfc->match_nvt = pnv_match_nvt;
>> mc->alias = "powernv";
>> @@ -2140,8 +2153,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
>> XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
>> static const char compat[] = "qemu,powernv10\0ibm,powernv";
>> + static GlobalProperty phb_compat[] = {
>> + { TYPE_PNV_PHB, "version", "5" },
>> + };
>> +
>> mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
>> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
>> + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
>> pmc->compat = compat;
>> pmc->compat_size = sizeof(compat);
>> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
>> index 90843ac3a9..f22253358f 100644
>> --- a/include/hw/pci-host/pnv_phb4.h
>> +++ b/include/hw/pci-host/pnv_phb4.h
>> @@ -18,6 +18,7 @@
>> typedef struct PnvPhb4PecState PnvPhb4PecState;
>> typedef struct PnvPhb4PecStack PnvPhb4PecStack;
>> typedef struct PnvPHB4 PnvPHB4;
>> +typedef struct PnvPHB PnvPHB;
>> typedef struct PnvChip PnvChip;
>> /*
>> @@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
>> #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
>> struct PnvPHB4 {
>> - PCIExpressHost parent_obj;
>> + DeviceState parent;
>> +
>> + PnvPHB *phb_base;
>> uint32_t chip_id;
>> uint32_t phb_id;
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 06/12] ppc/pnv: add pnv-phb-root-port device
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (4 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 05/12] ppc/pnv: turn PnvPHB4 into a PnvPHB backend Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:42 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 07/12] ppc/pnv: remove pnv-phb3-root-port Daniel Henrique Barboza
` (6 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports is that
pnv-phb4-root-port has the pnv_phb4_root_port_reset() callback. All
other differences can be merged in a single device without too much
trouble.
This patch introduces the unified pnv-phb-root-port that, in time, will
be used as the default root port for the pnv-phb device.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb.c | 115 +++++++++++++++++++++++++++++++++++++++---
hw/pci-host/pnv_phb.h | 16 ++++++
2 files changed, 123 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index abcbcca445..5e61f85614 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -112,15 +112,114 @@ static void pnv_phb_class_init(ObjectClass *klass, void *data)
dc->user_creatable = false;
}
-static void pnv_phb_register_type(void)
+static void pnv_phb_root_port_reset(DeviceState *dev)
{
- static const TypeInfo pnv_phb_type_info = {
- .name = TYPE_PNV_PHB,
- .parent = TYPE_PCIE_HOST_BRIDGE,
- .instance_size = sizeof(PnvPHB),
- .class_init = pnv_phb_class_init,
- };
+ PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
+ PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
+ PCIDevice *d = PCI_DEVICE(dev);
+ uint8_t *conf = d->config;
+ rpc->parent_reset(dev);
+
+ if (phb_rp->version == 3) {
+ return;
+ }
+
+ /* PHB4 and later requires these extra reset steps */
+ pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
+ PCI_IO_RANGE_MASK & 0xff);
+ pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
+ PCI_IO_RANGE_MASK & 0xff);
+ pci_set_word(conf + PCI_MEMORY_BASE, 0);
+ pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
+ pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
+ pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
+ pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
+ pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
+ pci_config_set_interrupt_pin(conf, 0);
+}
+
+static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp)
+{
+ PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
+ PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
+ PCIDevice *pci = PCI_DEVICE(dev);
+ uint16_t device_id = 0;
+ Error *local_err = NULL;
+
+ rpc->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ switch (phb_rp->version) {
+ case 3:
+ device_id = PNV_PHB3_DEVICE_ID;
+ break;
+ case 4:
+ device_id = PNV_PHB4_DEVICE_ID;
+ break;
+ case 5:
+ device_id = PNV_PHB5_DEVICE_ID;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ pci_config_set_device_id(pci->config, device_id);
+ pci_config_set_interrupt_pin(pci->config, 0);
+}
+
+static Property pnv_phb_root_port_properties[] = {
+ DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
+
+ dc->desc = "IBM PHB PCIE Root Port";
+
+ device_class_set_props(dc, pnv_phb_root_port_properties);
+ device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
+ &rpc->parent_realize);
+ device_class_set_parent_reset(dc, pnv_phb_root_port_reset,
+ &rpc->parent_reset);
+ dc->reset = &pnv_phb_root_port_reset;
+ dc->user_creatable = false;
+
+ k->vendor_id = PCI_VENDOR_ID_IBM;
+ /* device_id will be written during realize() */
+ k->device_id = 0;
+ k->revision = 0;
+
+ rpc->exp_offset = 0x48;
+ rpc->aer_offset = 0x100;
+}
+
+static const TypeInfo pnv_phb_type_info = {
+ .name = TYPE_PNV_PHB,
+ .parent = TYPE_PCIE_HOST_BRIDGE,
+ .instance_size = sizeof(PnvPHB),
+ .class_init = pnv_phb_class_init,
+};
+
+static const TypeInfo pnv_phb_root_port_info = {
+ .name = TYPE_PNV_PHB_ROOT_PORT,
+ .parent = TYPE_PCIE_ROOT_PORT,
+ .instance_size = sizeof(PnvPHBRootPort),
+ .class_init = pnv_phb_root_port_class_init,
+};
+
+static void pnv_phb_register_types(void)
+{
type_register_static(&pnv_phb_type_info);
+ type_register_static(&pnv_phb_root_port_info);
}
-type_init(pnv_phb_register_type)
+
+type_init(pnv_phb_register_types)
diff --git a/hw/pci-host/pnv_phb.h b/hw/pci-host/pnv_phb.h
index a7cc8610e2..58ebd6dd0f 100644
--- a/hw/pci-host/pnv_phb.h
+++ b/hw/pci-host/pnv_phb.h
@@ -36,4 +36,20 @@ struct PnvPHB {
#define TYPE_PNV_PHB "pnv-phb"
OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB, PNV_PHB)
+/*
+ * PHB PCIe Root port
+ */
+#define PNV_PHB3_DEVICE_ID 0x03dc
+#define PNV_PHB4_DEVICE_ID 0x04c1
+#define PNV_PHB5_DEVICE_ID 0x0652
+
+typedef struct PnvPHBRootPort {
+ PCIESlot parent_obj;
+
+ uint32_t version;
+} PnvPHBRootPort;
+
+#define TYPE_PNV_PHB_ROOT_PORT "pnv-phb-root-port"
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPHBRootPort, PNV_PHB_ROOT_PORT)
+
#endif /* PCI_HOST_PNV_PHB_H */
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 06/12] ppc/pnv: add pnv-phb-root-port device
2022-06-24 8:49 ` [PATCH v3 06/12] ppc/pnv: add pnv-phb-root-port device Daniel Henrique Barboza
@ 2022-07-27 17:42 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:42 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> We have two very similar root-port devices, pnv-phb3-root-port and
> pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
> that, until now, has no additional attributes.
>
> The main difference between the PHB3 and PHB4 root ports is that
> pnv-phb4-root-port has the pnv_phb4_root_port_reset() callback. All
> other differences can be merged in a single device without too much
> trouble.
>
> This patch introduces the unified pnv-phb-root-port that, in time, will
> be used as the default root port for the pnv-phb device.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb.c | 115 +++++++++++++++++++++++++++++++++++++++---
> hw/pci-host/pnv_phb.h | 16 ++++++
> 2 files changed, 123 insertions(+), 8 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> index abcbcca445..5e61f85614 100644
> --- a/hw/pci-host/pnv_phb.c
> +++ b/hw/pci-host/pnv_phb.c
> @@ -112,15 +112,114 @@ static void pnv_phb_class_init(ObjectClass *klass, void *data)
> dc->user_creatable = false;
> }
>
> -static void pnv_phb_register_type(void)
> +static void pnv_phb_root_port_reset(DeviceState *dev)
> {
> - static const TypeInfo pnv_phb_type_info = {
> - .name = TYPE_PNV_PHB,
> - .parent = TYPE_PCIE_HOST_BRIDGE,
> - .instance_size = sizeof(PnvPHB),
> - .class_init = pnv_phb_class_init,
> - };
> + PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> + PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
> + PCIDevice *d = PCI_DEVICE(dev);
> + uint8_t *conf = d->config;
>
> + rpc->parent_reset(dev);
> +
> + if (phb_rp->version == 3) {
> + return;
> + }
> +
> + /* PHB4 and later requires these extra reset steps */
> + pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
> + PCI_IO_RANGE_MASK & 0xff);
> + pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
> + PCI_IO_RANGE_MASK & 0xff);
> + pci_set_word(conf + PCI_MEMORY_BASE, 0);
> + pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
> + pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
> + pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
> + pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
> + pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
> + pci_config_set_interrupt_pin(conf, 0);
> +}
> +
> +static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp)
> +{
> + PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> + PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
> + PCIDevice *pci = PCI_DEVICE(dev);
> + uint16_t device_id = 0;
> + Error *local_err = NULL;
> +
> + rpc->parent_realize(dev, &local_err);
> + if (local_err) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> + switch (phb_rp->version) {
> + case 3:
> + device_id = PNV_PHB3_DEVICE_ID;
> + break;
> + case 4:
> + device_id = PNV_PHB4_DEVICE_ID;
> + break;
> + case 5:
> + device_id = PNV_PHB5_DEVICE_ID;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + pci_config_set_device_id(pci->config, device_id);
> + pci_config_set_interrupt_pin(pci->config, 0);
> +}
> +
> +static Property pnv_phb_root_port_properties[] = {
> + DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
> +
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> + PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
> +
> + dc->desc = "IBM PHB PCIE Root Port";
> +
> + device_class_set_props(dc, pnv_phb_root_port_properties);
> + device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
> + &rpc->parent_realize);
> + device_class_set_parent_reset(dc, pnv_phb_root_port_reset,
> + &rpc->parent_reset);
> + dc->reset = &pnv_phb_root_port_reset;
> + dc->user_creatable = false;
> +
> + k->vendor_id = PCI_VENDOR_ID_IBM;
> + /* device_id will be written during realize() */
> + k->device_id = 0;
> + k->revision = 0;
> +
> + rpc->exp_offset = 0x48;
> + rpc->aer_offset = 0x100;
> +}
> +
> +static const TypeInfo pnv_phb_type_info = {
> + .name = TYPE_PNV_PHB,
> + .parent = TYPE_PCIE_HOST_BRIDGE,
> + .instance_size = sizeof(PnvPHB),
> + .class_init = pnv_phb_class_init,
> +};
> +
> +static const TypeInfo pnv_phb_root_port_info = {
> + .name = TYPE_PNV_PHB_ROOT_PORT,
> + .parent = TYPE_PCIE_ROOT_PORT,
> + .instance_size = sizeof(PnvPHBRootPort),
> + .class_init = pnv_phb_root_port_class_init,
> +};
> +
> +static void pnv_phb_register_types(void)
> +{
> type_register_static(&pnv_phb_type_info);
> + type_register_static(&pnv_phb_root_port_info);
> }
> -type_init(pnv_phb_register_type)
> +
> +type_init(pnv_phb_register_types)
> diff --git a/hw/pci-host/pnv_phb.h b/hw/pci-host/pnv_phb.h
> index a7cc8610e2..58ebd6dd0f 100644
> --- a/hw/pci-host/pnv_phb.h
> +++ b/hw/pci-host/pnv_phb.h
> @@ -36,4 +36,20 @@ struct PnvPHB {
> #define TYPE_PNV_PHB "pnv-phb"
> OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB, PNV_PHB)
>
> +/*
> + * PHB PCIe Root port
> + */
> +#define PNV_PHB3_DEVICE_ID 0x03dc
> +#define PNV_PHB4_DEVICE_ID 0x04c1
> +#define PNV_PHB5_DEVICE_ID 0x0652
> +
> +typedef struct PnvPHBRootPort {
> + PCIESlot parent_obj;
> +
> + uint32_t version;
> +} PnvPHBRootPort;
> +
> +#define TYPE_PNV_PHB_ROOT_PORT "pnv-phb-root-port"
> +OBJECT_DECLARE_SIMPLE_TYPE(PnvPHBRootPort, PNV_PHB_ROOT_PORT)
> +
> #endif /* PCI_HOST_PNV_PHB_H */
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 07/12] ppc/pnv: remove pnv-phb3-root-port
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (5 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 06/12] ppc/pnv: add pnv-phb-root-port device Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:43 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 08/12] ppc/pnv: remove pnv-phb4-root-port Daniel Henrique Barboza
` (5 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
The unified pnv-phb-root-port can be used in its place. There is no ABI
breakage in doing so because no official QEMU release introduced user
creatable pnv-phb3-root-port devices.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb.c | 2 +-
hw/pci-host/pnv_phb3.c | 42 ----------------------------------
hw/ppc/pnv.c | 1 +
include/hw/pci-host/pnv_phb3.h | 6 -----
4 files changed, 2 insertions(+), 49 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 5e61f85614..cdddc6a389 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -34,7 +34,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
switch (phb->version) {
case 3:
phb_typename = g_strdup(TYPE_PNV_PHB3);
- phb_rootport_typename = g_strdup(TYPE_PNV_PHB3_ROOT_PORT);
+ phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
case 4:
phb_typename = g_strdup(TYPE_PNV_PHB4);
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index ad5d67a8e8..2966374008 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1122,51 +1122,9 @@ static const TypeInfo pnv_phb3_root_bus_info = {
.class_init = pnv_phb3_root_bus_class_init,
};
-static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
-{
- PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
- PCIDevice *pci = PCI_DEVICE(dev);
- Error *local_err = NULL;
-
- rpc->parent_realize(dev, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
- pci_config_set_interrupt_pin(pci->config, 0);
-}
-
-static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
-
- dc->desc = "IBM PHB3 PCIE Root Port";
-
- device_class_set_parent_realize(dc, pnv_phb3_root_port_realize,
- &rpc->parent_realize);
- dc->user_creatable = false;
-
- k->vendor_id = PCI_VENDOR_ID_IBM;
- k->device_id = 0x03dc;
- k->revision = 0;
-
- rpc->exp_offset = 0x48;
- rpc->aer_offset = 0x100;
-}
-
-static const TypeInfo pnv_phb3_root_port_info = {
- .name = TYPE_PNV_PHB3_ROOT_PORT,
- .parent = TYPE_PCIE_ROOT_PORT,
- .instance_size = sizeof(PnvPHB3RootPort),
- .class_init = pnv_phb3_root_port_class_init,
-};
-
static void pnv_phb3_register_types(void)
{
type_register_static(&pnv_phb3_root_bus_info);
- type_register_static(&pnv_phb3_root_port_info);
type_register_static(&pnv_phb3_type_info);
type_register_static(&pnv_phb3_iommu_memory_region_info);
}
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index b7273f386e..d82c66ca6f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2108,6 +2108,7 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
static GlobalProperty phb_compat[] = {
{ TYPE_PNV_PHB, "version", "3" },
+ { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
};
mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index 3b9ff1096a..bff69201d9 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -108,12 +108,6 @@ struct PnvPBCQState {
*/
#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root"
-#define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port"
-
-typedef struct PnvPHB3RootPort {
- PCIESlot parent_obj;
-} PnvPHB3RootPort;
-
/*
* PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
*/
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 07/12] ppc/pnv: remove pnv-phb3-root-port
2022-06-24 8:49 ` [PATCH v3 07/12] ppc/pnv: remove pnv-phb3-root-port Daniel Henrique Barboza
@ 2022-07-27 17:43 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:43 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> The unified pnv-phb-root-port can be used in its place. There is no ABI
> breakage in doing so because no official QEMU release introduced user
> creatable pnv-phb3-root-port devices.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb.c | 2 +-
> hw/pci-host/pnv_phb3.c | 42 ----------------------------------
> hw/ppc/pnv.c | 1 +
> include/hw/pci-host/pnv_phb3.h | 6 -----
> 4 files changed, 2 insertions(+), 49 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> index 5e61f85614..cdddc6a389 100644
> --- a/hw/pci-host/pnv_phb.c
> +++ b/hw/pci-host/pnv_phb.c
> @@ -34,7 +34,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
> switch (phb->version) {
> case 3:
> phb_typename = g_strdup(TYPE_PNV_PHB3);
> - phb_rootport_typename = g_strdup(TYPE_PNV_PHB3_ROOT_PORT);
> + phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
> break;
> case 4:
> phb_typename = g_strdup(TYPE_PNV_PHB4);
> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
> index ad5d67a8e8..2966374008 100644
> --- a/hw/pci-host/pnv_phb3.c
> +++ b/hw/pci-host/pnv_phb3.c
> @@ -1122,51 +1122,9 @@ static const TypeInfo pnv_phb3_root_bus_info = {
> .class_init = pnv_phb3_root_bus_class_init,
> };
>
> -static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
> -{
> - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> - PCIDevice *pci = PCI_DEVICE(dev);
> - Error *local_err = NULL;
> -
> - rpc->parent_realize(dev, &local_err);
> - if (local_err) {
> - error_propagate(errp, local_err);
> - return;
> - }
> - pci_config_set_interrupt_pin(pci->config, 0);
> -}
> -
> -static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(klass);
> - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> - PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
> -
> - dc->desc = "IBM PHB3 PCIE Root Port";
> -
> - device_class_set_parent_realize(dc, pnv_phb3_root_port_realize,
> - &rpc->parent_realize);
> - dc->user_creatable = false;
> -
> - k->vendor_id = PCI_VENDOR_ID_IBM;
> - k->device_id = 0x03dc;
> - k->revision = 0;
> -
> - rpc->exp_offset = 0x48;
> - rpc->aer_offset = 0x100;
> -}
> -
> -static const TypeInfo pnv_phb3_root_port_info = {
> - .name = TYPE_PNV_PHB3_ROOT_PORT,
> - .parent = TYPE_PCIE_ROOT_PORT,
> - .instance_size = sizeof(PnvPHB3RootPort),
> - .class_init = pnv_phb3_root_port_class_init,
> -};
> -
> static void pnv_phb3_register_types(void)
> {
> type_register_static(&pnv_phb3_root_bus_info);
> - type_register_static(&pnv_phb3_root_port_info);
> type_register_static(&pnv_phb3_type_info);
> type_register_static(&pnv_phb3_iommu_memory_region_info);
> }
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index b7273f386e..d82c66ca6f 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -2108,6 +2108,7 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
>
> static GlobalProperty phb_compat[] = {
> { TYPE_PNV_PHB, "version", "3" },
> + { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
> };
>
> mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
> diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
> index 3b9ff1096a..bff69201d9 100644
> --- a/include/hw/pci-host/pnv_phb3.h
> +++ b/include/hw/pci-host/pnv_phb3.h
> @@ -108,12 +108,6 @@ struct PnvPBCQState {
> */
> #define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root"
>
> -#define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port"
> -
> -typedef struct PnvPHB3RootPort {
> - PCIESlot parent_obj;
> -} PnvPHB3RootPort;
> -
> /*
> * PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
> */
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 08/12] ppc/pnv: remove pnv-phb4-root-port
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (6 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 07/12] ppc/pnv: remove pnv-phb3-root-port Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:43 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 09/12] ppc/pnv: remove root port name from pnv_phb_attach_root_port() Daniel Henrique Barboza
` (4 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
The unified pnv-phb-root-port can be used instead. The phb4-root-port
device isn't exposed to the user in any official QEMU release so there's
no ABI breakage in removing it.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb.c | 4 +-
hw/pci-host/pnv_phb4.c | 85 ----------------------------------
hw/pci-host/pnv_phb4_pec.c | 4 +-
hw/ppc/pnv.c | 2 +
include/hw/pci-host/pnv_phb4.h | 9 ----
5 files changed, 6 insertions(+), 98 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index cdddc6a389..da729e89e7 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -38,11 +38,11 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
break;
case 4:
phb_typename = g_strdup(TYPE_PNV_PHB4);
- phb_rootport_typename = g_strdup(TYPE_PNV_PHB4_ROOT_PORT);
+ phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
case 5:
phb_typename = g_strdup(TYPE_PNV_PHB5);
- phb_rootport_typename = g_strdup(TYPE_PNV_PHB5_ROOT_PORT);
+ phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
default:
g_assert_not_reached();
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 74cf62dc1a..fefdd3ad89 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1741,94 +1741,9 @@ static const TypeInfo pnv_phb4_root_bus_info = {
.class_init = pnv_phb4_root_bus_class_init,
};
-static void pnv_phb4_root_port_reset(DeviceState *dev)
-{
- PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
- PCIDevice *d = PCI_DEVICE(dev);
- uint8_t *conf = d->config;
-
- rpc->parent_reset(dev);
-
- pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
- PCI_IO_RANGE_MASK & 0xff);
- pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
- PCI_IO_RANGE_MASK & 0xff);
- pci_set_word(conf + PCI_MEMORY_BASE, 0);
- pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
- pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
- pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
- pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
- pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
- pci_config_set_interrupt_pin(conf, 0);
-}
-
-static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
-{
- PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
- Error *local_err = NULL;
-
- rpc->parent_realize(dev, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
-}
-
-static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
-
- dc->desc = "IBM PHB4 PCIE Root Port";
- dc->user_creatable = false;
-
- device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
- &rpc->parent_realize);
- device_class_set_parent_reset(dc, pnv_phb4_root_port_reset,
- &rpc->parent_reset);
-
- k->vendor_id = PCI_VENDOR_ID_IBM;
- k->device_id = PNV_PHB4_DEVICE_ID;
- k->revision = 0;
-
- rpc->exp_offset = 0x48;
- rpc->aer_offset = 0x100;
-
- dc->reset = &pnv_phb4_root_port_reset;
-}
-
-static const TypeInfo pnv_phb4_root_port_info = {
- .name = TYPE_PNV_PHB4_ROOT_PORT,
- .parent = TYPE_PCIE_ROOT_PORT,
- .instance_size = sizeof(PnvPHB4RootPort),
- .class_init = pnv_phb4_root_port_class_init,
-};
-
-static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- dc->desc = "IBM PHB5 PCIE Root Port";
- dc->user_creatable = false;
-
- k->vendor_id = PCI_VENDOR_ID_IBM;
- k->device_id = PNV_PHB5_DEVICE_ID;
-}
-
-static const TypeInfo pnv_phb5_root_port_info = {
- .name = TYPE_PNV_PHB5_ROOT_PORT,
- .parent = TYPE_PNV_PHB4_ROOT_PORT,
- .instance_size = sizeof(PnvPHB4RootPort),
- .class_init = pnv_phb5_root_port_class_init,
-};
-
static void pnv_phb4_register_types(void)
{
type_register_static(&pnv_phb4_root_bus_info);
- type_register_static(&pnv_phb5_root_port_info);
- type_register_static(&pnv_phb4_root_port_info);
type_register_static(&pnv_phb4_type_info);
type_register_static(&pnv_phb5_type_info);
type_register_static(&pnv_phb4_iommu_memory_region_info);
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 4a0a9fbe8b..0ef66b9a9b 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -260,7 +260,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
pecc->version = PNV_PHB4_VERSION;
pecc->phb_type = TYPE_PNV_PHB4;
pecc->num_phbs = pnv_pec_num_phbs;
- pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT;
+ pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
}
static const TypeInfo pnv_pec_type_info = {
@@ -313,7 +313,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
pecc->version = PNV_PHB5_VERSION;
pecc->phb_type = TYPE_PNV_PHB5;
pecc->num_phbs = pnv_phb5_pec_num_stacks;
- pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT;
+ pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
}
static const TypeInfo pnv_phb5_pec_type_info = {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d82c66ca6f..159899103e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2132,6 +2132,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
static GlobalProperty phb_compat[] = {
{ TYPE_PNV_PHB, "version", "4" },
+ { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
};
mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
@@ -2156,6 +2157,7 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
static GlobalProperty phb_compat[] = {
{ TYPE_PNV_PHB, "version", "5" },
+ { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
};
mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index f22253358f..29c49ac79c 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -45,16 +45,7 @@ typedef struct PnvPhb4DMASpace {
QLIST_ENTRY(PnvPhb4DMASpace) list;
} PnvPhb4DMASpace;
-/*
- * PHB4 PCIe Root port
- */
#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
-#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
-#define TYPE_PNV_PHB5_ROOT_PORT "pnv-phb5-root-port"
-
-typedef struct PnvPHB4RootPort {
- PCIESlot parent_obj;
-} PnvPHB4RootPort;
/*
* PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 08/12] ppc/pnv: remove pnv-phb4-root-port
2022-06-24 8:49 ` [PATCH v3 08/12] ppc/pnv: remove pnv-phb4-root-port Daniel Henrique Barboza
@ 2022-07-27 17:43 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:43 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> The unified pnv-phb-root-port can be used instead. The phb4-root-port
> device isn't exposed to the user in any official QEMU release so there's
> no ABI breakage in removing it.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb.c | 4 +-
> hw/pci-host/pnv_phb4.c | 85 ----------------------------------
> hw/pci-host/pnv_phb4_pec.c | 4 +-
> hw/ppc/pnv.c | 2 +
> include/hw/pci-host/pnv_phb4.h | 9 ----
> 5 files changed, 6 insertions(+), 98 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> index cdddc6a389..da729e89e7 100644
> --- a/hw/pci-host/pnv_phb.c
> +++ b/hw/pci-host/pnv_phb.c
> @@ -38,11 +38,11 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
> break;
> case 4:
> phb_typename = g_strdup(TYPE_PNV_PHB4);
> - phb_rootport_typename = g_strdup(TYPE_PNV_PHB4_ROOT_PORT);
> + phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
> break;
> case 5:
> phb_typename = g_strdup(TYPE_PNV_PHB5);
> - phb_rootport_typename = g_strdup(TYPE_PNV_PHB5_ROOT_PORT);
> + phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
> break;
> default:
> g_assert_not_reached();
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index 74cf62dc1a..fefdd3ad89 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -1741,94 +1741,9 @@ static const TypeInfo pnv_phb4_root_bus_info = {
> .class_init = pnv_phb4_root_bus_class_init,
> };
>
> -static void pnv_phb4_root_port_reset(DeviceState *dev)
> -{
> - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> - PCIDevice *d = PCI_DEVICE(dev);
> - uint8_t *conf = d->config;
> -
> - rpc->parent_reset(dev);
> -
> - pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
> - PCI_IO_RANGE_MASK & 0xff);
> - pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
> - PCI_IO_RANGE_MASK & 0xff);
> - pci_set_word(conf + PCI_MEMORY_BASE, 0);
> - pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
> - pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
> - pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
> - pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
> - pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
> - pci_config_set_interrupt_pin(conf, 0);
> -}
> -
> -static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
> -{
> - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> - Error *local_err = NULL;
> -
> - rpc->parent_realize(dev, &local_err);
> - if (local_err) {
> - error_propagate(errp, local_err);
> - return;
> - }
> -}
> -
> -static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(klass);
> - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> - PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
> -
> - dc->desc = "IBM PHB4 PCIE Root Port";
> - dc->user_creatable = false;
> -
> - device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
> - &rpc->parent_realize);
> - device_class_set_parent_reset(dc, pnv_phb4_root_port_reset,
> - &rpc->parent_reset);
> -
> - k->vendor_id = PCI_VENDOR_ID_IBM;
> - k->device_id = PNV_PHB4_DEVICE_ID;
> - k->revision = 0;
> -
> - rpc->exp_offset = 0x48;
> - rpc->aer_offset = 0x100;
> -
> - dc->reset = &pnv_phb4_root_port_reset;
> -}
> -
> -static const TypeInfo pnv_phb4_root_port_info = {
> - .name = TYPE_PNV_PHB4_ROOT_PORT,
> - .parent = TYPE_PCIE_ROOT_PORT,
> - .instance_size = sizeof(PnvPHB4RootPort),
> - .class_init = pnv_phb4_root_port_class_init,
> -};
> -
> -static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(klass);
> - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> - dc->desc = "IBM PHB5 PCIE Root Port";
> - dc->user_creatable = false;
> -
> - k->vendor_id = PCI_VENDOR_ID_IBM;
> - k->device_id = PNV_PHB5_DEVICE_ID;
> -}
> -
> -static const TypeInfo pnv_phb5_root_port_info = {
> - .name = TYPE_PNV_PHB5_ROOT_PORT,
> - .parent = TYPE_PNV_PHB4_ROOT_PORT,
> - .instance_size = sizeof(PnvPHB4RootPort),
> - .class_init = pnv_phb5_root_port_class_init,
> -};
> -
> static void pnv_phb4_register_types(void)
> {
> type_register_static(&pnv_phb4_root_bus_info);
> - type_register_static(&pnv_phb5_root_port_info);
> - type_register_static(&pnv_phb4_root_port_info);
> type_register_static(&pnv_phb4_type_info);
> type_register_static(&pnv_phb5_type_info);
> type_register_static(&pnv_phb4_iommu_memory_region_info);
> diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
> index 4a0a9fbe8b..0ef66b9a9b 100644
> --- a/hw/pci-host/pnv_phb4_pec.c
> +++ b/hw/pci-host/pnv_phb4_pec.c
> @@ -260,7 +260,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
> pecc->version = PNV_PHB4_VERSION;
> pecc->phb_type = TYPE_PNV_PHB4;
> pecc->num_phbs = pnv_pec_num_phbs;
> - pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT;
> + pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
> }
>
> static const TypeInfo pnv_pec_type_info = {
> @@ -313,7 +313,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
> pecc->version = PNV_PHB5_VERSION;
> pecc->phb_type = TYPE_PNV_PHB5;
> pecc->num_phbs = pnv_phb5_pec_num_stacks;
> - pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT;
> + pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
> }
>
> static const TypeInfo pnv_phb5_pec_type_info = {
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index d82c66ca6f..159899103e 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -2132,6 +2132,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
>
> static GlobalProperty phb_compat[] = {
> { TYPE_PNV_PHB, "version", "4" },
> + { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
> };
>
> mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
> @@ -2156,6 +2157,7 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
>
> static GlobalProperty phb_compat[] = {
> { TYPE_PNV_PHB, "version", "5" },
> + { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
> };
>
> mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
> index f22253358f..29c49ac79c 100644
> --- a/include/hw/pci-host/pnv_phb4.h
> +++ b/include/hw/pci-host/pnv_phb4.h
> @@ -45,16 +45,7 @@ typedef struct PnvPhb4DMASpace {
> QLIST_ENTRY(PnvPhb4DMASpace) list;
> } PnvPhb4DMASpace;
>
> -/*
> - * PHB4 PCIe Root port
> - */
> #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
> -#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
> -#define TYPE_PNV_PHB5_ROOT_PORT "pnv-phb5-root-port"
> -
> -typedef struct PnvPHB4RootPort {
> - PCIESlot parent_obj;
> -} PnvPHB4RootPort;
>
> /*
> * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 09/12] ppc/pnv: remove root port name from pnv_phb_attach_root_port()
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (7 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 08/12] ppc/pnv: remove pnv-phb4-root-port Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:43 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 10/12] ppc/pnv: remove pecc->rp_model Daniel Henrique Barboza
` (3 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
We support only a single root port, PNV_PHB_ROOT_PORT.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb.c | 7 +------
hw/ppc/pnv.c | 9 +++++----
include/hw/ppc/pnv.h | 3 +--
3 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index da729e89e7..cc15a949c9 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -24,7 +24,6 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
PnvPHB *phb = PNV_PHB(dev);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
g_autofree char *phb_typename = NULL;
- g_autofree char *phb_rootport_typename = NULL;
if (!phb->version) {
error_setg(errp, "version not specified");
@@ -34,15 +33,12 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
switch (phb->version) {
case 3:
phb_typename = g_strdup(TYPE_PNV_PHB3);
- phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
case 4:
phb_typename = g_strdup(TYPE_PNV_PHB4);
- phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
case 5:
phb_typename = g_strdup(TYPE_PNV_PHB5);
- phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
break;
default:
g_assert_not_reached();
@@ -73,8 +69,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
}
- pnv_phb_attach_root_port(pci, phb_rootport_typename,
- phb->phb_id, phb->chip_id);
+ pnv_phb_attach_root_port(pci, phb->phb_id, phb->chip_id);
}
static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 159899103e..5b7cbfc699 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1199,11 +1199,12 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
* QOM id. 'chip_id' is going to be used as PCIE chassis for the
* root port.
*/
-void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
- int index, int chip_id)
+void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
{
- PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
- g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index);
+ PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
+ g_autofree char *default_id = g_strdup_printf("%s[%d]",
+ TYPE_PNV_PHB_ROOT_PORT,
+ index);
const char *dev_id = DEVICE(root)->id;
object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 33b7b52f45..fbad11d6a7 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -190,8 +190,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
-void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
- int index, int chip_id);
+void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id);
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 09/12] ppc/pnv: remove root port name from pnv_phb_attach_root_port()
2022-06-24 8:49 ` [PATCH v3 09/12] ppc/pnv: remove root port name from pnv_phb_attach_root_port() Daniel Henrique Barboza
@ 2022-07-27 17:43 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:43 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> We support only a single root port, PNV_PHB_ROOT_PORT.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb.c | 7 +------
> hw/ppc/pnv.c | 9 +++++----
> include/hw/ppc/pnv.h | 3 +--
> 3 files changed, 7 insertions(+), 12 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> index da729e89e7..cc15a949c9 100644
> --- a/hw/pci-host/pnv_phb.c
> +++ b/hw/pci-host/pnv_phb.c
> @@ -24,7 +24,6 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
> PnvPHB *phb = PNV_PHB(dev);
> PCIHostState *pci = PCI_HOST_BRIDGE(dev);
> g_autofree char *phb_typename = NULL;
> - g_autofree char *phb_rootport_typename = NULL;
>
> if (!phb->version) {
> error_setg(errp, "version not specified");
> @@ -34,15 +33,12 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
> switch (phb->version) {
> case 3:
> phb_typename = g_strdup(TYPE_PNV_PHB3);
> - phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
> break;
> case 4:
> phb_typename = g_strdup(TYPE_PNV_PHB4);
> - phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
> break;
> case 5:
> phb_typename = g_strdup(TYPE_PNV_PHB5);
> - phb_rootport_typename = g_strdup(TYPE_PNV_PHB_ROOT_PORT);
> break;
> default:
> g_assert_not_reached();
> @@ -73,8 +69,7 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp)
> pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
> }
>
> - pnv_phb_attach_root_port(pci, phb_rootport_typename,
> - phb->phb_id, phb->chip_id);
> + pnv_phb_attach_root_port(pci, phb->phb_id, phb->chip_id);
> }
>
> static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 159899103e..5b7cbfc699 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1199,11 +1199,12 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
> * QOM id. 'chip_id' is going to be used as PCIE chassis for the
> * root port.
> */
> -void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
> - int index, int chip_id)
> +void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
> {
> - PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
> - g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index);
> + PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
> + g_autofree char *default_id = g_strdup_printf("%s[%d]",
> + TYPE_PNV_PHB_ROOT_PORT,
> + index);
> const char *dev_id = DEVICE(root)->id;
>
> object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 33b7b52f45..fbad11d6a7 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -190,8 +190,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
> TYPE_PNV_CHIP_POWER10)
>
> PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
> -void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
> - int index, int chip_id);
> +void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id);
>
> #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
> typedef struct PnvMachineClass PnvMachineClass;
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 10/12] ppc/pnv: remove pecc->rp_model
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (8 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 09/12] ppc/pnv: remove root port name from pnv_phb_attach_root_port() Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:43 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 11/12] ppc/pnv: remove PnvPHB4.version Daniel Henrique Barboza
` (2 subsequent siblings)
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
The attribute is unused.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb4_pec.c | 2 --
include/hw/pci-host/pnv_phb4.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 0ef66b9a9b..8dc363d69c 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -260,7 +260,6 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
pecc->version = PNV_PHB4_VERSION;
pecc->phb_type = TYPE_PNV_PHB4;
pecc->num_phbs = pnv_pec_num_phbs;
- pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
}
static const TypeInfo pnv_pec_type_info = {
@@ -313,7 +312,6 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
pecc->version = PNV_PHB5_VERSION;
pecc->phb_type = TYPE_PNV_PHB5;
pecc->num_phbs = pnv_phb5_pec_num_stacks;
- pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
}
static const TypeInfo pnv_phb5_pec_type_info = {
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 29c49ac79c..61a0cb9989 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -200,7 +200,6 @@ struct PnvPhb4PecClass {
uint64_t version;
const char *phb_type;
const uint32_t *num_phbs;
- const char *rp_model;
};
/*
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 10/12] ppc/pnv: remove pecc->rp_model
2022-06-24 8:49 ` [PATCH v3 10/12] ppc/pnv: remove pecc->rp_model Daniel Henrique Barboza
@ 2022-07-27 17:43 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:43 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> The attribute is unused.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb4_pec.c | 2 --
> include/hw/pci-host/pnv_phb4.h | 1 -
> 2 files changed, 3 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
> index 0ef66b9a9b..8dc363d69c 100644
> --- a/hw/pci-host/pnv_phb4_pec.c
> +++ b/hw/pci-host/pnv_phb4_pec.c
> @@ -260,7 +260,6 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
> pecc->version = PNV_PHB4_VERSION;
> pecc->phb_type = TYPE_PNV_PHB4;
> pecc->num_phbs = pnv_pec_num_phbs;
> - pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
> }
>
> static const TypeInfo pnv_pec_type_info = {
> @@ -313,7 +312,6 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
> pecc->version = PNV_PHB5_VERSION;
> pecc->phb_type = TYPE_PNV_PHB5;
> pecc->num_phbs = pnv_phb5_pec_num_stacks;
> - pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT;
> }
>
> static const TypeInfo pnv_phb5_pec_type_info = {
> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
> index 29c49ac79c..61a0cb9989 100644
> --- a/include/hw/pci-host/pnv_phb4.h
> +++ b/include/hw/pci-host/pnv_phb4.h
> @@ -200,7 +200,6 @@ struct PnvPhb4PecClass {
> uint64_t version;
> const char *phb_type;
> const uint32_t *num_phbs;
> - const char *rp_model;
> };
>
> /*
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 11/12] ppc/pnv: remove PnvPHB4.version
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (9 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 10/12] ppc/pnv: remove pecc->rp_model Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:44 ` Frederic Barrat
2022-06-24 8:49 ` [PATCH v3 12/12] ppc/pnv: move attach_root_port helper to pnv-phb.c Daniel Henrique Barboza
2022-07-27 17:28 ` [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Frederic Barrat
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
It's unused.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
include/hw/pci-host/pnv_phb4.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 61a0cb9989..20aa4819d3 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -77,8 +77,6 @@ struct PnvPHB4 {
uint32_t chip_id;
uint32_t phb_id;
- uint64_t version;
-
/* The owner PEC */
PnvPhb4PecState *pec;
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 11/12] ppc/pnv: remove PnvPHB4.version
2022-06-24 8:49 ` [PATCH v3 11/12] ppc/pnv: remove PnvPHB4.version Daniel Henrique Barboza
@ 2022-07-27 17:44 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:44 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> It's unused.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> include/hw/pci-host/pnv_phb4.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
> index 61a0cb9989..20aa4819d3 100644
> --- a/include/hw/pci-host/pnv_phb4.h
> +++ b/include/hw/pci-host/pnv_phb4.h
> @@ -77,8 +77,6 @@ struct PnvPHB4 {
> uint32_t chip_id;
> uint32_t phb_id;
>
> - uint64_t version;
> -
> /* The owner PEC */
> PnvPhb4PecState *pec;
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 12/12] ppc/pnv: move attach_root_port helper to pnv-phb.c
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (10 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 11/12] ppc/pnv: remove PnvPHB4.version Daniel Henrique Barboza
@ 2022-06-24 8:49 ` Daniel Henrique Barboza
2022-07-27 17:44 ` Frederic Barrat
2022-07-27 17:28 ` [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Frederic Barrat
12 siblings, 1 reply; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-24 8:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
The helper is only used in this file.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb.c | 24 ++++++++++++++++++++++++
hw/ppc/pnv.c | 25 -------------------------
include/hw/ppc/pnv.h | 1 -
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index cc15a949c9..c47ed92462 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -18,6 +18,30 @@
#include "hw/qdev-properties.h"
#include "qom/object.h"
+/*
+ * Attach a root port device.
+ *
+ * 'index' will be used both as a PCIE slot value and to calculate
+ * QOM id. 'chip_id' is going to be used as PCIE chassis for the
+ * root port.
+ */
+static void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
+{
+ PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
+ g_autofree char *default_id = g_strdup_printf("%s[%d]",
+ TYPE_PNV_PHB_ROOT_PORT,
+ index);
+ const char *dev_id = DEVICE(root)->id;
+
+ object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
+ OBJECT(root));
+
+ /* Set unique chassis/slot values for the root port */
+ qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
+ qdev_prop_set_uint16(DEVICE(root), "slot", index);
+
+ pci_realize_and_unref(root, pci->bus, &error_fatal);
+}
static void pnv_phb_realize(DeviceState *dev, Error **errp)
{
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5b7cbfc699..d649ed6b1b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1192,31 +1192,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
}
}
-/*
- * Attach a root port device.
- *
- * 'index' will be used both as a PCIE slot value and to calculate
- * QOM id. 'chip_id' is going to be used as PCIE chassis for the
- * root port.
- */
-void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
-{
- PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
- g_autofree char *default_id = g_strdup_printf("%s[%d]",
- TYPE_PNV_PHB_ROOT_PORT,
- index);
- const char *dev_id = DEVICE(root)->id;
-
- object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
- OBJECT(root));
-
- /* Set unique chassis/slot values for the root port */
- qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
- qdev_prop_set_uint16(DEVICE(root), "slot", index);
-
- pci_realize_and_unref(root, pci->bus, &error_fatal);
-}
-
static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index fbad11d6a7..033d907287 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -190,7 +190,6 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
-void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id);
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;
--
2.36.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH v3 12/12] ppc/pnv: move attach_root_port helper to pnv-phb.c
2022-06-24 8:49 ` [PATCH v3 12/12] ppc/pnv: move attach_root_port helper to pnv-phb.c Daniel Henrique Barboza
@ 2022-07-27 17:44 ` Frederic Barrat
0 siblings, 0 replies; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:44 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> The helper is only used in this file.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb.c | 24 ++++++++++++++++++++++++
> hw/ppc/pnv.c | 25 -------------------------
> include/hw/ppc/pnv.h | 1 -
> 3 files changed, 24 insertions(+), 26 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
> index cc15a949c9..c47ed92462 100644
> --- a/hw/pci-host/pnv_phb.c
> +++ b/hw/pci-host/pnv_phb.c
> @@ -18,6 +18,30 @@
> #include "hw/qdev-properties.h"
> #include "qom/object.h"
>
> +/*
> + * Attach a root port device.
> + *
> + * 'index' will be used both as a PCIE slot value and to calculate
> + * QOM id. 'chip_id' is going to be used as PCIE chassis for the
> + * root port.
> + */
> +static void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
> +{
> + PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
> + g_autofree char *default_id = g_strdup_printf("%s[%d]",
> + TYPE_PNV_PHB_ROOT_PORT,
> + index);
> + const char *dev_id = DEVICE(root)->id;
> +
> + object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
> + OBJECT(root));
> +
> + /* Set unique chassis/slot values for the root port */
> + qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
> + qdev_prop_set_uint16(DEVICE(root), "slot", index);
> +
> + pci_realize_and_unref(root, pci->bus, &error_fatal);
> +}
>
> static void pnv_phb_realize(DeviceState *dev, Error **errp)
> {
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 5b7cbfc699..d649ed6b1b 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1192,31 +1192,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
> }
> }
>
> -/*
> - * Attach a root port device.
> - *
> - * 'index' will be used both as a PCIE slot value and to calculate
> - * QOM id. 'chip_id' is going to be used as PCIE chassis for the
> - * root port.
> - */
> -void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id)
> -{
> - PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
> - g_autofree char *default_id = g_strdup_printf("%s[%d]",
> - TYPE_PNV_PHB_ROOT_PORT,
> - index);
> - const char *dev_id = DEVICE(root)->id;
> -
> - object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
> - OBJECT(root));
> -
> - /* Set unique chassis/slot values for the root port */
> - qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
> - qdev_prop_set_uint16(DEVICE(root), "slot", index);
> -
> - pci_realize_and_unref(root, pci->bus, &error_fatal);
> -}
> -
> static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
> {
> PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index fbad11d6a7..033d907287 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -190,7 +190,6 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
> TYPE_PNV_CHIP_POWER10)
>
> PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
> -void pnv_phb_attach_root_port(PCIHostState *pci, int index, int chip_id);
>
> #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
> typedef struct PnvMachineClass PnvMachineClass;
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices
2022-06-24 8:49 [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Daniel Henrique Barboza
` (11 preceding siblings ...)
2022-06-24 8:49 ` [PATCH v3 12/12] ppc/pnv: move attach_root_port helper to pnv-phb.c Daniel Henrique Barboza
@ 2022-07-27 17:28 ` Frederic Barrat
2022-07-28 13:12 ` Daniel Henrique Barboza
12 siblings, 1 reply; 30+ messages in thread
From: Frederic Barrat @ 2022-07-27 17:28 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
> Hi,
>
> This is the version 3 of the pnv-phb proxy device which has the
> following main differences from v2:
>
> - it's rebased on top of "[PATCH v3 0/8] pnv-phb related cleanups"
> - it doesn't have any patches related to user-created devices
>
> There is no user visible change made here yet. We're making device
> changes that are effective using default settings.
>
> Changes from v2:
> - all related changes made with the rebase on top of "[PATCH v3 0/8]
> pnv-phb related cleanups"
> - the following user devices patches were removed:
> - ppc/pnv: user created pnv-phb for powernv8
> - ppc/pnv: user created pnv-phb for powernv9
> - ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs
> - ppc/pnv: user creatable pnv-phb for powernv10
> - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2022-05/msg06254.html
This series look pretty good to me! I only have a couple of minor
comments, which I don't think are worth a resend.
Fred
> Daniel Henrique Barboza (12):
> ppc/pnv: add PHB3 bus init helper
> ppc/pnv: add PnvPHB base/proxy device
> ppc/pnv: turn PnvPHB3 into a PnvPHB backend
> ppc/pnv: add PHB4 bus init helper
> ppc/pnv: turn PnvPHB4 into a PnvPHB backend
> ppc/pnv: add pnv-phb-root-port device
> ppc/pnv: remove pnv-phb3-root-port
> ppc/pnv: remove pnv-phb4-root-port
> ppc/pnv: remove root port name from pnv_phb_attach_root_port()
> ppc/pnv: remove pecc->rp_model
> ppc/pnv: remove PnvPHB4.version
> ppc/pnv: move attach_root_port helper to pnv-phb.c
>
> hw/pci-host/meson.build | 3 +-
> hw/pci-host/pnv_phb.c | 244 +++++++++++++++++++++++++++++++++
> hw/pci-host/pnv_phb.h | 55 ++++++++
> hw/pci-host/pnv_phb3.c | 106 ++++----------
> hw/pci-host/pnv_phb4.c | 144 ++++---------------
> hw/pci-host/pnv_phb4_pec.c | 5 +-
> hw/ppc/pnv.c | 68 ++++-----
> include/hw/pci-host/pnv_phb3.h | 12 +-
> include/hw/pci-host/pnv_phb4.h | 18 +--
> include/hw/ppc/pnv.h | 5 +-
> 10 files changed, 401 insertions(+), 259 deletions(-)
> create mode 100644 hw/pci-host/pnv_phb.c
> create mode 100644 hw/pci-host/pnv_phb.h
>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices
2022-07-27 17:28 ` [PATCH v3 00/12] powernv: introduce pnv-phb base/proxy devices Frederic Barrat
@ 2022-07-28 13:12 ` Daniel Henrique Barboza
0 siblings, 0 replies; 30+ messages in thread
From: Daniel Henrique Barboza @ 2022-07-28 13:12 UTC (permalink / raw)
To: Frederic Barrat, qemu-devel; +Cc: qemu-ppc, clg
On 7/27/22 14:28, Frederic Barrat wrote:
>
>
> On 24/06/2022 10:49, Daniel Henrique Barboza wrote:
>> Hi,
>>
>> This is the version 3 of the pnv-phb proxy device which has the
>> following main differences from v2:
>>
>> - it's rebased on top of "[PATCH v3 0/8] pnv-phb related cleanups"
>> - it doesn't have any patches related to user-created devices
>>
>> There is no user visible change made here yet. We're making device
>> changes that are effective using default settings.
>>
>> Changes from v2:
>> - all related changes made with the rebase on top of "[PATCH v3 0/8]
>> pnv-phb related cleanups"
>> - the following user devices patches were removed:
>> - ppc/pnv: user created pnv-phb for powernv8
>> - ppc/pnv: user created pnv-phb for powernv9
>> - ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs
>> - ppc/pnv: user creatable pnv-phb for powernv10
>> - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2022-05/msg06254.html
>
>
> This series look pretty good to me! I only have a couple of minor comments, which I don't think are worth a resend.
>
> Fred
Thanks for the review! Patches queued in gitlab.com/danielhb/qemu/tree/ppc-7.2 .
Daniel
>
>
>
>> Daniel Henrique Barboza (12):
>> ppc/pnv: add PHB3 bus init helper
>> ppc/pnv: add PnvPHB base/proxy device
>> ppc/pnv: turn PnvPHB3 into a PnvPHB backend
>> ppc/pnv: add PHB4 bus init helper
>> ppc/pnv: turn PnvPHB4 into a PnvPHB backend
>> ppc/pnv: add pnv-phb-root-port device
>> ppc/pnv: remove pnv-phb3-root-port
>> ppc/pnv: remove pnv-phb4-root-port
>> ppc/pnv: remove root port name from pnv_phb_attach_root_port()
>> ppc/pnv: remove pecc->rp_model
>> ppc/pnv: remove PnvPHB4.version
>> ppc/pnv: move attach_root_port helper to pnv-phb.c
>>
>> hw/pci-host/meson.build | 3 +-
>> hw/pci-host/pnv_phb.c | 244 +++++++++++++++++++++++++++++++++
>> hw/pci-host/pnv_phb.h | 55 ++++++++
>> hw/pci-host/pnv_phb3.c | 106 ++++----------
>> hw/pci-host/pnv_phb4.c | 144 ++++---------------
>> hw/pci-host/pnv_phb4_pec.c | 5 +-
>> hw/ppc/pnv.c | 68 ++++-----
>> include/hw/pci-host/pnv_phb3.h | 12 +-
>> include/hw/pci-host/pnv_phb4.h | 18 +--
>> include/hw/ppc/pnv.h | 5 +-
>> 10 files changed, 401 insertions(+), 259 deletions(-)
>> create mode 100644 hw/pci-host/pnv_phb.c
>> create mode 100644 hw/pci-host/pnv_phb.h
>>
^ permalink raw reply [flat|nested] 30+ messages in thread