* [PATCH v2 0/9] Add support for AST1030 SoC
@ 2022-03-31 8:15 Jamin Lin
2022-03-31 8:15 ` [PATCH v2 1/9] aspeed/adc: Add AST1030 support Jamin Lin
` (8 more replies)
0 siblings, 9 replies; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Andrew Jeffery,
Joel Stanley, Alistair Francis, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
Changes from v2:
- replace aspeed_ast1030.c with aspeed_ast10xx.c for minibmc SOCs family support
- Add "ast1030-evb" machine in aspeed.c and removes aspeed_minibmc.c
Changes from v1:
The patch series supports ADC, SCU, SMC, TIMER, and WDT for AST1030 SoC.
Add avocado test case for "ast1030-evb" machine.
Test steps:
1. Download image from
https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip
2. Extract the zip file to obtain zephyr.elf
3. Run ./qemu-system-arm -M ast1030-evb -kernel $PATH/zephyr.elf -nographic
4. Test IO by Zephyr command line, commands are refer to Aspeed Zephyr
SDK User Guide below
https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.04/Aspeed_Zephy_SDK_User_Guide_v00.01.04.pdf
- ADC(channel 0):
uart:~$ adc ADC0 resolution 10
uart:~$ adc ADC0 calibrate 1
uart:~$ adc ADC0 read_format 1
uart:~$ adc ADC0 read 0
[Result]
read: 1416mv
- SCU
uart:~$ md 7e6e2040
uart:~$ md 7e6e2080
uart:~$ md 7e6e20d0
uart:~$ md 7e6e2200
uart:~$ md 7e6e2300
uart:~$ md 7e6e25b0
[Result]
The register value should match the value of ast1030_a1_resets
in aspeed_scu.c
- Flash(fmc_cs0):
uart:~$ flash write fmc_cs0 0 0x12345678 0x87654321 0x34127856 0x78563412
uart:~$ flash read fmc_cs0 0 10
[Result]
00000000: 78 56 34 12 21 43 65 87 56 78 12 34 12 34 56 78 |xV4.!Ce. Vx.4.4Vx|
uart:~$ flash erase fmc_cs0 0
uart:~$ flash read fmc_cs0 0 10
[Result]
00000000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |........ ........|
- Timer(TIMER0):
uart:~$ timer start TIMER0 -p 2000 -t 0
TIMER0: period 20000 ms, type 0
[Result]
timer expired after 2 seconds
- Watchdog(WDT1):
uart:~$ mw 7e785008 4755
uart:~$ mw 7e78500c 1
[Result]
soc reset after 22 seconds
Based-on: 20220315075753.8591-3-steven_lee@aspeedtech.com
([v2,2/2] hw: aspeed_scu: Introduce clkin_25Mhz attribute)
Jamin Lin (2):
aspeed: Add an AST1030 eval board
test/avocado/machine_aspeed.py: Add ast1030 test case
Steven Lee (7):
aspeed/adc: Add AST1030 support
aspeed/smc: Add AST1030 support
aspeed/wdt: Fix ast2500/ast2600 default reload value.
aspeed/wdt: Add AST1030 support
aspeed/timer: Add AST1030 support.
aspeed/scu: Add AST1030 support
aspeed/soc : Add AST1030 support
hw/adc/aspeed_adc.c | 16 ++
hw/arm/aspeed.c | 111 +++++++++++
hw/arm/aspeed_ast10xx.c | 303 +++++++++++++++++++++++++++++++
hw/arm/meson.build | 6 +-
hw/misc/aspeed_scu.c | 63 +++++++
hw/ssi/aspeed_smc.c | 160 ++++++++++++++++
hw/timer/aspeed_timer.c | 17 ++
hw/watchdog/wdt_aspeed.c | 34 +++-
include/hw/adc/aspeed_adc.h | 1 +
include/hw/arm/aspeed.h | 21 +++
include/hw/arm/aspeed_soc.h | 3 +
include/hw/misc/aspeed_scu.h | 24 +++
include/hw/timer/aspeed_timer.h | 1 +
include/hw/watchdog/wdt_aspeed.h | 3 +
tests/avocado/machine_aspeed.py | 36 ++++
15 files changed, 796 insertions(+), 3 deletions(-)
create mode 100644 hw/arm/aspeed_ast10xx.c
create mode 100644 tests/avocado/machine_aspeed.py
--
2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/9] aspeed/adc: Add AST1030 support
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
2022-03-31 8:15 ` [PATCH v2 2/9] aspeed/smc: " Jamin Lin
` (7 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell, Cédric Le Goater,
Andrew Jeffery, Joel Stanley, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:STM32F205,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
From: Steven Lee <steven_lee@aspeedtech.com>
Per ast1030_v7.pdf, AST1030 ADC engine is identical to AST2600's ADC.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/adc/aspeed_adc.c | 16 ++++++++++++++++
include/hw/adc/aspeed_adc.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c
index c5fcae29f6..0d29663129 100644
--- a/hw/adc/aspeed_adc.c
+++ b/hw/adc/aspeed_adc.c
@@ -389,6 +389,15 @@ static void aspeed_2600_adc_class_init(ObjectClass *klass, void *data)
aac->nr_engines = 2;
}
+static void aspeed_1030_adc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedADCClass *aac = ASPEED_ADC_CLASS(klass);
+
+ dc->desc = "ASPEED 1030 ADC Controller";
+ aac->nr_engines = 2;
+}
+
static const TypeInfo aspeed_adc_info = {
.name = TYPE_ASPEED_ADC,
.parent = TYPE_SYS_BUS_DEVICE,
@@ -415,6 +424,12 @@ static const TypeInfo aspeed_2600_adc_info = {
.class_init = aspeed_2600_adc_class_init,
};
+static const TypeInfo aspeed_1030_adc_info = {
+ .name = TYPE_ASPEED_1030_ADC,
+ .parent = TYPE_ASPEED_ADC,
+ .class_init = aspeed_1030_adc_class_init, /* No change since AST2600 */
+};
+
static void aspeed_adc_register_types(void)
{
type_register_static(&aspeed_adc_engine_info);
@@ -422,6 +437,7 @@ static void aspeed_adc_register_types(void)
type_register_static(&aspeed_2400_adc_info);
type_register_static(&aspeed_2500_adc_info);
type_register_static(&aspeed_2600_adc_info);
+ type_register_static(&aspeed_1030_adc_info);
}
type_init(aspeed_adc_register_types);
diff --git a/include/hw/adc/aspeed_adc.h b/include/hw/adc/aspeed_adc.h
index 2f166e8be1..ff1d06ea91 100644
--- a/include/hw/adc/aspeed_adc.h
+++ b/include/hw/adc/aspeed_adc.h
@@ -17,6 +17,7 @@
#define TYPE_ASPEED_2400_ADC TYPE_ASPEED_ADC "-ast2400"
#define TYPE_ASPEED_2500_ADC TYPE_ASPEED_ADC "-ast2500"
#define TYPE_ASPEED_2600_ADC TYPE_ASPEED_ADC "-ast2600"
+#define TYPE_ASPEED_1030_ADC TYPE_ASPEED_ADC "-ast1030"
OBJECT_DECLARE_TYPE(AspeedADCState, AspeedADCClass, ASPEED_ADC)
#define TYPE_ASPEED_ADC_ENGINE "aspeed.adc.engine"
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 2/9] aspeed/smc: Add AST1030 support
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
2022-03-31 8:15 ` [PATCH v2 1/9] aspeed/adc: Add AST1030 support Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
2022-03-31 15:59 ` Cédric Le Goater
2022-03-31 8:15 ` [PATCH v2 3/9] aspeed/wdt: Fix ast2500/ast2600 default reload value Jamin Lin
` (6 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell, Cédric Le Goater,
Andrew Jeffery, Joel Stanley, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:STM32F205,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
From: Steven Lee <steven_lee@aspeedtech.com>
AST1030 spi controller's address decoding unit is 1MB that is identical
to ast2600, but fmc address decoding unit is 512kb.
Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller.
In addition, add ast1030 fmc, spi1, and spi2 class init handler.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
hw/ssi/aspeed_smc.c | 160 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 48305e1574..81af783729 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -1696,6 +1696,163 @@ static const TypeInfo aspeed_2600_spi2_info = {
.class_init = aspeed_2600_spi2_class_init,
};
+/*
+ * The FMC Segment Registers of the AST1030 have a 512KB unit.
+ * Only bits [27:19] are used for decoding.
+ */
+#define AST1030_SEG_ADDR_MASK 0x0ff80000
+
+static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s,
+ const AspeedSegments *seg)
+{
+ uint32_t reg = 0;
+
+ /* Disabled segments have a nil register */
+ if (!seg->size) {
+ return 0;
+ }
+
+ reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */
+ reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */
+ return reg;
+}
+
+static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s,
+ uint32_t reg, AspeedSegments *seg)
+{
+ uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK;
+ uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK;
+ AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+
+ if (reg) {
+ seg->addr = asc->flash_window_base + start_offset;
+ seg->size = end_offset + (512 * KiB) - start_offset;
+ } else {
+ seg->addr = asc->flash_window_base;
+ seg->size = 0;
+ }
+}
+
+static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = {
+ [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
+ CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
+};
+
+static const AspeedSegments aspeed_1030_fmc_segments[] = {
+ { 0x0, 128 * MiB }, /* start address is readonly */
+ { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
+ { 0x0, 0 }, /* disabled */
+};
+
+static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
+
+ dc->desc = "Aspeed 1030 FMC Controller";
+ asc->r_conf = R_CONF;
+ asc->r_ce_ctrl = R_CE_CTRL;
+ asc->r_ctrl0 = R_CTRL0;
+ asc->r_timings = R_TIMINGS;
+ asc->nregs_timings = 2;
+ asc->conf_enable_w0 = CONF_ENABLE_W0;
+ asc->cs_num_max = 2;
+ asc->segments = aspeed_1030_fmc_segments;
+ asc->segment_addr_mask = 0x0ff80ff8;
+ asc->resets = aspeed_1030_fmc_resets;
+ asc->flash_window_base = 0x80000000;
+ asc->flash_window_size = 0x10000000;
+ asc->features = ASPEED_SMC_FEATURE_DMA |
+ ASPEED_SMC_FEATURE_WDT_CONTROL;
+ asc->dma_flash_mask = 0x0FFFFFFC;
+ asc->dma_dram_mask = 0x000BFFFC;
+ asc->nregs = ASPEED_SMC_R_MAX;
+ asc->segment_to_reg = aspeed_1030_smc_segment_to_reg;
+ asc->reg_to_segment = aspeed_1030_smc_reg_to_segment;
+ asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+}
+
+static const TypeInfo aspeed_1030_fmc_info = {
+ .name = "aspeed.fmc-ast1030",
+ .parent = TYPE_ASPEED_SMC,
+ .class_init = aspeed_1030_fmc_class_init,
+};
+
+static const AspeedSegments aspeed_1030_spi1_segments[] = {
+ { 0x0, 128 * MiB }, /* start address is readonly */
+ { 0x0, 0 }, /* disabled */
+};
+
+static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
+
+ dc->desc = "Aspeed 1030 SPI1 Controller";
+ asc->r_conf = R_CONF;
+ asc->r_ce_ctrl = R_CE_CTRL;
+ asc->r_ctrl0 = R_CTRL0;
+ asc->r_timings = R_TIMINGS;
+ asc->nregs_timings = 2;
+ asc->conf_enable_w0 = CONF_ENABLE_W0;
+ asc->cs_num_max = 2;
+ asc->segments = aspeed_1030_spi1_segments;
+ asc->segment_addr_mask = 0x0ff00ff0;
+ asc->flash_window_base = 0x90000000;
+ asc->flash_window_size = 0x10000000;
+ asc->features = ASPEED_SMC_FEATURE_DMA |
+ ASPEED_SMC_FEATURE_WDT_CONTROL;
+ asc->dma_flash_mask = 0x0FFFFFFC;
+ asc->dma_dram_mask = 0x000BFFFC;
+ asc->nregs = ASPEED_SMC_R_MAX;
+ asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
+ asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
+ asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+}
+
+static const TypeInfo aspeed_1030_spi1_info = {
+ .name = "aspeed.spi1-ast1030",
+ .parent = TYPE_ASPEED_SMC,
+ .class_init = aspeed_1030_spi1_class_init,
+};
+static const AspeedSegments aspeed_1030_spi2_segments[] = {
+ { 0x0, 128 * MiB }, /* start address is readonly */
+ { 0x0, 0 }, /* disabled */
+};
+
+static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
+
+ dc->desc = "Aspeed 1030 SPI2 Controller";
+ asc->r_conf = R_CONF;
+ asc->r_ce_ctrl = R_CE_CTRL;
+ asc->r_ctrl0 = R_CTRL0;
+ asc->r_timings = R_TIMINGS;
+ asc->nregs_timings = 2;
+ asc->conf_enable_w0 = CONF_ENABLE_W0;
+ asc->cs_num_max = 2;
+ asc->segments = aspeed_1030_spi2_segments;
+ asc->segment_addr_mask = 0x0ff00ff0;
+ asc->flash_window_base = 0xb0000000;
+ asc->flash_window_size = 0x10000000;
+ asc->features = ASPEED_SMC_FEATURE_DMA |
+ ASPEED_SMC_FEATURE_WDT_CONTROL;
+ asc->dma_flash_mask = 0x0FFFFFFC;
+ asc->dma_dram_mask = 0x000BFFFC;
+ asc->nregs = ASPEED_SMC_R_MAX;
+ asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
+ asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
+ asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+}
+
+static const TypeInfo aspeed_1030_spi2_info = {
+ .name = "aspeed.spi2-ast1030",
+ .parent = TYPE_ASPEED_SMC,
+ .class_init = aspeed_1030_spi2_class_init,
+};
+
static void aspeed_smc_register_types(void)
{
type_register_static(&aspeed_smc_flash_info);
@@ -1709,6 +1866,9 @@ static void aspeed_smc_register_types(void)
type_register_static(&aspeed_2600_fmc_info);
type_register_static(&aspeed_2600_spi1_info);
type_register_static(&aspeed_2600_spi2_info);
+ type_register_static(&aspeed_1030_fmc_info);
+ type_register_static(&aspeed_1030_spi1_info);
+ type_register_static(&aspeed_1030_spi2_info);
}
type_init(aspeed_smc_register_types)
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 3/9] aspeed/wdt: Fix ast2500/ast2600 default reload value.
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
2022-03-31 8:15 ` [PATCH v2 1/9] aspeed/adc: Add AST1030 support Jamin Lin
2022-03-31 8:15 ` [PATCH v2 2/9] aspeed/smc: " Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
2022-03-31 8:15 ` [PATCH v2 4/9] aspeed/wdt: Add AST1030 support Jamin Lin
` (5 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Andrew Jeffery,
Joel Stanley, Alistair Francis, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
From: Steven Lee <steven_lee@aspeedtech.com>
Per ast2500_2520_datasheet_v1.8 and ast2600v11.pdf, the default value of
WDT00 and WDT04 is 0x014FB180 for ast2500/ast2600.
Add default_status and default_reload_value attributes for storing
counter status and reload value as they are different from ast2400.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/watchdog/wdt_aspeed.c | 10 ++++++++--
include/hw/watchdog/wdt_aspeed.h | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 6aa6f90b66..386928e9c0 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -232,8 +232,8 @@ static void aspeed_wdt_reset(DeviceState *dev)
AspeedWDTState *s = ASPEED_WDT(dev);
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
- s->regs[WDT_STATUS] = 0x3EF1480;
- s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
+ s->regs[WDT_STATUS] = awc->default_status;
+ s->regs[WDT_RELOAD_VALUE] = awc->default_reload_value;
s->regs[WDT_RESTART] = 0;
s->regs[WDT_CTRL] = awc->sanitize_ctrl(0);
s->regs[WDT_RESET_WIDTH] = 0xFF;
@@ -319,6 +319,8 @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
awc->wdt_reload = aspeed_wdt_reload;
awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl;
+ awc->default_status = 0x03EF1480;
+ awc->default_reload_value = 0x03EF1480;
}
static const TypeInfo aspeed_2400_wdt_info = {
@@ -355,6 +357,8 @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
awc->wdt_reload = aspeed_wdt_reload_1mhz;
awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl;
+ awc->default_status = 0x014FB180;
+ awc->default_reload_value = 0x014FB180;
}
static const TypeInfo aspeed_2500_wdt_info = {
@@ -376,6 +380,8 @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
awc->wdt_reload = aspeed_wdt_reload_1mhz;
awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
+ awc->default_status = 0x014FB180;
+ awc->default_reload_value = 0x014FB180;
}
static const TypeInfo aspeed_2600_wdt_info = {
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index f945cd6c58..0e37f39f38 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -45,6 +45,8 @@ struct AspeedWDTClass {
void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
void (*wdt_reload)(AspeedWDTState *s);
uint64_t (*sanitize_ctrl)(uint64_t data);
+ uint32_t default_status;
+ uint32_t default_reload_value;
};
#endif /* WDT_ASPEED_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 4/9] aspeed/wdt: Add AST1030 support
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
` (2 preceding siblings ...)
2022-03-31 8:15 ` [PATCH v2 3/9] aspeed/wdt: Fix ast2500/ast2600 default reload value Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
2022-03-31 8:15 ` [PATCH v2 5/9] aspeed/timer: " Jamin Lin
` (4 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell, Cédric Le Goater,
Andrew Jeffery, Joel Stanley, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:STM32F205,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
From: Steven Lee <steven_lee@aspeedtech.com>
AST1030 wdt controller is similiar to AST2600's wdt, but it has extra
registers.
Introduce ast1030 object class and increse the number of regs(offset) of
ast1030 model.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/watchdog/wdt_aspeed.c | 24 ++++++++++++++++++++++++
include/hw/watchdog/wdt_aspeed.h | 1 +
2 files changed, 25 insertions(+)
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 386928e9c0..31855afdf4 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -391,6 +391,29 @@ static const TypeInfo aspeed_2600_wdt_info = {
.class_init = aspeed_2600_wdt_class_init,
};
+static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
+
+ dc->desc = "ASPEED 1030 Watchdog Controller";
+ awc->offset = 0x80;
+ awc->ext_pulse_width_mask = 0xfffff; /* TODO */
+ awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
+ awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
+ awc->wdt_reload = aspeed_wdt_reload_1mhz;
+ awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
+ awc->default_status = 0x014FB180;
+ awc->default_reload_value = 0x014FB180;
+}
+
+static const TypeInfo aspeed_1030_wdt_info = {
+ .name = TYPE_ASPEED_1030_WDT,
+ .parent = TYPE_ASPEED_WDT,
+ .instance_size = sizeof(AspeedWDTState),
+ .class_init = aspeed_1030_wdt_class_init,
+};
+
static void wdt_aspeed_register_types(void)
{
watchdog_add_model(&model);
@@ -398,6 +421,7 @@ static void wdt_aspeed_register_types(void)
type_register_static(&aspeed_2400_wdt_info);
type_register_static(&aspeed_2500_wdt_info);
type_register_static(&aspeed_2600_wdt_info);
+ type_register_static(&aspeed_1030_wdt_info);
}
type_init(wdt_aspeed_register_types)
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index 0e37f39f38..dfa5dfa424 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -19,6 +19,7 @@ OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
+#define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
#define ASPEED_WDT_REGS_MAX (0x20 / 4)
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 5/9] aspeed/timer: Add AST1030 support.
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
` (3 preceding siblings ...)
2022-03-31 8:15 ` [PATCH v2 4/9] aspeed/wdt: Add AST1030 support Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
2022-03-31 8:15 ` [PATCH v2 6/9] aspeed/scu: " Jamin Lin
` (3 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Andrew Jeffery,
Joel Stanley, Alistair Francis, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
From: Steven Lee <steven_lee@aspeedtech.com>
ast1030 tmc(timer controller) is identical to ast2600 tmc.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/timer/aspeed_timer.c | 17 +++++++++++++++++
include/hw/timer/aspeed_timer.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 42c47d2ce6..9c20b3d6ad 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -745,12 +745,29 @@ static const TypeInfo aspeed_2600_timer_info = {
.class_init = aspeed_2600_timer_class_init,
};
+static void aspeed_1030_timer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass);
+
+ dc->desc = "ASPEED 1030 Timer";
+ awc->read = aspeed_2600_timer_read;
+ awc->write = aspeed_2600_timer_write;
+}
+
+static const TypeInfo aspeed_1030_timer_info = {
+ .name = TYPE_ASPEED_1030_TIMER,
+ .parent = TYPE_ASPEED_TIMER,
+ .class_init = aspeed_1030_timer_class_init,
+};
+
static void aspeed_timer_register_types(void)
{
type_register_static(&aspeed_timer_info);
type_register_static(&aspeed_2400_timer_info);
type_register_static(&aspeed_2500_timer_info);
type_register_static(&aspeed_2600_timer_info);
+ type_register_static(&aspeed_1030_timer_info);
}
type_init(aspeed_timer_register_types)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index d36034a10c..07dc6b6f2c 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -31,6 +31,7 @@ OBJECT_DECLARE_TYPE(AspeedTimerCtrlState, AspeedTimerClass, ASPEED_TIMER)
#define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
#define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
#define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
+#define TYPE_ASPEED_1030_TIMER TYPE_ASPEED_TIMER "-ast1030"
#define ASPEED_TIMER_NR_TIMERS 8
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 6/9] aspeed/scu: Add AST1030 support
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
` (4 preceding siblings ...)
2022-03-31 8:15 ` [PATCH v2 5/9] aspeed/timer: " Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
2022-03-31 8:15 ` [PATCH v2 7/9] aspeed/soc : " Jamin Lin
` (2 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Andrew Jeffery,
Joel Stanley, Alistair Francis, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
From: Steven Lee <steven_lee@aspeedtech.com>
Per ast1030_v07.pdf, AST1030 SOC doesn't have SCU300, the pclk divider
selection is defined in SCU310[11:8].
Add a get_apb_freq function and a class init handler for ast1030.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/aspeed_scu.c | 63 ++++++++++++++++++++++++++++++++++++
include/hw/misc/aspeed_scu.h | 24 ++++++++++++++
2 files changed, 87 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 150567f98a..19b03471fc 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -235,6 +235,15 @@ static uint32_t aspeed_2600_scu_get_apb_freq(AspeedSCUState *s)
/ asc->apb_divider;
}
+static uint32_t aspeed_1030_scu_get_apb_freq(AspeedSCUState *s)
+{
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
+ uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]);
+
+ return hpll / (SCU_AST1030_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL4]) + 1)
+ / asc->apb_divider;
+}
+
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -482,6 +491,8 @@ static uint32_t aspeed_silicon_revs[] = {
AST2600_A1_SILICON_REV,
AST2600_A2_SILICON_REV,
AST2600_A3_SILICON_REV,
+ AST1030_A0_SILICON_REV,
+ AST1030_A1_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t silicon_rev)
@@ -770,12 +781,64 @@ static const TypeInfo aspeed_2600_scu_info = {
.class_init = aspeed_2600_scu_class_init,
};
+static const uint32_t ast1030_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
+ [AST2600_SYS_RST_CTRL] = 0xFFC3FED8,
+ [AST2600_SYS_RST_CTRL2] = 0x09FFFFFC,
+ [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
+ [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
+ [AST2600_DEBUG_CTRL2] = 0x00000000,
+ [AST2600_HPLL_PARAM] = 0x10004077,
+ [AST2600_HPLL_EXT] = 0x00000031,
+ [AST2600_CLK_SEL4] = 0x43F90900,
+ [AST2600_CLK_SEL5] = 0x40000000,
+ [AST2600_CHIP_ID0] = 0xDEADBEEF,
+ [AST2600_CHIP_ID1] = 0x0BADCAFE,
+};
+
+static void aspeed_ast1030_scu_reset(DeviceState *dev)
+{
+ AspeedSCUState *s = ASPEED_SCU(dev);
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+
+ memcpy(s->regs, asc->resets, asc->nr_regs * 4);
+
+ s->regs[AST2600_SILICON_REV] = AST1030_A1_SILICON_REV;
+ s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
+ s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
+ s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
+ s->regs[PROT_KEY] = s->hw_prot_key;
+}
+
+static void aspeed_1030_scu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
+
+ dc->desc = "ASPEED 1030 System Control Unit";
+ dc->reset = aspeed_ast1030_scu_reset;
+ asc->resets = ast1030_a1_resets;
+ asc->calc_hpll = aspeed_2600_scu_calc_hpll;
+ asc->get_apb = aspeed_1030_scu_get_apb_freq;
+ asc->apb_divider = 2;
+ asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
+ asc->clkin_25Mhz = true;
+ asc->ops = &aspeed_ast2600_scu_ops;
+}
+
+static const TypeInfo aspeed_1030_scu_info = {
+ .name = TYPE_ASPEED_1030_SCU,
+ .parent = TYPE_ASPEED_SCU,
+ .instance_size = sizeof(AspeedSCUState),
+ .class_init = aspeed_1030_scu_class_init,
+};
+
static void aspeed_scu_register_types(void)
{
type_register_static(&aspeed_scu_info);
type_register_static(&aspeed_2400_scu_info);
type_register_static(&aspeed_2500_scu_info);
type_register_static(&aspeed_2600_scu_info);
+ type_register_static(&aspeed_1030_scu_info);
}
type_init(aspeed_scu_register_types);
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index fdc721846c..d2c485c8f6 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -19,6 +19,7 @@ OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU)
#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
+#define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
@@ -45,6 +46,8 @@ struct AspeedSCUState {
#define AST2600_A1_SILICON_REV 0x05010303U
#define AST2600_A2_SILICON_REV 0x05020303U
#define AST2600_A3_SILICON_REV 0x05030303U
+#define AST1030_A0_SILICON_REV 0x80000000U
+#define AST1030_A1_SILICON_REV 0x80010000U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
@@ -335,4 +338,25 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
#define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24)
#define SCU_AST2600_H_PLL_OFF (0x1 << 23)
+/* SCU310 Clock Selection Register Set 4 (for Aspeed AST1030 SOC)
+ *
+ * 31 I3C Clock Source selection
+ * 30:28 I3C clock divider selection
+ * 26:24 MAC AHB clock divider selection
+ * 22:20 RGMII 125MHz clock divider ration
+ * 19:16 RGMII 50MHz clock divider ration
+ * 15 LHCLK clock generation/output enable control
+ * 14:12 LHCLK divider selection
+ * 11:8 APB Bus PCLK divider selection
+ * 7 Select PECI clock source
+ * 6 Select UART debug port clock source
+ * 5 Select UART6 clock source
+ * 4 Select UART5 clock source
+ * 3 Select UART4 clock source
+ * 2 Select UART3 clock source
+ * 1 Select UART2 clock source
+ * 0 Select UART1 clock source
+ */
+#define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf)
+
#endif /* ASPEED_SCU_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 7/9] aspeed/soc : Add AST1030 support
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
` (5 preceding siblings ...)
2022-03-31 8:15 ` [PATCH v2 6/9] aspeed/scu: " Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
2022-03-31 11:08 ` Cédric Le Goater
2022-03-31 8:15 ` [PATCH v2 8/9] aspeed: Add an AST1030 eval board Jamin Lin
2022-03-31 8:15 ` [PATCH v2 9/9] test/avocado/machine_aspeed.py: Add ast1030 test case Jamin Lin
8 siblings, 1 reply; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell, Cédric Le Goater,
Andrew Jeffery, Joel Stanley, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:STM32F205,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
From: Steven Lee <steven_lee@aspeedtech.com>
The embedded core of AST1030 SoC is ARM Coretex M4.
It is hard to be integrated in the common Aspeed Soc framework.
We introduce a new ast1030 class with instance_init and realize
handlers.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
hw/arm/aspeed_ast10xx.c | 303 ++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 6 +-
include/hw/arm/aspeed_soc.h | 3 +
3 files changed, 311 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/aspeed_ast10xx.c
diff --git a/hw/arm/aspeed_ast10xx.c b/hw/arm/aspeed_ast10xx.c
new file mode 100644
index 0000000000..939a183a6a
--- /dev/null
+++ b/hw/arm/aspeed_ast10xx.c
@@ -0,0 +1,303 @@
+/*
+ * ASPEED AST10xx SoC
+ *
+ * Copyright (C) 2022 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Implementation extracted from the AST2600 and adapted for AST10xx
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
+#include "hw/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "hw/char/serial.h"
+
+#include "hw/arm/aspeed_soc.h"
+
+#define ASPEED_SOC_IOMEM_SIZE 0x00200000
+
+static const hwaddr aspeed_soc_ast1030_memmap[] = {
+ [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_SBC] = 0x79000000,
+ [ASPEED_DEV_IOMEM] = 0x7E600000,
+ [ASPEED_DEV_PWM] = 0x7E610000,
+ [ASPEED_DEV_FMC] = 0x7E620000,
+ [ASPEED_DEV_SPI1] = 0x7E630000,
+ [ASPEED_DEV_SPI2] = 0x7E640000,
+ [ASPEED_DEV_SCU] = 0x7E6E2000,
+ [ASPEED_DEV_ADC] = 0x7E6E9000,
+ [ASPEED_DEV_SBC] = 0x7E6F2000,
+ [ASPEED_DEV_GPIO] = 0x7E780000,
+ [ASPEED_DEV_TIMER1] = 0x7E782000,
+ [ASPEED_DEV_UART5] = 0x7E784000,
+ [ASPEED_DEV_WDT] = 0x7E785000,
+ [ASPEED_DEV_LPC] = 0x7E789000,
+ [ASPEED_DEV_I2C] = 0x7E7B0000,
+};
+
+static const int aspeed_soc_ast1030_irqmap[] = {
+ [ASPEED_DEV_UART5] = 8,
+ [ASPEED_DEV_GPIO] = 11,
+ [ASPEED_DEV_TIMER1] = 16,
+ [ASPEED_DEV_TIMER2] = 17,
+ [ASPEED_DEV_TIMER3] = 18,
+ [ASPEED_DEV_TIMER4] = 19,
+ [ASPEED_DEV_TIMER5] = 20,
+ [ASPEED_DEV_TIMER6] = 21,
+ [ASPEED_DEV_TIMER7] = 22,
+ [ASPEED_DEV_TIMER8] = 23,
+ [ASPEED_DEV_WDT] = 24,
+ [ASPEED_DEV_LPC] = 35,
+ [ASPEED_DEV_FMC] = 39,
+ [ASPEED_DEV_PWM] = 44,
+ [ASPEED_DEV_ADC] = 46,
+ [ASPEED_DEV_SPI1] = 65,
+ [ASPEED_DEV_SPI2] = 66,
+ [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
+ [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
+};
+
+static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ctrl]);
+}
+
+
+static void aspeed_soc_ast1030_init(Object *obj)
+{
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ char socname[8];
+ char typename[64];
+ int i;
+
+ if (sscanf(sc->name, "%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
+
+ object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+
+
+ snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
+ object_initialize_child(obj, "scu", &s->scu, typename);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
+
+ object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
+ object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
+
+ snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
+ object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
+
+ snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
+ object_initialize_child(obj, "adc", &s->adc, typename);
+
+ snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
+ object_initialize_child(obj, "fmc", &s->fmc, typename);
+
+ for (i = 0; i < sc->spis_num; i++) {
+ snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
+ }
+
+ object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
+
+ object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
+
+ for (i = 0; i < sc->wdts_num; i++) {
+ snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
+ object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
+ }
+}
+
+static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
+{
+ AspeedSoCState *s = ASPEED_SOC(dev_soc);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ MemoryRegion *system_memory = get_system_memory();
+ DeviceState *armv7m;
+ Error *err = NULL;
+ int i;
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /* General I/O memory space to catch all unimplemented device */
+ create_unimplemented_device("aspeed.sbc",
+ sc->memmap[ASPEED_DEV_SBC],
+ 0x40000);
+ create_unimplemented_device("aspeed.io",
+ sc->memmap[ASPEED_DEV_IOMEM],
+ ASPEED_SOC_IOMEM_SIZE);
+
+ /* AST1030 CPU Core */
+ armv7m = DEVICE(&s->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 256);
+ qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ object_property_set_link(OBJECT(&s->armv7m), "memory",
+ OBJECT(system_memory), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
+
+ /* Internal SRAM */
+ memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(system_memory,
+ sc->memmap[ASPEED_DEV_SRAM],
+ &s->sram);
+
+ /* SCU */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+
+ /* LPC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
+
+ /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
+
+ /*
+ * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
+ */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
+
+ /* UART5 - attach an 8250 to the IO space as our UART */
+ serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
+ aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
+ 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+
+ /* Timer */
+ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
+ sc->memmap[ASPEED_DEV_TIMER1]);
+ for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
+ qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
+ }
+
+ /* ADC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
+
+ /* FMC, The number of CS is set at the board level */
+ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
+ ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+
+ /* SPI */
+ for (i = 0; i < sc->spis_num; i++) {
+ object_property_set_link(OBJECT(&s->spi[i]), "dram",
+ OBJECT(&s->sram), &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ sc->memmap[ASPEED_DEV_SPI1 + i]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
+ ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
+ }
+
+ /* Secure Boot Controller */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
+
+ /* Watch dog */
+ for (i = 0; i < sc->wdts_num; i++) {
+ AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+
+ object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
+ sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
+ }
+}
+
+static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+ dc->realize = aspeed_soc_ast1030_realize;
+
+ sc->name = "ast1030-a1";
+ sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+ sc->silicon_rev = AST1030_A1_SILICON_REV;
+ sc->sram_size = 0xc0000;
+ sc->spis_num = 2;
+ sc->ehcis_num = 0;
+ sc->wdts_num = 4;
+ sc->macs_num = 1;
+ sc->irqmap = aspeed_soc_ast1030_irqmap;
+ sc->memmap = aspeed_soc_ast1030_memmap;
+ sc->num_cpus = 1;
+}
+
+static const TypeInfo aspeed_soc_ast1030_type_info = {
+ .name = "ast1030-a1",
+ .parent = TYPE_ASPEED_SOC,
+ .instance_size = sizeof(AspeedSoCState),
+ .instance_init = aspeed_soc_ast1030_init,
+ .class_init = aspeed_soc_ast1030_class_init,
+ .class_size = sizeof(AspeedSoCClass),
+};
+
+static void aspeed_soc_register_types(void)
+{
+ type_register_static(&aspeed_soc_ast1030_type_info);
+};
+
+type_init(aspeed_soc_register_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 721a8eb8be..ddb3cc3706 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -48,7 +48,11 @@ arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-ver
arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
-arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_soc.c', 'aspeed.c', 'aspeed_ast2600.c'))
+arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+ 'aspeed_soc.c',
+ 'aspeed.c',
+ 'aspeed_ast2600.c',
+ 'aspeed_ast10xx.c'))
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index da043dcb45..645d2dc83b 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -13,6 +13,7 @@
#define ASPEED_SOC_H
#include "hw/cpu/a15mpcore.h"
+#include "hw/arm/armv7m.h"
#include "hw/intc/aspeed_vic.h"
#include "hw/misc/aspeed_scu.h"
#include "hw/adc/aspeed_adc.h"
@@ -47,6 +48,7 @@ struct AspeedSoCState {
/*< public >*/
ARMCPU cpu[ASPEED_CPUS_NUM];
A15MPPrivState a7mpcore;
+ ARMv7MState armv7m;
MemoryRegion *dram_mr;
MemoryRegion sram;
AspeedVICState vic;
@@ -72,6 +74,7 @@ struct AspeedSoCState {
AspeedSDHCIState emmc;
AspeedLPCState lpc;
uint32_t uart_default;
+ Clock *sysclk;
};
#define TYPE_ASPEED_SOC "aspeed-soc"
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 8/9] aspeed: Add an AST1030 eval board
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
` (6 preceding siblings ...)
2022-03-31 8:15 ` [PATCH v2 7/9] aspeed/soc : " Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
2022-03-31 11:04 ` Cédric Le Goater
2022-03-31 8:15 ` [PATCH v2 9/9] test/avocado/machine_aspeed.py: Add ast1030 test case Jamin Lin
8 siblings, 1 reply; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Andrew Jeffery,
Joel Stanley, Alistair Francis, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
The image should be supplied with ELF binary.
$ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
hw/arm/aspeed.c | 111 ++++++++++++++++++++++++++++++++++++++++
include/hw/arm/aspeed.h | 21 ++++++++
2 files changed, 132 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index d205384d98..14ce0dff8b 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -24,6 +24,7 @@
#include "hw/loader.h"
#include "qemu/error-report.h"
#include "qemu/units.h"
+#include "hw/qdev-clock.h"
static struct arm_boot_info aspeed_board_binfo = {
.board_id = -1, /* device-tree-only board */
@@ -1361,3 +1362,113 @@ static const TypeInfo aspeed_machine_types[] = {
};
DEFINE_TYPES(aspeed_machine_types)
+
+#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
+
+struct AspeedMiniBmcMachineState {
+ /* Private */
+ MachineState parent_obj;
+ /* Public */
+
+ AspeedSoCState soc;
+ MemoryRegion ram_container;
+ MemoryRegion max_ram;
+ bool mmio_exec;
+ char *fmc_model;
+ char *spi_model;
+};
+
+/* Main SYSCLK frequency in Hz (200MHz) */
+#define SYSCLK_FRQ 200000000ULL
+
+static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
+ void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
+ amc->soc_name = "ast1030-a1";
+ amc->hw_strap1 = 0;
+ amc->hw_strap2 = 0;
+ mc->default_ram_size = 0;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
+ amc->fmc_model = "sst25vf032b";
+ amc->spi_model = "sst25vf032b";
+ amc->num_cs = 2;
+}
+
+static void ast1030_machine_instance_init(Object *obj)
+{
+ ASPEED_MINIBMC_MACHINE(obj)->mmio_exec = false;
+}
+
+static void aspeed_minibmc_machine_init(MachineState *machine)
+{
+ AspeedMiniBmcMachineState *bmc = ASPEED_MINIBMC_MACHINE(machine);
+ AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_GET_CLASS(machine);
+ Clock *sysclk;
+
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
+ object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
+ qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+
+ qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
+ amc->uart_default);
+ qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+
+ aspeed_board_init_flashes(&bmc->soc.fmc,
+ bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
+ amc->num_cs,
+ 0);
+
+ aspeed_board_init_flashes(&bmc->soc.spi[0],
+ bmc->spi_model ? bmc->spi_model : amc->spi_model,
+ amc->num_cs, amc->num_cs);
+
+ aspeed_board_init_flashes(&bmc->soc.spi[1],
+ bmc->spi_model ? bmc->spi_model : amc->spi_model,
+ amc->num_cs, (amc->num_cs * 2));
+
+ if (amc->i2c_init) {
+ amc->i2c_init(bmc);
+ }
+
+ armv7m_load_kernel(ARM_CPU(first_cpu),
+ machine->kernel_filename,
+ AST1030_INTERNAL_FLASH_SIZE);
+}
+
+static void aspeed_minibmc_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_CLASS(oc);
+
+ mc->init = aspeed_minibmc_machine_init;
+ mc->no_floppy = 1;
+ mc->no_cdrom = 1;
+ mc->no_parallel = 1;
+ mc->default_ram_id = "ram";
+ amc->uart_default = ASPEED_DEV_UART5;
+}
+
+static const TypeInfo aspeed_minibmc_machine_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("ast1030-evb"),
+ .parent = TYPE_ASPEED_MINIBMC_MACHINE,
+ .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
+ }, {
+ .name = TYPE_ASPEED_MINIBMC_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(AspeedMiniBmcMachineState),
+ .instance_init = ast1030_machine_instance_init,
+ .class_size = sizeof(AspeedMiniBmcMachineClass),
+ .class_init = aspeed_minibmc_machine_class_init,
+ .abstract = true,
+ }
+};
+
+DEFINE_TYPES(aspeed_minibmc_machine_types)
+
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index cbeacb214c..d300ab0042 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -13,12 +13,18 @@
#include "qom/object.h"
typedef struct AspeedMachineState AspeedMachineState;
+typedef struct AspeedMiniBmcMachineState AspeedMiniBmcMachineState;
#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
+#define TYPE_ASPEED_MINIBMC_MACHINE MACHINE_TYPE_NAME("aspeed-minibmc")
typedef struct AspeedMachineClass AspeedMachineClass;
DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineClass,
ASPEED_MACHINE, TYPE_ASPEED_MACHINE)
+typedef struct AspeedMiniBmcMachineClass AspeedMiniBmcMachineClass;
+DECLARE_OBJ_CHECKERS(AspeedMiniBmcMachineState, AspeedMiniBmcMachineClass,
+ ASPEED_MINIBMC_MACHINE, TYPE_ASPEED_MINIBMC_MACHINE)
+
#define ASPEED_MAC0_ON (1 << 0)
#define ASPEED_MAC1_ON (1 << 1)
#define ASPEED_MAC2_ON (1 << 2)
@@ -41,5 +47,20 @@ struct AspeedMachineClass {
uint32_t uart_default;
};
+struct AspeedMiniBmcMachineClass {
+ MachineClass parent_obj;
+
+ const char *name;
+ const char *desc;
+ const char *soc_name;
+ uint32_t hw_strap1;
+ uint32_t hw_strap2;
+ const char *fmc_model;
+ const char *spi_model;
+ uint32_t num_cs;
+ uint32_t macs_mask;
+ void (*i2c_init)(AspeedMiniBmcMachineState *bmc);
+ uint32_t uart_default;
+};
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 9/9] test/avocado/machine_aspeed.py: Add ast1030 test case
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
` (7 preceding siblings ...)
2022-03-31 8:15 ` [PATCH v2 8/9] aspeed: Add an AST1030 eval board Jamin Lin
@ 2022-03-31 8:15 ` Jamin Lin
8 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-03-31 8:15 UTC (permalink / raw)
To: Alistair Francis, Peter Maydell, Cédric Le Goater,
Andrew Jeffery, Joel Stanley, Cleber Rosa,
Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:STM32F205,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
Add test case to test "ast1030-evb" machine with zephyr os
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
tests/avocado/machine_aspeed.py | 36 +++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 tests/avocado/machine_aspeed.py
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
new file mode 100644
index 0000000000..33090af199
--- /dev/null
+++ b/tests/avocado/machine_aspeed.py
@@ -0,0 +1,36 @@
+# Functional test that boots the ASPEED SoCs with firmware
+#
+# Copyright (C) 2022 ASPEED Technology Inc
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado_qemu import QemuSystemTest
+from avocado_qemu import wait_for_console_pattern
+from avocado_qemu import exec_command_and_wait_for_pattern
+from avocado.utils import archive
+
+
+class AST1030Machine(QemuSystemTest):
+ """Boots the zephyr os and checks that the console is operational"""
+
+ timeout = 10
+
+ def test_ast1030_zephyros(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:ast1030-evb
+ """
+ tar_url = ('https://github.com/AspeedTech-BMC'
+ '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip')
+ tar_hash = '4c6a8ce3a8ba76ef1a65dae419ae3409343c4b20'
+ tar_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
+ archive.extract(tar_path, self.workdir)
+ kernel_file = self.workdir + "/ast1030-evb-demo/zephyr.elf"
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_file,
+ '-nographic')
+ self.vm.launch()
+ wait_for_console_pattern(self, "Booting Zephyr OS")
+ exec_command_and_wait_for_pattern(self, "help",
+ "Available commands")
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 8/9] aspeed: Add an AST1030 eval board
2022-03-31 8:15 ` [PATCH v2 8/9] aspeed: Add an AST1030 eval board Jamin Lin
@ 2022-03-31 11:04 ` Cédric Le Goater
2022-04-01 1:24 ` Jamin Lin
0 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2022-03-31 11:04 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Andrew Jeffery, Joel Stanley,
Alistair Francis, Cleber Rosa, Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, steven_lee
Hello Jamin,
On 3/31/22 10:15, Jamin Lin wrote:
> The image should be supplied with ELF binary.
> $ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
> hw/arm/aspeed.c | 111 ++++++++++++++++++++++++++++++++++++++++
> include/hw/arm/aspeed.h | 21 ++++++++
> 2 files changed, 132 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index d205384d98..14ce0dff8b 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -24,6 +24,7 @@
> #include "hw/loader.h"
> #include "qemu/error-report.h"
> #include "qemu/units.h"
> +#include "hw/qdev-clock.h"
>
> static struct arm_boot_info aspeed_board_binfo = {
> .board_id = -1, /* device-tree-only board */
> @@ -1361,3 +1362,113 @@ static const TypeInfo aspeed_machine_types[] = {
> };
>
> DEFINE_TYPES(aspeed_machine_types)
> +
> +#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
> +
> +struct AspeedMiniBmcMachineState {
> + /* Private */
> + MachineState parent_obj;
> + /* Public */
> +
> + AspeedSoCState soc;
> + MemoryRegion ram_container;
> + MemoryRegion max_ram;
> + bool mmio_exec;
> + char *fmc_model;
> + char *spi_model;
> +};
>
Why duplicate the state structure since it is the same ?
> +/* Main SYSCLK frequency in Hz (200MHz) */
> +#define SYSCLK_FRQ 200000000ULL
> +
> +static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
> + void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_CLASS(oc);
> +
> + mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
> + amc->soc_name = "ast1030-a1";
> + amc->hw_strap1 = 0;
> + amc->hw_strap2 = 0;
> + mc->default_ram_size = 0;
> + mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
> + amc->fmc_model = "sst25vf032b";
> + amc->spi_model = "sst25vf032b";
> + amc->num_cs = 2;
> +}
> +
> +static void ast1030_machine_instance_init(Object *obj)
> +{
> + ASPEED_MINIBMC_MACHINE(obj)->mmio_exec = false;
> +}
> +
> +static void aspeed_minibmc_machine_init(MachineState *machine)
> +{
> + AspeedMiniBmcMachineState *bmc = ASPEED_MINIBMC_MACHINE(machine);
> + AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_GET_CLASS(machine);
> + Clock *sysclk;
> +
> + sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(sysclk, SYSCLK_FRQ);
> +
> + object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
> + qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
> +
> + qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
> + amc->uart_default);
> + qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
> +
> + aspeed_board_init_flashes(&bmc->soc.fmc,
> + bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
> + amc->num_cs,
> + 0);
> +
> + aspeed_board_init_flashes(&bmc->soc.spi[0],
> + bmc->spi_model ? bmc->spi_model : amc->spi_model,
> + amc->num_cs, amc->num_cs);
> +
> + aspeed_board_init_flashes(&bmc->soc.spi[1],
> + bmc->spi_model ? bmc->spi_model : amc->spi_model,
> + amc->num_cs, (amc->num_cs * 2));
> +
> + if (amc->i2c_init) {
> + amc->i2c_init(bmc);
> + }
> +
> + armv7m_load_kernel(ARM_CPU(first_cpu),
> + machine->kernel_filename,
> + AST1030_INTERNAL_FLASH_SIZE);
> +}
> +
> +static void aspeed_minibmc_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_CLASS(oc);
> +
> + mc->init = aspeed_minibmc_machine_init;
> + mc->no_floppy = 1;
> + mc->no_cdrom = 1;
> + mc->no_parallel = 1;
> + mc->default_ram_id = "ram";
> + amc->uart_default = ASPEED_DEV_UART5;
> +}
> +
> +static const TypeInfo aspeed_minibmc_machine_types[] = {
> + {
> + .name = MACHINE_TYPE_NAME("ast1030-evb"),
> + .parent = TYPE_ASPEED_MINIBMC_MACHINE,
> + .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
> + }, {
> + .name = TYPE_ASPEED_MINIBMC_MACHINE,
> + .parent = TYPE_MACHINE,
> + .instance_size = sizeof(AspeedMiniBmcMachineState),
> + .instance_init = ast1030_machine_instance_init,
> + .class_size = sizeof(AspeedMiniBmcMachineClass),
> + .class_init = aspeed_minibmc_machine_class_init,
> + .abstract = true,
> + }
> +};
> +
> +DEFINE_TYPES(aspeed_minibmc_machine_types)
> +
> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> index cbeacb214c..d300ab0042 100644
> --- a/include/hw/arm/aspeed.h
> +++ b/include/hw/arm/aspeed.h
> @@ -13,12 +13,18 @@
> #include "qom/object.h"
>
> typedef struct AspeedMachineState AspeedMachineState;
> +typedef struct AspeedMiniBmcMachineState AspeedMiniBmcMachineState;
>
> #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
> +#define TYPE_ASPEED_MINIBMC_MACHINE MACHINE_TYPE_NAME("aspeed-minibmc")
> typedef struct AspeedMachineClass AspeedMachineClass;
> DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineClass,
> ASPEED_MACHINE, TYPE_ASPEED_MACHINE)
>
> +typedef struct AspeedMiniBmcMachineClass AspeedMiniBmcMachineClass;
> +DECLARE_OBJ_CHECKERS(AspeedMiniBmcMachineState, AspeedMiniBmcMachineClass,
> + ASPEED_MINIBMC_MACHINE, TYPE_ASPEED_MINIBMC_MACHINE)
> +
> #define ASPEED_MAC0_ON (1 << 0)
> #define ASPEED_MAC1_ON (1 << 1)
> #define ASPEED_MAC2_ON (1 << 2)
> @@ -41,5 +47,20 @@ struct AspeedMachineClass {
> uint32_t uart_default;
> };
>
> +struct AspeedMiniBmcMachineClass {
> + MachineClass parent_obj;
> +
> + const char *name;
> + const char *desc;
> + const char *soc_name;
> + uint32_t hw_strap1;
> + uint32_t hw_strap2;
> + const char *fmc_model;
> + const char *spi_model;
> + uint32_t num_cs;
> + uint32_t macs_mask;
> + void (*i2c_init)(AspeedMiniBmcMachineState *bmc);
> + uint32_t uart_default;
> +};
I don't see a good reason to duplicate the class either.
Thanks,
C.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 7/9] aspeed/soc : Add AST1030 support
2022-03-31 8:15 ` [PATCH v2 7/9] aspeed/soc : " Jamin Lin
@ 2022-03-31 11:08 ` Cédric Le Goater
2022-04-01 1:26 ` Jamin Lin
0 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2022-03-31 11:08 UTC (permalink / raw)
To: Jamin Lin, Alistair Francis, Peter Maydell, Andrew Jeffery,
Joel Stanley, Cleber Rosa, Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:STM32F205,
open list:All patches CC here
Cc: troy_lee, steven_lee
On 3/31/22 10:15, Jamin Lin wrote:
> From: Steven Lee <steven_lee@aspeedtech.com>
>
> The embedded core of AST1030 SoC is ARM Coretex M4.
> It is hard to be integrated in the common Aspeed Soc framework.
> We introduce a new ast1030 class with instance_init and realize
> handlers.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
LTGM
Reviewed-by: Cédric Le Goater <clg@kaod.org>
In case you resend, please remove the double newlines. There are
a few below.
Thanks,
C.
> ---
> hw/arm/aspeed_ast10xx.c | 303 ++++++++++++++++++++++++++++++++++++
> hw/arm/meson.build | 6 +-
> include/hw/arm/aspeed_soc.h | 3 +
> 3 files changed, 311 insertions(+), 1 deletion(-)
> create mode 100644 hw/arm/aspeed_ast10xx.c
>
> diff --git a/hw/arm/aspeed_ast10xx.c b/hw/arm/aspeed_ast10xx.c
> new file mode 100644
> index 0000000000..939a183a6a
> --- /dev/null
> +++ b/hw/arm/aspeed_ast10xx.c
> @@ -0,0 +1,303 @@
> +/*
> + * ASPEED AST10xx SoC
> + *
> + * Copyright (C) 2022 ASPEED Technology Inc.
> + *
> + * This code is licensed under the GPL version 2 or later. See
> + * the COPYING file in the top-level directory.
> + *
> + * Implementation extracted from the AST2600 and adapted for AST10xx
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "exec/address-spaces.h"
> +#include "sysemu/sysemu.h"
> +#include "hw/qdev-clock.h"
> +#include "hw/misc/unimp.h"
> +#include "hw/char/serial.h"
> +
> +#include "hw/arm/aspeed_soc.h"
> +
> +#define ASPEED_SOC_IOMEM_SIZE 0x00200000
> +
> +static const hwaddr aspeed_soc_ast1030_memmap[] = {
> + [ASPEED_DEV_SRAM] = 0x00000000,
> + [ASPEED_DEV_SBC] = 0x79000000,
> + [ASPEED_DEV_IOMEM] = 0x7E600000,
> + [ASPEED_DEV_PWM] = 0x7E610000,
> + [ASPEED_DEV_FMC] = 0x7E620000,
> + [ASPEED_DEV_SPI1] = 0x7E630000,
> + [ASPEED_DEV_SPI2] = 0x7E640000,
> + [ASPEED_DEV_SCU] = 0x7E6E2000,
> + [ASPEED_DEV_ADC] = 0x7E6E9000,
> + [ASPEED_DEV_SBC] = 0x7E6F2000,
> + [ASPEED_DEV_GPIO] = 0x7E780000,
> + [ASPEED_DEV_TIMER1] = 0x7E782000,
> + [ASPEED_DEV_UART5] = 0x7E784000,
> + [ASPEED_DEV_WDT] = 0x7E785000,
> + [ASPEED_DEV_LPC] = 0x7E789000,
> + [ASPEED_DEV_I2C] = 0x7E7B0000,
> +};
> +
> +static const int aspeed_soc_ast1030_irqmap[] = {
> + [ASPEED_DEV_UART5] = 8,
> + [ASPEED_DEV_GPIO] = 11,
> + [ASPEED_DEV_TIMER1] = 16,
> + [ASPEED_DEV_TIMER2] = 17,
> + [ASPEED_DEV_TIMER3] = 18,
> + [ASPEED_DEV_TIMER4] = 19,
> + [ASPEED_DEV_TIMER5] = 20,
> + [ASPEED_DEV_TIMER6] = 21,
> + [ASPEED_DEV_TIMER7] = 22,
> + [ASPEED_DEV_TIMER8] = 23,
> + [ASPEED_DEV_WDT] = 24,
> + [ASPEED_DEV_LPC] = 35,
> + [ASPEED_DEV_FMC] = 39,
> + [ASPEED_DEV_PWM] = 44,
> + [ASPEED_DEV_ADC] = 46,
> + [ASPEED_DEV_SPI1] = 65,
> + [ASPEED_DEV_SPI2] = 66,
> + [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
> + [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
> +};
> +
> +static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
> +{
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> +
> + return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ctrl]);
> +}
> +
> +
> +static void aspeed_soc_ast1030_init(Object *obj)
> +{
> + AspeedSoCState *s = ASPEED_SOC(obj);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + char socname[8];
> + char typename[64];
> + int i;
> +
> + if (sscanf(sc->name, "%7s", socname) != 1) {
> + g_assert_not_reached();
> + }
> +
> + object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> +
> +
> + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> + object_initialize_child(obj, "scu", &s->scu, typename);
> + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
> +
> + object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
> + object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
> +
> + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
> + object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
> +
> + snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> + object_initialize_child(obj, "adc", &s->adc, typename);
> +
> + snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
> + object_initialize_child(obj, "fmc", &s->fmc, typename);
> +
> + for (i = 0; i < sc->spis_num; i++) {
> + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
> + object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
> + }
> +
> + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
> +
> + object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
> +
> + for (i = 0; i < sc->wdts_num; i++) {
> + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
> + object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
> + }
> +}
> +
> +static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> +{
> + AspeedSoCState *s = ASPEED_SOC(dev_soc);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + MemoryRegion *system_memory = get_system_memory();
> + DeviceState *armv7m;
> + Error *err = NULL;
> + int i;
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /* General I/O memory space to catch all unimplemented device */
> + create_unimplemented_device("aspeed.sbc",
> + sc->memmap[ASPEED_DEV_SBC],
> + 0x40000);
> + create_unimplemented_device("aspeed.io",
> + sc->memmap[ASPEED_DEV_IOMEM],
> + ASPEED_SOC_IOMEM_SIZE);
> +
> + /* AST1030 CPU Core */
> + armv7m = DEVICE(&s->armv7m);
> + qdev_prop_set_uint32(armv7m, "num-irq", 256);
> + qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + object_property_set_link(OBJECT(&s->armv7m), "memory",
> + OBJECT(system_memory), &error_abort);
> + sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
> +
> + /* Internal SRAM */
> + memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + memory_region_add_subregion(system_memory,
> + sc->memmap[ASPEED_DEV_SRAM],
> + &s->sram);
> +
> + /* SCU */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
> +
> + /* LPC */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
> +
> + /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
> + aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
> +
> + /*
> + * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
> + */
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
> +
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
> +
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
> +
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
> +
> + /* UART5 - attach an 8250 to the IO space as our UART */
> + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
> + aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
> + 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +
> + /* Timer */
> + object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
> + sc->memmap[ASPEED_DEV_TIMER1]);
> + for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
> + qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
> + }
> +
> + /* ADC */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
> + return;
> + }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
> + aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
> +
> + /* FMC, The number of CS is set at the board level */
> + object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
> + ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
> + aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
> +
> + /* SPI */
> + for (i = 0; i < sc->spis_num; i++) {
> + object_property_set_link(OBJECT(&s->spi[i]), "dram",
> + OBJECT(&s->sram), &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
> + sc->memmap[ASPEED_DEV_SPI1 + i]);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
> + ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
> + }
> +
> + /* Secure Boot Controller */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
> +
> + /* Watch dog */
> + for (i = 0; i < sc->wdts_num; i++) {
> + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
> +
> + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
> + sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
> + }
> +}
> +
> +static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
> +
> + dc->realize = aspeed_soc_ast1030_realize;
> +
> + sc->name = "ast1030-a1";
> + sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
> + sc->silicon_rev = AST1030_A1_SILICON_REV;
> + sc->sram_size = 0xc0000;
> + sc->spis_num = 2;
> + sc->ehcis_num = 0;
> + sc->wdts_num = 4;
> + sc->macs_num = 1;
> + sc->irqmap = aspeed_soc_ast1030_irqmap;
> + sc->memmap = aspeed_soc_ast1030_memmap;
> + sc->num_cpus = 1;
> +}
> +
> +static const TypeInfo aspeed_soc_ast1030_type_info = {
> + .name = "ast1030-a1",
> + .parent = TYPE_ASPEED_SOC,
> + .instance_size = sizeof(AspeedSoCState),
> + .instance_init = aspeed_soc_ast1030_init,
> + .class_init = aspeed_soc_ast1030_class_init,
> + .class_size = sizeof(AspeedSoCClass),
> +};
> +
> +static void aspeed_soc_register_types(void)
> +{
> + type_register_static(&aspeed_soc_ast1030_type_info);
> +};
> +
> +type_init(aspeed_soc_register_types)
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index 721a8eb8be..ddb3cc3706 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -48,7 +48,11 @@ arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-ver
> arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
> arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
> arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
> -arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_soc.c', 'aspeed.c', 'aspeed_ast2600.c'))
> +arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> + 'aspeed_soc.c',
> + 'aspeed.c',
> + 'aspeed_ast2600.c',
> + 'aspeed_ast10xx.c'))
> arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
> arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
> arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index da043dcb45..645d2dc83b 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -13,6 +13,7 @@
> #define ASPEED_SOC_H
>
> #include "hw/cpu/a15mpcore.h"
> +#include "hw/arm/armv7m.h"
> #include "hw/intc/aspeed_vic.h"
> #include "hw/misc/aspeed_scu.h"
> #include "hw/adc/aspeed_adc.h"
> @@ -47,6 +48,7 @@ struct AspeedSoCState {
> /*< public >*/
> ARMCPU cpu[ASPEED_CPUS_NUM];
> A15MPPrivState a7mpcore;
> + ARMv7MState armv7m;
> MemoryRegion *dram_mr;
> MemoryRegion sram;
> AspeedVICState vic;
> @@ -72,6 +74,7 @@ struct AspeedSoCState {
> AspeedSDHCIState emmc;
> AspeedLPCState lpc;
> uint32_t uart_default;
> + Clock *sysclk;
> };
>
> #define TYPE_ASPEED_SOC "aspeed-soc"
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/9] aspeed/smc: Add AST1030 support
2022-03-31 8:15 ` [PATCH v2 2/9] aspeed/smc: " Jamin Lin
@ 2022-03-31 15:59 ` Cédric Le Goater
2022-04-01 1:27 ` Jamin Lin
0 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2022-03-31 15:59 UTC (permalink / raw)
To: Jamin Lin, Alistair Francis, Peter Maydell, Andrew Jeffery,
Joel Stanley, Cleber Rosa, Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, Beraldo Leal, open list:STM32F205,
open list:All patches CC here
Cc: troy_lee, steven_lee
Hello Jamin,
On 3/31/22 10:15, Jamin Lin wrote:
> From: Steven Lee <steven_lee@aspeedtech.com>
>
> AST1030 spi controller's address decoding unit is 1MB that is identical
> to ast2600, but fmc address decoding unit is 512kb.
> Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller.
> In addition, add ast1030 fmc, spi1, and spi2 class init handler.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
I did a review of this patch, anyhow
Reviewed-by: Cédric Le Goater <clg@kaod.org>
but please drop the ASPEED_SMC_FEATURE_WDT_CONTROL flag which is not
upstream.
Thanks,
C.
> ---
> hw/ssi/aspeed_smc.c | 160 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 160 insertions(+)
>
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 48305e1574..81af783729 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -1696,6 +1696,163 @@ static const TypeInfo aspeed_2600_spi2_info = {
> .class_init = aspeed_2600_spi2_class_init,
> };
>
> +/*
> + * The FMC Segment Registers of the AST1030 have a 512KB unit.
> + * Only bits [27:19] are used for decoding.
> + */
> +#define AST1030_SEG_ADDR_MASK 0x0ff80000
> +
> +static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s,
> + const AspeedSegments *seg)
> +{
> + uint32_t reg = 0;
> +
> + /* Disabled segments have a nil register */
> + if (!seg->size) {
> + return 0;
> + }
> +
> + reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */
> + reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */
> + return reg;
> +}
> +
> +static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s,
> + uint32_t reg, AspeedSegments *seg)
> +{
> + uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK;
> + uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK;
> + AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
> +
> + if (reg) {
> + seg->addr = asc->flash_window_base + start_offset;
> + seg->size = end_offset + (512 * KiB) - start_offset;
> + } else {
> + seg->addr = asc->flash_window_base;
> + seg->size = 0;
> + }
> +}
> +
> +static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = {
> + [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
> + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
> +};
> +
> +static const AspeedSegments aspeed_1030_fmc_segments[] = {
> + { 0x0, 128 * MiB }, /* start address is readonly */
> + { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
> + { 0x0, 0 }, /* disabled */
> +};
> +
> +static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
> +
> + dc->desc = "Aspeed 1030 FMC Controller";
> + asc->r_conf = R_CONF;
> + asc->r_ce_ctrl = R_CE_CTRL;
> + asc->r_ctrl0 = R_CTRL0;
> + asc->r_timings = R_TIMINGS;
> + asc->nregs_timings = 2;
> + asc->conf_enable_w0 = CONF_ENABLE_W0;
> + asc->cs_num_max = 2;
> + asc->segments = aspeed_1030_fmc_segments;
> + asc->segment_addr_mask = 0x0ff80ff8;
> + asc->resets = aspeed_1030_fmc_resets;
> + asc->flash_window_base = 0x80000000;
> + asc->flash_window_size = 0x10000000;
> + asc->features = ASPEED_SMC_FEATURE_DMA |
> + ASPEED_SMC_FEATURE_WDT_CONTROL;
> + asc->dma_flash_mask = 0x0FFFFFFC;
> + asc->dma_dram_mask = 0x000BFFFC;
> + asc->nregs = ASPEED_SMC_R_MAX;
> + asc->segment_to_reg = aspeed_1030_smc_segment_to_reg;
> + asc->reg_to_segment = aspeed_1030_smc_reg_to_segment;
> + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
> +}
> +
> +static const TypeInfo aspeed_1030_fmc_info = {
> + .name = "aspeed.fmc-ast1030",
> + .parent = TYPE_ASPEED_SMC,
> + .class_init = aspeed_1030_fmc_class_init,
> +};
> +
> +static const AspeedSegments aspeed_1030_spi1_segments[] = {
> + { 0x0, 128 * MiB }, /* start address is readonly */
> + { 0x0, 0 }, /* disabled */
> +};
> +
> +static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
> +
> + dc->desc = "Aspeed 1030 SPI1 Controller";
> + asc->r_conf = R_CONF;
> + asc->r_ce_ctrl = R_CE_CTRL;
> + asc->r_ctrl0 = R_CTRL0;
> + asc->r_timings = R_TIMINGS;
> + asc->nregs_timings = 2;
> + asc->conf_enable_w0 = CONF_ENABLE_W0;
> + asc->cs_num_max = 2;
> + asc->segments = aspeed_1030_spi1_segments;
> + asc->segment_addr_mask = 0x0ff00ff0;
> + asc->flash_window_base = 0x90000000;
> + asc->flash_window_size = 0x10000000;
> + asc->features = ASPEED_SMC_FEATURE_DMA |
> + ASPEED_SMC_FEATURE_WDT_CONTROL;
> + asc->dma_flash_mask = 0x0FFFFFFC;
> + asc->dma_dram_mask = 0x000BFFFC;
> + asc->nregs = ASPEED_SMC_R_MAX;
> + asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
> + asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
> + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
> +}
> +
> +static const TypeInfo aspeed_1030_spi1_info = {
> + .name = "aspeed.spi1-ast1030",
> + .parent = TYPE_ASPEED_SMC,
> + .class_init = aspeed_1030_spi1_class_init,
> +};
> +static const AspeedSegments aspeed_1030_spi2_segments[] = {
> + { 0x0, 128 * MiB }, /* start address is readonly */
> + { 0x0, 0 }, /* disabled */
> +};
> +
> +static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
> +
> + dc->desc = "Aspeed 1030 SPI2 Controller";
> + asc->r_conf = R_CONF;
> + asc->r_ce_ctrl = R_CE_CTRL;
> + asc->r_ctrl0 = R_CTRL0;
> + asc->r_timings = R_TIMINGS;
> + asc->nregs_timings = 2;
> + asc->conf_enable_w0 = CONF_ENABLE_W0;
> + asc->cs_num_max = 2;
> + asc->segments = aspeed_1030_spi2_segments;
> + asc->segment_addr_mask = 0x0ff00ff0;
> + asc->flash_window_base = 0xb0000000;
> + asc->flash_window_size = 0x10000000;
> + asc->features = ASPEED_SMC_FEATURE_DMA |
> + ASPEED_SMC_FEATURE_WDT_CONTROL;
> + asc->dma_flash_mask = 0x0FFFFFFC;
> + asc->dma_dram_mask = 0x000BFFFC;
> + asc->nregs = ASPEED_SMC_R_MAX;
> + asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
> + asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
> + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
> +}
> +
> +static const TypeInfo aspeed_1030_spi2_info = {
> + .name = "aspeed.spi2-ast1030",
> + .parent = TYPE_ASPEED_SMC,
> + .class_init = aspeed_1030_spi2_class_init,
> +};
> +
> static void aspeed_smc_register_types(void)
> {
> type_register_static(&aspeed_smc_flash_info);
> @@ -1709,6 +1866,9 @@ static void aspeed_smc_register_types(void)
> type_register_static(&aspeed_2600_fmc_info);
> type_register_static(&aspeed_2600_spi1_info);
> type_register_static(&aspeed_2600_spi2_info);
> + type_register_static(&aspeed_1030_fmc_info);
> + type_register_static(&aspeed_1030_spi1_info);
> + type_register_static(&aspeed_1030_spi2_info);
> }
>
> type_init(aspeed_smc_register_types)
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 8/9] aspeed: Add an AST1030 eval board
2022-03-31 11:04 ` Cédric Le Goater
@ 2022-04-01 1:24 ` Jamin Lin
0 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-04-01 1:24 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Peter Maydell, Troy Lee, Beraldo Leal, Andrew Jeffery,
Alistair Francis, Steven Lee, Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, open list:All patches CC here,
open list:ASPEED BMCs, Joel Stanley, Cleber Rosa
The 03/31/2022 11:04, Cédric Le Goater wrote:
Hi Cedric,
> Hello Jamin,
>
> On 3/31/22 10:15, Jamin Lin wrote:
> > The image should be supplied with ELF binary.
> > $ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic
> >
> > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > ---
> > hw/arm/aspeed.c | 111 ++++++++++++++++++++++++++++++++++++++++
> > include/hw/arm/aspeed.h | 21 ++++++++
> > 2 files changed, 132 insertions(+)
> >
> > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> > index d205384d98..14ce0dff8b 100644
> > --- a/hw/arm/aspeed.c
> > +++ b/hw/arm/aspeed.c
> > @@ -24,6 +24,7 @@
> > #include "hw/loader.h"
> > #include "qemu/error-report.h"
> > #include "qemu/units.h"
> > +#include "hw/qdev-clock.h"
> >
> > static struct arm_boot_info aspeed_board_binfo = {
> > .board_id = -1, /* device-tree-only board */
> > @@ -1361,3 +1362,113 @@ static const TypeInfo aspeed_machine_types[] = {
> > };
> >
> > DEFINE_TYPES(aspeed_machine_types)
> > +
> > +#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
> > +
> > +struct AspeedMiniBmcMachineState {
> > + /* Private */
> > + MachineState parent_obj;
> > + /* Public */
> > +
> > + AspeedSoCState soc;
> > + MemoryRegion ram_container;
> > + MemoryRegion max_ram;
> > + bool mmio_exec;
> > + char *fmc_model;
> > + char *spi_model;
> > +};
> >
>
> Why duplicate the state structure since it is the same ?
>
Will fix
> > +/* Main SYSCLK frequency in Hz (200MHz) */
> > +#define SYSCLK_FRQ 200000000ULL
> > +
> > +static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
> > + void *data)
> > +{
> > + MachineClass *mc = MACHINE_CLASS(oc);
> > + AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_CLASS(oc);
> > +
> > + mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
> > + amc->soc_name = "ast1030-a1";
> > + amc->hw_strap1 = 0;
> > + amc->hw_strap2 = 0;
> > + mc->default_ram_size = 0;
> > + mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
> > + amc->fmc_model = "sst25vf032b";
> > + amc->spi_model = "sst25vf032b";
> > + amc->num_cs = 2;
> > +}
> > +
> > +static void ast1030_machine_instance_init(Object *obj)
> > +{
> > + ASPEED_MINIBMC_MACHINE(obj)->mmio_exec = false;
> > +}
> > +
> > +static void aspeed_minibmc_machine_init(MachineState *machine)
> > +{
> > + AspeedMiniBmcMachineState *bmc = ASPEED_MINIBMC_MACHINE(machine);
> > + AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_GET_CLASS(machine);
> > + Clock *sysclk;
> > +
> > + sysclk = clock_new(OBJECT(machine), "SYSCLK");
> > + clock_set_hz(sysclk, SYSCLK_FRQ);
> > +
> > + object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
> > + qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
> > +
> > + qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
> > + amc->uart_default);
> > + qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
> > +
> > + aspeed_board_init_flashes(&bmc->soc.fmc,
> > + bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
> > + amc->num_cs,
> > + 0);
> > +
> > + aspeed_board_init_flashes(&bmc->soc.spi[0],
> > + bmc->spi_model ? bmc->spi_model : amc->spi_model,
> > + amc->num_cs, amc->num_cs);
> > +
> > + aspeed_board_init_flashes(&bmc->soc.spi[1],
> > + bmc->spi_model ? bmc->spi_model : amc->spi_model,
> > + amc->num_cs, (amc->num_cs * 2));
> > +
> > + if (amc->i2c_init) {
> > + amc->i2c_init(bmc);
> > + }
> > +
> > + armv7m_load_kernel(ARM_CPU(first_cpu),
> > + machine->kernel_filename,
> > + AST1030_INTERNAL_FLASH_SIZE);
> > +}
> > +
> > +static void aspeed_minibmc_machine_class_init(ObjectClass *oc, void *data)
> > +{
> > + MachineClass *mc = MACHINE_CLASS(oc);
> > + AspeedMiniBmcMachineClass *amc = ASPEED_MINIBMC_MACHINE_CLASS(oc);
> > +
> > + mc->init = aspeed_minibmc_machine_init;
> > + mc->no_floppy = 1;
> > + mc->no_cdrom = 1;
> > + mc->no_parallel = 1;
> > + mc->default_ram_id = "ram";
> > + amc->uart_default = ASPEED_DEV_UART5;
> > +}
> > +
> > +static const TypeInfo aspeed_minibmc_machine_types[] = {
> > + {
> > + .name = MACHINE_TYPE_NAME("ast1030-evb"),
> > + .parent = TYPE_ASPEED_MINIBMC_MACHINE,
> > + .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
> > + }, {
> > + .name = TYPE_ASPEED_MINIBMC_MACHINE,
> > + .parent = TYPE_MACHINE,
> > + .instance_size = sizeof(AspeedMiniBmcMachineState),
> > + .instance_init = ast1030_machine_instance_init,
> > + .class_size = sizeof(AspeedMiniBmcMachineClass),
> > + .class_init = aspeed_minibmc_machine_class_init,
> > + .abstract = true,
> > + }
> > +};
> > +
> > +DEFINE_TYPES(aspeed_minibmc_machine_types)
> > +
> > diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> > index cbeacb214c..d300ab0042 100644
> > --- a/include/hw/arm/aspeed.h
> > +++ b/include/hw/arm/aspeed.h
> > @@ -13,12 +13,18 @@
> > #include "qom/object.h"
> >
> > typedef struct AspeedMachineState AspeedMachineState;
> > +typedef struct AspeedMiniBmcMachineState AspeedMiniBmcMachineState;
> >
> > #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
> > +#define TYPE_ASPEED_MINIBMC_MACHINE MACHINE_TYPE_NAME("aspeed-minibmc")
> > typedef struct AspeedMachineClass AspeedMachineClass;
> > DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineClass,
> > ASPEED_MACHINE, TYPE_ASPEED_MACHINE)
> >
> > +typedef struct AspeedMiniBmcMachineClass AspeedMiniBmcMachineClass;
> > +DECLARE_OBJ_CHECKERS(AspeedMiniBmcMachineState, AspeedMiniBmcMachineClass,
> > + ASPEED_MINIBMC_MACHINE, TYPE_ASPEED_MINIBMC_MACHINE)
> > +
> > #define ASPEED_MAC0_ON (1 << 0)
> > #define ASPEED_MAC1_ON (1 << 1)
> > #define ASPEED_MAC2_ON (1 << 2)
> > @@ -41,5 +47,20 @@ struct AspeedMachineClass {
> > uint32_t uart_default;
> > };
> >
> > +struct AspeedMiniBmcMachineClass {
> > + MachineClass parent_obj;
> > +
> > + const char *name;
> > + const char *desc;
> > + const char *soc_name;
> > + uint32_t hw_strap1;
> > + uint32_t hw_strap2;
> > + const char *fmc_model;
> > + const char *spi_model;
> > + uint32_t num_cs;
> > + uint32_t macs_mask;
> > + void (*i2c_init)(AspeedMiniBmcMachineState *bmc);
> > + uint32_t uart_default;
> > +};
>
> I don't see a good reason to duplicate the class either.
>
> Thanks,
>
> C.
Will fix
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 7/9] aspeed/soc : Add AST1030 support
2022-03-31 11:08 ` Cédric Le Goater
@ 2022-04-01 1:26 ` Jamin Lin
0 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-04-01 1:26 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Peter Maydell, Troy Lee, Beraldo Leal, Andrew Jeffery,
Alistair Francis, Steven Lee, Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, open list:All patches CC here,
open list:STM32F205, Joel Stanley, Cleber Rosa
The 03/31/2022 11:08, Cédric Le Goater wrote:
> On 3/31/22 10:15, Jamin Lin wrote:
> > From: Steven Lee <steven_lee@aspeedtech.com>
> >
> > The embedded core of AST1030 SoC is ARM Coretex M4.
> > It is hard to be integrated in the common Aspeed Soc framework.
> > We introduce a new ast1030 class with instance_init and realize
> > handlers.
> >
> > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
>
> LTGM
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>
> In case you resend, please remove the double newlines. There are
> a few below.
>
> Thanks,
>
> C.
>
Will fix
> > ---
> > hw/arm/aspeed_ast10xx.c | 303 ++++++++++++++++++++++++++++++++++++
> > hw/arm/meson.build | 6 +-
> > include/hw/arm/aspeed_soc.h | 3 +
> > 3 files changed, 311 insertions(+), 1 deletion(-)
> > create mode 100644 hw/arm/aspeed_ast10xx.c
> >
> > diff --git a/hw/arm/aspeed_ast10xx.c b/hw/arm/aspeed_ast10xx.c
> > new file mode 100644
> > index 0000000000..939a183a6a
> > --- /dev/null
> > +++ b/hw/arm/aspeed_ast10xx.c
> > @@ -0,0 +1,303 @@
> > +/*
> > + * ASPEED AST10xx SoC
> > + *
> > + * Copyright (C) 2022 ASPEED Technology Inc.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * Implementation extracted from the AST2600 and adapted for AST10xx
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "exec/address-spaces.h"
> > +#include "sysemu/sysemu.h"
> > +#include "hw/qdev-clock.h"
> > +#include "hw/misc/unimp.h"
> > +#include "hw/char/serial.h"
> > +
> > +#include "hw/arm/aspeed_soc.h"
> > +
> > +#define ASPEED_SOC_IOMEM_SIZE 0x00200000
> > +
> > +static const hwaddr aspeed_soc_ast1030_memmap[] = {
> > + [ASPEED_DEV_SRAM] = 0x00000000,
> > + [ASPEED_DEV_SBC] = 0x79000000,
> > + [ASPEED_DEV_IOMEM] = 0x7E600000,
> > + [ASPEED_DEV_PWM] = 0x7E610000,
> > + [ASPEED_DEV_FMC] = 0x7E620000,
> > + [ASPEED_DEV_SPI1] = 0x7E630000,
> > + [ASPEED_DEV_SPI2] = 0x7E640000,
> > + [ASPEED_DEV_SCU] = 0x7E6E2000,
> > + [ASPEED_DEV_ADC] = 0x7E6E9000,
> > + [ASPEED_DEV_SBC] = 0x7E6F2000,
> > + [ASPEED_DEV_GPIO] = 0x7E780000,
> > + [ASPEED_DEV_TIMER1] = 0x7E782000,
> > + [ASPEED_DEV_UART5] = 0x7E784000,
> > + [ASPEED_DEV_WDT] = 0x7E785000,
> > + [ASPEED_DEV_LPC] = 0x7E789000,
> > + [ASPEED_DEV_I2C] = 0x7E7B0000,
> > +};
> > +
> > +static const int aspeed_soc_ast1030_irqmap[] = {
> > + [ASPEED_DEV_UART5] = 8,
> > + [ASPEED_DEV_GPIO] = 11,
> > + [ASPEED_DEV_TIMER1] = 16,
> > + [ASPEED_DEV_TIMER2] = 17,
> > + [ASPEED_DEV_TIMER3] = 18,
> > + [ASPEED_DEV_TIMER4] = 19,
> > + [ASPEED_DEV_TIMER5] = 20,
> > + [ASPEED_DEV_TIMER6] = 21,
> > + [ASPEED_DEV_TIMER7] = 22,
> > + [ASPEED_DEV_TIMER8] = 23,
> > + [ASPEED_DEV_WDT] = 24,
> > + [ASPEED_DEV_LPC] = 35,
> > + [ASPEED_DEV_FMC] = 39,
> > + [ASPEED_DEV_PWM] = 44,
> > + [ASPEED_DEV_ADC] = 46,
> > + [ASPEED_DEV_SPI1] = 65,
> > + [ASPEED_DEV_SPI2] = 66,
> > + [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
> > + [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
> > +};
> > +
> > +static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
> > +{
> > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > +
> > + return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ctrl]);
> > +}
> > +
> > +
> > +static void aspeed_soc_ast1030_init(Object *obj)
> > +{
> > + AspeedSoCState *s = ASPEED_SOC(obj);
> > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > + char socname[8];
> > + char typename[64];
> > + int i;
> > +
> > + if (sscanf(sc->name, "%7s", socname) != 1) {
> > + g_assert_not_reached();
> > + }
> > +
> > + object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
> > +
> > + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> > +
> > +
> > + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> > + object_initialize_child(obj, "scu", &s->scu, typename);
> > + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
> > +
> > + object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
> > + object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
> > +
> > + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
> > + object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
> > +
> > + snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> > + object_initialize_child(obj, "adc", &s->adc, typename);
> > +
> > + snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
> > + object_initialize_child(obj, "fmc", &s->fmc, typename);
> > +
> > + for (i = 0; i < sc->spis_num; i++) {
> > + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
> > + object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
> > + }
> > +
> > + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
> > +
> > + object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
> > +
> > + for (i = 0; i < sc->wdts_num; i++) {
> > + snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
> > + object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
> > + }
> > +}
> > +
> > +static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> > +{
> > + AspeedSoCState *s = ASPEED_SOC(dev_soc);
> > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > + MemoryRegion *system_memory = get_system_memory();
> > + DeviceState *armv7m;
> > + Error *err = NULL;
> > + int i;
> > +
> > + if (!clock_has_source(s->sysclk)) {
> > + error_setg(errp, "sysclk clock must be wired up by the board code");
> > + return;
> > + }
> > +
> > + /* General I/O memory space to catch all unimplemented device */
> > + create_unimplemented_device("aspeed.sbc",
> > + sc->memmap[ASPEED_DEV_SBC],
> > + 0x40000);
> > + create_unimplemented_device("aspeed.io",
> > + sc->memmap[ASPEED_DEV_IOMEM],
> > + ASPEED_SOC_IOMEM_SIZE);
> > +
> > + /* AST1030 CPU Core */
> > + armv7m = DEVICE(&s->armv7m);
> > + qdev_prop_set_uint32(armv7m, "num-irq", 256);
> > + qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
> > + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> > + object_property_set_link(OBJECT(&s->armv7m), "memory",
> > + OBJECT(system_memory), &error_abort);
> > + sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
> > +
> > + /* Internal SRAM */
> > + memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &err);
> > + if (err != NULL) {
> > + error_propagate(errp, err);
> > + return;
> > + }
> > + memory_region_add_subregion(system_memory,
> > + sc->memmap[ASPEED_DEV_SRAM],
> > + &s->sram);
> > +
> > + /* SCU */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
> > +
> > + /* LPC */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
> > +
> > + /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
> > + aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
> > +
> > + /*
> > + * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
> > + */
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
> > + qdev_get_gpio_in(DEVICE(&s->armv7m),
> > + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
> > +
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
> > + qdev_get_gpio_in(DEVICE(&s->armv7m),
> > + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
> > +
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
> > + qdev_get_gpio_in(DEVICE(&s->armv7m),
> > + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
> > +
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
> > + qdev_get_gpio_in(DEVICE(&s->armv7m),
> > + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
> > +
> > + /* UART5 - attach an 8250 to the IO space as our UART */
> > + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
> > + aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
> > + 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
> > +
> > + /* Timer */
> > + object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
> > + &error_abort);
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
> > + sc->memmap[ASPEED_DEV_TIMER1]);
> > + for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
> > + qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
> > + }
> > +
> > + /* ADC */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
> > + return;
> > + }
> > +
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
> > + aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
> > +
> > + /* FMC, The number of CS is set at the board level */
> > + object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
> > + &error_abort);
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
> > + ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
> > + aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
> > +
> > + /* SPI */
> > + for (i = 0; i < sc->spis_num; i++) {
> > + object_property_set_link(OBJECT(&s->spi[i]), "dram",
> > + OBJECT(&s->sram), &error_abort);
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
> > + sc->memmap[ASPEED_DEV_SPI1 + i]);
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
> > + ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
> > + }
> > +
> > + /* Secure Boot Controller */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
> > +
> > + /* Watch dog */
> > + for (i = 0; i < sc->wdts_num; i++) {
> > + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
> > +
> > + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
> > + &error_abort);
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
> > + sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
> > + }
> > +}
> > +
> > +static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
> > +
> > + dc->realize = aspeed_soc_ast1030_realize;
> > +
> > + sc->name = "ast1030-a1";
> > + sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
> > + sc->silicon_rev = AST1030_A1_SILICON_REV;
> > + sc->sram_size = 0xc0000;
> > + sc->spis_num = 2;
> > + sc->ehcis_num = 0;
> > + sc->wdts_num = 4;
> > + sc->macs_num = 1;
> > + sc->irqmap = aspeed_soc_ast1030_irqmap;
> > + sc->memmap = aspeed_soc_ast1030_memmap;
> > + sc->num_cpus = 1;
> > +}
> > +
> > +static const TypeInfo aspeed_soc_ast1030_type_info = {
> > + .name = "ast1030-a1",
> > + .parent = TYPE_ASPEED_SOC,
> > + .instance_size = sizeof(AspeedSoCState),
> > + .instance_init = aspeed_soc_ast1030_init,
> > + .class_init = aspeed_soc_ast1030_class_init,
> > + .class_size = sizeof(AspeedSoCClass),
> > +};
> > +
> > +static void aspeed_soc_register_types(void)
> > +{
> > + type_register_static(&aspeed_soc_ast1030_type_info);
> > +};
> > +
> > +type_init(aspeed_soc_register_types)
> > diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> > index 721a8eb8be..ddb3cc3706 100644
> > --- a/hw/arm/meson.build
> > +++ b/hw/arm/meson.build
> > @@ -48,7 +48,11 @@ arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-ver
> > arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
> > arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
> > arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
> > -arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_soc.c', 'aspeed.c', 'aspeed_ast2600.c'))
> > +arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> > + 'aspeed_soc.c',
> > + 'aspeed.c',
> > + 'aspeed_ast2600.c',
> > + 'aspeed_ast10xx.c'))
> > arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
> > arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
> > arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index da043dcb45..645d2dc83b 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -13,6 +13,7 @@
> > #define ASPEED_SOC_H
> >
> > #include "hw/cpu/a15mpcore.h"
> > +#include "hw/arm/armv7m.h"
> > #include "hw/intc/aspeed_vic.h"
> > #include "hw/misc/aspeed_scu.h"
> > #include "hw/adc/aspeed_adc.h"
> > @@ -47,6 +48,7 @@ struct AspeedSoCState {
> > /*< public >*/
> > ARMCPU cpu[ASPEED_CPUS_NUM];
> > A15MPPrivState a7mpcore;
> > + ARMv7MState armv7m;
> > MemoryRegion *dram_mr;
> > MemoryRegion sram;
> > AspeedVICState vic;
> > @@ -72,6 +74,7 @@ struct AspeedSoCState {
> > AspeedSDHCIState emmc;
> > AspeedLPCState lpc;
> > uint32_t uart_default;
> > + Clock *sysclk;
> > };
> >
> > #define TYPE_ASPEED_SOC "aspeed-soc"
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/9] aspeed/smc: Add AST1030 support
2022-03-31 15:59 ` Cédric Le Goater
@ 2022-04-01 1:27 ` Jamin Lin
0 siblings, 0 replies; 16+ messages in thread
From: Jamin Lin @ 2022-04-01 1:27 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Peter Maydell, Troy Lee, Beraldo Leal, Andrew Jeffery,
Alistair Francis, Steven Lee, Philippe Mathieu-Daudé,
Wainer dos Santos Moschetta, open list:All patches CC here,
open list:STM32F205, Joel Stanley, Cleber Rosa
The 03/31/2022 15:59, Cédric Le Goater wrote:
> Hello Jamin,
>
> On 3/31/22 10:15, Jamin Lin wrote:
> > From: Steven Lee <steven_lee@aspeedtech.com>
> >
> > AST1030 spi controller's address decoding unit is 1MB that is identical
> > to ast2600, but fmc address decoding unit is 512kb.
> > Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller.
> > In addition, add ast1030 fmc, spi1, and spi2 class init handler.
> >
> > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
>
> I did a review of this patch, anyhow
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>
> but please drop the ASPEED_SMC_FEATURE_WDT_CONTROL flag which is not
> upstream.
>
> Thanks,
>
> C.
>
>
Sorry, I lost to remove it.
Will fix
> > ---
> > hw/ssi/aspeed_smc.c | 160 ++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 160 insertions(+)
> >
> > diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> > index 48305e1574..81af783729 100644
> > --- a/hw/ssi/aspeed_smc.c
> > +++ b/hw/ssi/aspeed_smc.c
> > @@ -1696,6 +1696,163 @@ static const TypeInfo aspeed_2600_spi2_info = {
> > .class_init = aspeed_2600_spi2_class_init,
> > };
> >
> > +/*
> > + * The FMC Segment Registers of the AST1030 have a 512KB unit.
> > + * Only bits [27:19] are used for decoding.
> > + */
> > +#define AST1030_SEG_ADDR_MASK 0x0ff80000
> > +
> > +static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s,
> > + const AspeedSegments *seg)
> > +{
> > + uint32_t reg = 0;
> > +
> > + /* Disabled segments have a nil register */
> > + if (!seg->size) {
> > + return 0;
> > + }
> > +
> > + reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */
> > + reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */
> > + return reg;
> > +}
> > +
> > +static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s,
> > + uint32_t reg, AspeedSegments *seg)
> > +{
> > + uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK;
> > + uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK;
> > + AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
> > +
> > + if (reg) {
> > + seg->addr = asc->flash_window_base + start_offset;
> > + seg->size = end_offset + (512 * KiB) - start_offset;
> > + } else {
> > + seg->addr = asc->flash_window_base;
> > + seg->size = 0;
> > + }
> > +}
> > +
> > +static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = {
> > + [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
> > + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
> > +};
> > +
> > +static const AspeedSegments aspeed_1030_fmc_segments[] = {
> > + { 0x0, 128 * MiB }, /* start address is readonly */
> > + { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
> > + { 0x0, 0 }, /* disabled */
> > +};
> > +
> > +static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
> > +
> > + dc->desc = "Aspeed 1030 FMC Controller";
> > + asc->r_conf = R_CONF;
> > + asc->r_ce_ctrl = R_CE_CTRL;
> > + asc->r_ctrl0 = R_CTRL0;
> > + asc->r_timings = R_TIMINGS;
> > + asc->nregs_timings = 2;
> > + asc->conf_enable_w0 = CONF_ENABLE_W0;
> > + asc->cs_num_max = 2;
> > + asc->segments = aspeed_1030_fmc_segments;
> > + asc->segment_addr_mask = 0x0ff80ff8;
> > + asc->resets = aspeed_1030_fmc_resets;
> > + asc->flash_window_base = 0x80000000;
> > + asc->flash_window_size = 0x10000000;
> > + asc->features = ASPEED_SMC_FEATURE_DMA |
> > + ASPEED_SMC_FEATURE_WDT_CONTROL;
> > + asc->dma_flash_mask = 0x0FFFFFFC;
> > + asc->dma_dram_mask = 0x000BFFFC;
> > + asc->nregs = ASPEED_SMC_R_MAX;
> > + asc->segment_to_reg = aspeed_1030_smc_segment_to_reg;
> > + asc->reg_to_segment = aspeed_1030_smc_reg_to_segment;
> > + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
> > +}
> > +
> > +static const TypeInfo aspeed_1030_fmc_info = {
> > + .name = "aspeed.fmc-ast1030",
> > + .parent = TYPE_ASPEED_SMC,
> > + .class_init = aspeed_1030_fmc_class_init,
> > +};
> > +
> > +static const AspeedSegments aspeed_1030_spi1_segments[] = {
> > + { 0x0, 128 * MiB }, /* start address is readonly */
> > + { 0x0, 0 }, /* disabled */
> > +};
> > +
> > +static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
> > +
> > + dc->desc = "Aspeed 1030 SPI1 Controller";
> > + asc->r_conf = R_CONF;
> > + asc->r_ce_ctrl = R_CE_CTRL;
> > + asc->r_ctrl0 = R_CTRL0;
> > + asc->r_timings = R_TIMINGS;
> > + asc->nregs_timings = 2;
> > + asc->conf_enable_w0 = CONF_ENABLE_W0;
> > + asc->cs_num_max = 2;
> > + asc->segments = aspeed_1030_spi1_segments;
> > + asc->segment_addr_mask = 0x0ff00ff0;
> > + asc->flash_window_base = 0x90000000;
> > + asc->flash_window_size = 0x10000000;
> > + asc->features = ASPEED_SMC_FEATURE_DMA |
> > + ASPEED_SMC_FEATURE_WDT_CONTROL;
> > + asc->dma_flash_mask = 0x0FFFFFFC;
> > + asc->dma_dram_mask = 0x000BFFFC;
> > + asc->nregs = ASPEED_SMC_R_MAX;
> > + asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
> > + asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
> > + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
> > +}
> > +
> > +static const TypeInfo aspeed_1030_spi1_info = {
> > + .name = "aspeed.spi1-ast1030",
> > + .parent = TYPE_ASPEED_SMC,
> > + .class_init = aspeed_1030_spi1_class_init,
> > +};
> > +static const AspeedSegments aspeed_1030_spi2_segments[] = {
> > + { 0x0, 128 * MiB }, /* start address is readonly */
> > + { 0x0, 0 }, /* disabled */
> > +};
> > +
> > +static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
> > +
> > + dc->desc = "Aspeed 1030 SPI2 Controller";
> > + asc->r_conf = R_CONF;
> > + asc->r_ce_ctrl = R_CE_CTRL;
> > + asc->r_ctrl0 = R_CTRL0;
> > + asc->r_timings = R_TIMINGS;
> > + asc->nregs_timings = 2;
> > + asc->conf_enable_w0 = CONF_ENABLE_W0;
> > + asc->cs_num_max = 2;
> > + asc->segments = aspeed_1030_spi2_segments;
> > + asc->segment_addr_mask = 0x0ff00ff0;
> > + asc->flash_window_base = 0xb0000000;
> > + asc->flash_window_size = 0x10000000;
> > + asc->features = ASPEED_SMC_FEATURE_DMA |
> > + ASPEED_SMC_FEATURE_WDT_CONTROL;
> > + asc->dma_flash_mask = 0x0FFFFFFC;
> > + asc->dma_dram_mask = 0x000BFFFC;
> > + asc->nregs = ASPEED_SMC_R_MAX;
> > + asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
> > + asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
> > + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
> > +}
> > +
> > +static const TypeInfo aspeed_1030_spi2_info = {
> > + .name = "aspeed.spi2-ast1030",
> > + .parent = TYPE_ASPEED_SMC,
> > + .class_init = aspeed_1030_spi2_class_init,
> > +};
> > +
> > static void aspeed_smc_register_types(void)
> > {
> > type_register_static(&aspeed_smc_flash_info);
> > @@ -1709,6 +1866,9 @@ static void aspeed_smc_register_types(void)
> > type_register_static(&aspeed_2600_fmc_info);
> > type_register_static(&aspeed_2600_spi1_info);
> > type_register_static(&aspeed_2600_spi2_info);
> > + type_register_static(&aspeed_1030_fmc_info);
> > + type_register_static(&aspeed_1030_spi1_info);
> > + type_register_static(&aspeed_1030_spi2_info);
> > }
> >
> > type_init(aspeed_smc_register_types)
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-04-01 1:29 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-31 8:15 [PATCH v2 0/9] Add support for AST1030 SoC Jamin Lin
2022-03-31 8:15 ` [PATCH v2 1/9] aspeed/adc: Add AST1030 support Jamin Lin
2022-03-31 8:15 ` [PATCH v2 2/9] aspeed/smc: " Jamin Lin
2022-03-31 15:59 ` Cédric Le Goater
2022-04-01 1:27 ` Jamin Lin
2022-03-31 8:15 ` [PATCH v2 3/9] aspeed/wdt: Fix ast2500/ast2600 default reload value Jamin Lin
2022-03-31 8:15 ` [PATCH v2 4/9] aspeed/wdt: Add AST1030 support Jamin Lin
2022-03-31 8:15 ` [PATCH v2 5/9] aspeed/timer: " Jamin Lin
2022-03-31 8:15 ` [PATCH v2 6/9] aspeed/scu: " Jamin Lin
2022-03-31 8:15 ` [PATCH v2 7/9] aspeed/soc : " Jamin Lin
2022-03-31 11:08 ` Cédric Le Goater
2022-04-01 1:26 ` Jamin Lin
2022-03-31 8:15 ` [PATCH v2 8/9] aspeed: Add an AST1030 eval board Jamin Lin
2022-03-31 11:04 ` Cédric Le Goater
2022-04-01 1:24 ` Jamin Lin
2022-03-31 8:15 ` [PATCH v2 9/9] test/avocado/machine_aspeed.py: Add ast1030 test case Jamin Lin
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