* [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
@ 2018-11-26 6:36 S, Shirish
[not found] ` <1543214171-12460-1-git-send-email-shirish.s-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: S, Shirish @ 2018-11-26 6:36 UTC (permalink / raw)
To: Li, Sun peng (Leo), Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, S, Shirish
[Why]
ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,
that it cannot handle correctly, hence resulting in
several issues like flickering, black lines/flashes and so on.
[How]
These modes are basically high pixel clock ones, hence
limit the same to be advertised to avoid bad user experiences
Signed-off-by: Shirish S <shirish.s@amd.com>
Suggested-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 1b2fe0d..1b8fe99 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(
if (!timing)
return false;
+ /* Limit all modes that have a high pixel clock
+ * which seems to be problematic on dce110
+ * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz
+ * based on the below formula:
+ * refresh rate = pixel clock / (htotal * vtotal)
+ */
+ if (timing->pix_clk_khz > 300000)
+ return false;
+
+
hsync_offset = timing->h_border_right + timing->h_front_porch;
h_sync_start = timing->h_addressable + hsync_offset;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[not found] ` <1543214171-12460-1-git-send-email-shirish.s-5C7GfCeVMHo@public.gmane.org>
@ 2018-11-26 14:15 ` Deucher, Alexander
[not found] ` <BN6PR12MB1809F50687D05789C14E6C61F7D70-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Deucher, Alexander @ 2018-11-26 14:15 UTC (permalink / raw)
To: S, Shirish, Li, Sun peng (Leo), Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 2325 bytes --]
I thought there was a patch to do this already that got sent out a few weeks ago. Basically limit ST/CZ to modes that do not require a retimer. Is an additional patch needed?
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, November 26, 2018 1:36:30 AM
To: Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; S, Shirish
Subject: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[Why]
ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,
that it cannot handle correctly, hence resulting in
several issues like flickering, black lines/flashes and so on.
[How]
These modes are basically high pixel clock ones, hence
limit the same to be advertised to avoid bad user experiences
Signed-off-by: Shirish S <shirish.s-5C7GfCeVMHo@public.gmane.org>
Suggested-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
---
.../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 1b2fe0d..1b8fe99 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(
if (!timing)
return false;
+ /* Limit all modes that have a high pixel clock
+ * which seems to be problematic on dce110
+ * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz
+ * based on the below formula:
+ * refresh rate = pixel clock / (htotal * vtotal)
+ */
+ if (timing->pix_clk_khz > 300000)
+ return false;
+
+
hsync_offset = timing->h_border_right + timing->h_front_porch;
h_sync_start = timing->h_addressable + hsync_offset;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[not found] ` <BN6PR12MB1809F50687D05789C14E6C61F7D70-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-11-27 4:11 ` S, Shirish
[not found] ` <BLUPR12MB0452C3CF56CBB8089FB9D5CBF2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: S, Shirish @ 2018-11-27 4:11 UTC (permalink / raw)
To: Deucher, Alexander, Li, Sun peng (Leo), Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 3162 bytes --]
Thanks Alex, found that patch.
My patch is no more required.
Regards,
Shirish S
From: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, November 26, 2018 7:46 PM
To: S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org>; Li, Sun peng (Leo) <Sunpeng.Li-5C7GfCeVMHo@public.gmane.org>; Wentland, Harry <Harry.Wentland-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
I thought there was a patch to do this already that got sent out a few weeks ago. Basically limit ST/CZ to modes that do not require a retimer. Is an additional patch needed?
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org<mailto:Shirish.S-5C7GfCeVMHo@public.gmane.org>>
Sent: Monday, November 26, 2018 1:36:30 AM
To: Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; S, Shirish
Subject: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[Why]
ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,
that it cannot handle correctly, hence resulting in
several issues like flickering, black lines/flashes and so on.
[How]
These modes are basically high pixel clock ones, hence
limit the same to be advertised to avoid bad user experiences
Signed-off-by: Shirish S <shirish.s-5C7GfCeVMHo@public.gmane.org<mailto:shirish.s-5C7GfCeVMHo@public.gmane.org>>
Suggested-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org<mailto:harry.wentland@amd.com>>
---
.../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 1b2fe0d..1b8fe99 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(
if (!timing)
return false;
+ /* Limit all modes that have a high pixel clock
+ * which seems to be problematic on dce110
+ * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz
+ * based on the below formula:
+ * refresh rate = pixel clock / (htotal * vtotal)
+ */
+ if (timing->pix_clk_khz > 300000)
+ return false;
+
+
hsync_offset = timing->h_border_right + timing->h_front_porch;
h_sync_start = timing->h_addressable + hsync_offset;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[not found] ` <BLUPR12MB0452C3CF56CBB8089FB9D5CBF2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-11-27 8:58 ` S, Shirish
[not found] ` <BLUPR12MB045213B336F6D1D61674CFEFF2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: S, Shirish @ 2018-11-27 8:58 UTC (permalink / raw)
To: Deucher, Alexander, Li, Sun peng (Leo), Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 4054 bytes --]
However, while using Type-C connectors noted that the signal type is actually SIGNAL_TYPE_DISPLAY_PORT and found that the check was missing.
Hence have added the same in https://patchwork.freedesktop.org/patch/264033/
Regards,
Shirish S
From: S, Shirish
Sent: Tuesday, November 27, 2018 9:54 AM
To: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Li, Sun peng (Leo) <Sunpeng.Li-5C7GfCeVMHo@public.gmane.org>; Wentland, Harry <Harry.Wentland-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
Thanks Alex, found that patch.
My patch is no more required.
Regards,
Shirish S
From: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>
Sent: Monday, November 26, 2018 7:46 PM
To: S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org<mailto:Shirish.S-5C7GfCeVMHo@public.gmane.org>>; Li, Sun peng (Leo) <Sunpeng.Li-5C7GfCeVMHo@public.gmane.org<mailto:Sunpeng.Li-5C7GfCeVMHo@public.gmane.org>>; Wentland, Harry <Harry.Wentland-5C7GfCeVMHo@public.gmane.org<mailto:Harry.Wentland-5C7GfCeVMHo@public.gmane.org>>
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
I thought there was a patch to do this already that got sent out a few weeks ago. Basically limit ST/CZ to modes that do not require a retimer. Is an additional patch needed?
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org<mailto:Shirish.S-5C7GfCeVMHo@public.gmane.org>>
Sent: Monday, November 26, 2018 1:36:30 AM
To: Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; S, Shirish
Subject: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[Why]
ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,
that it cannot handle correctly, hence resulting in
several issues like flickering, black lines/flashes and so on.
[How]
These modes are basically high pixel clock ones, hence
limit the same to be advertised to avoid bad user experiences
Signed-off-by: Shirish S <shirish.s-5C7GfCeVMHo@public.gmane.org<mailto:shirish.s-5C7GfCeVMHo@public.gmane.org>>
Suggested-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org<mailto:harry.wentland@amd.com>>
---
.../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 1b2fe0d..1b8fe99 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(
if (!timing)
return false;
+ /* Limit all modes that have a high pixel clock
+ * which seems to be problematic on dce110
+ * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz
+ * based on the below formula:
+ * refresh rate = pixel clock / (htotal * vtotal)
+ */
+ if (timing->pix_clk_khz > 300000)
+ return false;
+
+
hsync_offset = timing->h_border_right + timing->h_front_porch;
h_sync_start = timing->h_addressable + hsync_offset;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[not found] ` <BLUPR12MB045213B336F6D1D61674CFEFF2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-11-27 18:36 ` Deucher, Alexander
[not found] ` <BN6PR12MB1809B7A81F8D2A38C4B85362F7D00-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Deucher, Alexander @ 2018-11-27 18:36 UTC (permalink / raw)
To: S, Shirish, Li, Sun peng (Leo), Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 4528 bytes --]
Is this a DP to HDMI adapter? I think 4k@60 should be valid on DP in general on ST/CZ, but Harry or Leo should comment.
Alex
________________________________
From: S, Shirish
Sent: Tuesday, November 27, 2018 3:58:12 AM
To: Deucher, Alexander; Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
However, while using Type-C connectors noted that the signal type is actually SIGNAL_TYPE_DISPLAY_PORT and found that the check was missing.
Hence have added the same in https://patchwork.freedesktop.org/patch/264033/
Regards,
Shirish S
From: S, Shirish
Sent: Tuesday, November 27, 2018 9:54 AM
To: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Li, Sun peng (Leo) <Sunpeng.Li-5C7GfCeVMHo@public.gmane.org>; Wentland, Harry <Harry.Wentland-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
Thanks Alex, found that patch.
My patch is no more required.
Regards,
Shirish S
From: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>
Sent: Monday, November 26, 2018 7:46 PM
To: S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org<mailto:Shirish.S-5C7GfCeVMHo@public.gmane.org>>; Li, Sun peng (Leo) <Sunpeng.Li-5C7GfCeVMHo@public.gmane.org<mailto:Sunpeng.Li-5C7GfCeVMHo@public.gmane.org>>; Wentland, Harry <Harry.Wentland-5C7GfCeVMHo@public.gmane.org<mailto:Harry.Wentland-5C7GfCeVMHo@public.gmane.org>>
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
I thought there was a patch to do this already that got sent out a few weeks ago. Basically limit ST/CZ to modes that do not require a retimer. Is an additional patch needed?
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org<mailto:Shirish.S-5C7GfCeVMHo@public.gmane.org>>
Sent: Monday, November 26, 2018 1:36:30 AM
To: Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; S, Shirish
Subject: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[Why]
ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,
that it cannot handle correctly, hence resulting in
several issues like flickering, black lines/flashes and so on.
[How]
These modes are basically high pixel clock ones, hence
limit the same to be advertised to avoid bad user experiences
Signed-off-by: Shirish S <shirish.s-5C7GfCeVMHo@public.gmane.org<mailto:shirish.s-5C7GfCeVMHo@public.gmane.org>>
Suggested-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org<mailto:harry.wentland@amd.com>>
---
.../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 1b2fe0d..1b8fe99 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(
if (!timing)
return false;
+ /* Limit all modes that have a high pixel clock
+ * which seems to be problematic on dce110
+ * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz
+ * based on the below formula:
+ * refresh rate = pixel clock / (htotal * vtotal)
+ */
+ if (timing->pix_clk_khz > 300000)
+ return false;
+
+
hsync_offset = timing->h_border_right + timing->h_front_porch;
h_sync_start = timing->h_addressable + hsync_offset;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[not found] ` <BN6PR12MB1809B7A81F8D2A38C4B85362F7D00-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-11-27 18:49 ` S, Shirish
[not found] ` <BLUPR12MB0452CFA936F551D64AA10737F2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: S, Shirish @ 2018-11-27 18:49 UTC (permalink / raw)
To: Li, Sun peng (Leo), Wentland, Harry, Deucher, Alexander
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
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This is for the devices with type-c ports.
Wherein the signal type is same 32 (DISPLAY PORT) for both HDMI and DP monitors connected to the system via type-c dongles/convertors.
Regards,
Shirish S
Get Outlook for Android<https://aka.ms/ghei36>
________________________________
From: Deucher, Alexander
Sent: Wednesday, November 28, 2018 12:06:26 AM
To: S, Shirish; Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
Is this a DP to HDMI adapter? I think 4k@60 should be valid on DP in general on ST/CZ, but Harry or Leo should comment.
Alex
________________________________
From: S, Shirish
Sent: Tuesday, November 27, 2018 3:58:12 AM
To: Deucher, Alexander; Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
However, while using Type-C connectors noted that the signal type is actually SIGNAL_TYPE_DISPLAY_PORT and found that the check was missing.
Hence have added the same in https://patchwork.freedesktop.org/patch/264033/
Regards,
Shirish S
From: S, Shirish
Sent: Tuesday, November 27, 2018 9:54 AM
To: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Li, Sun peng (Leo) <Sunpeng.Li-5C7GfCeVMHo@public.gmane.org>; Wentland, Harry <Harry.Wentland-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
Thanks Alex, found that patch.
My patch is no more required.
Regards,
Shirish S
From: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>
Sent: Monday, November 26, 2018 7:46 PM
To: S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org<mailto:Shirish.S-5C7GfCeVMHo@public.gmane.org>>; Li, Sun peng (Leo) <Sunpeng.Li-5C7GfCeVMHo@public.gmane.org<mailto:Sunpeng.Li-5C7GfCeVMHo@public.gmane.org>>; Wentland, Harry <Harry.Wentland-5C7GfCeVMHo@public.gmane.org<mailto:Harry.Wentland-5C7GfCeVMHo@public.gmane.org>>
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
I thought there was a patch to do this already that got sent out a few weeks ago. Basically limit ST/CZ to modes that do not require a retimer. Is an additional patch needed?
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org<mailto:Shirish.S-5C7GfCeVMHo@public.gmane.org>>
Sent: Monday, November 26, 2018 1:36:30 AM
To: Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; S, Shirish
Subject: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[Why]
ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,
that it cannot handle correctly, hence resulting in
several issues like flickering, black lines/flashes and so on.
[How]
These modes are basically high pixel clock ones, hence
limit the same to be advertised to avoid bad user experiences
Signed-off-by: Shirish S <shirish.s-5C7GfCeVMHo@public.gmane.org<mailto:shirish.s-5C7GfCeVMHo@public.gmane.org>>
Suggested-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org<mailto:harry.wentland@amd.com>>
---
.../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 1b2fe0d..1b8fe99 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(
if (!timing)
return false;
+ /* Limit all modes that have a high pixel clock
+ * which seems to be problematic on dce110
+ * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz
+ * based on the below formula:
+ * refresh rate = pixel clock / (htotal * vtotal)
+ */
+ if (timing->pix_clk_khz > 300000)
+ return false;
+
+
hsync_offset = timing->h_border_right + timing->h_front_porch;
h_sync_start = timing->h_addressable + hsync_offset;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
[not found] ` <BLUPR12MB0452CFA936F551D64AA10737F2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-11-29 19:13 ` Wentland, Harry
0 siblings, 0 replies; 7+ messages in thread
From: Wentland, Harry @ 2018-11-29 19:13 UTC (permalink / raw)
To: S, Shirish, Li, Sun peng (Leo), Deucher, Alexander
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Hersen confirmed 4k60 works fine over DP. The problem here are really just USB-C ports and associated dongles. We've never supported USB-C dongles on CZ/ST before.
Harry
On 2018-11-27 1:49 p.m., S, Shirish wrote:
> This is for the devices with type-c ports.
>
> Wherein the signal type is same 32 (DISPLAY PORT) for both HDMI and DP monitors connected to the system via type-c dongles/convertors.
>
> Regards,
> Shirish S
>
> Get Outlook for Android <https://aka.ms/ghei36>
>
> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> *From:* Deucher, Alexander
> *Sent:* Wednesday, November 28, 2018 12:06:26 AM
> *To:* S, Shirish; Li, Sun peng (Leo); Wentland, Harry
> *Cc:* amd-gfx@lists.freedesktop.org
> *Subject:* Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
>
>
> Is this a DP to HDMI adapter? I think 4k@60 should be valid on DP in general on ST/CZ, but Harry or Leo should comment.
>
>
> Alex
>
> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> *From:* S, Shirish
> *Sent:* Tuesday, November 27, 2018 3:58:12 AM
> *To:* Deucher, Alexander; Li, Sun peng (Leo); Wentland, Harry
> *Cc:* amd-gfx@lists.freedesktop.org
> *Subject:* RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
>
>
> However, while using Type-C connectors noted that the signal type is actually SIGNAL_TYPE_DISPLAY_PORT and found that the check was missing.
>
> Hence have added the same in https://patchwork.freedesktop.org/patch/264033/
>
>
>
> Regards,
>
> Shirish S
>
>
>
> *From:* S, Shirish
> *Sent:* Tuesday, November 27, 2018 9:54 AM
> *To:* Deucher, Alexander <Alexander.Deucher@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>
> *Cc:* amd-gfx@lists.freedesktop.org
> *Subject:* RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
>
>
>
> Thanks Alex, found that patch.
>
> My patch is no more required.
>
>
>
>
>
> Regards,
>
> Shirish S
>
>
>
> *From:* Deucher, Alexander <Alexander.Deucher@amd.com <mailto:Alexander.Deucher@amd.com>>
> *Sent:* Monday, November 26, 2018 7:46 PM
> *To:* S, Shirish <Shirish.S@amd.com <mailto:Shirish.S@amd.com>>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com <mailto:Sunpeng.Li@amd.com>>; Wentland, Harry <Harry.Wentland@amd.com <mailto:Harry.Wentland@amd.com>>
> *Cc:* amd-gfx@lists.freedesktop.org <mailto:amd-gfx@lists.freedesktop.org>
> *Subject:* Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
>
>
>
> I thought there was a patch to do this already that got sent out a few weeks ago. Basically limit ST/CZ to modes that do not require a retimer. Is an additional patch needed?
>
>
>
> Alex
>
> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
>
> *From:*amd-gfx <amd-gfx-bounces@lists.freedesktop.org <mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of S, Shirish <Shirish.S@amd.com <mailto:Shirish.S@amd.com>>
> *Sent:* Monday, November 26, 2018 1:36:30 AM
> *To:* Li, Sun peng (Leo); Wentland, Harry
> *Cc:* amd-gfx@lists.freedesktop.org <mailto:amd-gfx@lists.freedesktop.org>; S, Shirish
> *Subject:* [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ
>
>
>
> [Why]
> ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,
> that it cannot handle correctly, hence resulting in
> several issues like flickering, black lines/flashes and so on.
>
> [How]
> These modes are basically high pixel clock ones, hence
> limit the same to be advertised to avoid bad user experiences
>
> Signed-off-by: Shirish S <shirish.s@amd.com <mailto:shirish.s@amd.com>>
> Suggested-by: Harry Wentland <harry.wentland@amd.com <mailto:harry.wentland@amd.com>>
> ---
> .../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
> index 1b2fe0d..1b8fe99 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
> @@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(
> if (!timing)
> return false;
>
> + /* Limit all modes that have a high pixel clock
> + * which seems to be problematic on dce110
> + * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz
> + * based on the below formula:
> + * refresh rate = pixel clock / (htotal * vtotal)
> + */
> + if (timing->pix_clk_khz > 300000)
> + return false;
> +
> +
> hsync_offset = timing->h_border_right + timing->h_front_porch;
> h_sync_start = timing->h_addressable + hsync_offset;
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org <mailto:amd-gfx@lists.freedesktop.org>
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-11-29 19:13 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-26 6:36 [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ S, Shirish
[not found] ` <1543214171-12460-1-git-send-email-shirish.s-5C7GfCeVMHo@public.gmane.org>
2018-11-26 14:15 ` Deucher, Alexander
[not found] ` <BN6PR12MB1809F50687D05789C14E6C61F7D70-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-11-27 4:11 ` S, Shirish
[not found] ` <BLUPR12MB0452C3CF56CBB8089FB9D5CBF2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-11-27 8:58 ` S, Shirish
[not found] ` <BLUPR12MB045213B336F6D1D61674CFEFF2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-11-27 18:36 ` Deucher, Alexander
[not found] ` <BN6PR12MB1809B7A81F8D2A38C4B85362F7D00-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-11-27 18:49 ` S, Shirish
[not found] ` <BLUPR12MB0452CFA936F551D64AA10737F2D00-7LeqcoF/hwohIaQXubWUmgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-11-29 19:13 ` Wentland, Harry
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