From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH v2 2/8] target/riscv: Define ePMP mseccfg Date: Fri, 9 Apr 2021 08:20:05 -0400 [thread overview] Message-ID: <ff64915c9ea90fe5b234013df538e435154b0d36.1617970729.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1617970729.git.alistair.francis@wdc.com> From: Hou Weiying <weiying_hou@outlook.com> Use address 0x390 and 0x391 for the ePMP CSRs. Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com> Signed-off-by: Hou Weiying <weiying_hou@outlook.com> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <SG2PR02MB2634D85E5DF0C2BB540AE1BB93450@SG2PR02MB2634.apcprd02.prod.outlook.com> [ Changes by AF: - Tidy up commit message ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- target/riscv/cpu_bits.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8549d77b4f..24d89939a0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -220,6 +220,9 @@ #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b +/* Enhanced Physical Memory Protection (ePMP) */ +#define CSR_MSECCFG 0x390 +#define CSR_MSECCFGH 0x391 /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 -- 2.31.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v2 2/8] target/riscv: Define ePMP mseccfg Date: Fri, 9 Apr 2021 08:20:05 -0400 [thread overview] Message-ID: <ff64915c9ea90fe5b234013df538e435154b0d36.1617970729.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1617970729.git.alistair.francis@wdc.com> From: Hou Weiying <weiying_hou@outlook.com> Use address 0x390 and 0x391 for the ePMP CSRs. Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com> Signed-off-by: Hou Weiying <weiying_hou@outlook.com> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <SG2PR02MB2634D85E5DF0C2BB540AE1BB93450@SG2PR02MB2634.apcprd02.prod.outlook.com> [ Changes by AF: - Tidy up commit message ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- target/riscv/cpu_bits.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8549d77b4f..24d89939a0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -220,6 +220,9 @@ #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b +/* Enhanced Physical Memory Protection (ePMP) */ +#define CSR_MSECCFG 0x390 +#define CSR_MSECCFGH 0x391 /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 -- 2.31.0
next prev parent reply other threads:[~2021-04-09 12:28 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-09 12:19 [PATCH v2 0/8] RISC-V: Add support for ePMP v0.9.1 Alistair Francis 2021-04-09 12:19 ` Alistair Francis 2021-04-09 12:19 ` [PATCH v2 1/8] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis 2021-04-09 12:19 ` Alistair Francis 2021-04-09 12:20 ` Alistair Francis [this message] 2021-04-09 12:20 ` [PATCH v2 2/8] target/riscv: Define ePMP mseccfg Alistair Francis 2021-04-09 12:20 ` [PATCH v2 3/8] target/riscv: Add the ePMP feature Alistair Francis 2021-04-09 12:20 ` Alistair Francis 2021-04-09 12:20 ` [PATCH v2 4/8] target/riscv: Add ePMP CSR access functions Alistair Francis 2021-04-09 12:20 ` Alistair Francis 2021-04-09 12:20 ` [PATCH v2 5/8] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis 2021-04-09 12:20 ` Alistair Francis 2021-04-09 14:33 ` Bin Meng 2021-04-09 14:33 ` Bin Meng 2021-04-11 4:06 ` Alistair Francis 2021-04-11 4:06 ` Alistair Francis 2021-04-09 12:20 ` [PATCH v2 6/8] target/riscv: Add a config option for ePMP Alistair Francis 2021-04-09 12:20 ` Alistair Francis 2021-04-09 12:20 ` [PATCH v2 7/8] target/riscv/pmp: Remove outdated comment Alistair Francis 2021-04-09 12:20 ` Alistair Francis 2021-04-09 12:20 ` [PATCH v2 8/8] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis 2021-04-09 12:20 ` Alistair Francis
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=ff64915c9ea90fe5b234013df538e435154b0d36.1617970729.git.alistair.francis@wdc.com \ --to=alistair.francis@wdc.com \ --cc=alistair23@gmail.com \ --cc=bmeng.cn@gmail.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.