[PATCH 0/7] K2G: Add QSPI support

[PATCH 0/7] K2G: Add QSPI support

[Vignesh R]

This series adds support for Cadence QSPI for 66AK2G SoC. The first
three patches enhance the cadence-quadspi driver to support loopback
clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
DT nodes and enable the driver in defconfig.

Tested on 66AK2G GP and ICE boards.

Vignesh R (7):
  mtd: spi-nor: cadence-quadspi: add a delay in write sequence
  mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
    circuit
  mtd: spi-nor: cadence-quadspi: Add runtime PM support
  ARM: dts: keystone-k2g: Add QSPI DT entry
  ARM: dts: keystone-k2g-evm: Add QSPI node
  ARM: dts: keystone-k2g-ice: Add QSPI node
  ARM: configs: keystone: Enable Cadence QSPI driver

 .../devicetree/bindings/mtd/cadence-quadspi.txt    |  4 ++
 arch/arm/boot/dts/keystone-k2g-evm.dts             | 69 ++++++++++++++++++++++
 arch/arm/boot/dts/keystone-k2g-ice.dts             | 69 ++++++++++++++++++++++
 arch/arm/boot/dts/keystone-k2g.dtsi                | 15 +++++
 arch/arm/configs/keystone_defconfig                |  1 +
 drivers/mtd/spi-nor/cadence-quadspi.c              | 32 +++++++++-
 6 files changed, 188 insertions(+), 2 deletions(-)

-- 
2.13.3

[PATCH 0/7] K2G: Add QSPI support

[Vignesh R]

This series adds support for Cadence QSPI for 66AK2G SoC. The first
three patches enhance the cadence-quadspi driver to support loopback
clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
DT nodes and enable the driver in defconfig.

Tested on 66AK2G GP and ICE boards.

Vignesh R (7):
  mtd: spi-nor: cadence-quadspi: add a delay in write sequence
  mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
    circuit
  mtd: spi-nor: cadence-quadspi: Add runtime PM support
  ARM: dts: keystone-k2g: Add QSPI DT entry
  ARM: dts: keystone-k2g-evm: Add QSPI node
  ARM: dts: keystone-k2g-ice: Add QSPI node
  ARM: configs: keystone: Enable Cadence QSPI driver

 .../devicetree/bindings/mtd/cadence-quadspi.txt    |  4 ++
 arch/arm/boot/dts/keystone-k2g-evm.dts             | 69 ++++++++++++++++++++++
 arch/arm/boot/dts/keystone-k2g-ice.dts             | 69 ++++++++++++++++++++++
 arch/arm/boot/dts/keystone-k2g.dtsi                | 15 +++++
 arch/arm/configs/keystone_defconfig                |  1 +
 drivers/mtd/spi-nor/cadence-quadspi.c              | 32 +++++++++-
 6 files changed, 188 insertions(+), 2 deletions(-)

-- 
2.13.3

[PATCH 0/7] K2G: Add QSPI support

[Vignesh R]

This series adds support for Cadence QSPI for 66AK2G SoC. The first
three patches enhance the cadence-quadspi driver to support loopback
clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
DT nodes and enable the driver in defconfig.

Tested on 66AK2G GP and ICE boards.

Vignesh R (7):
  mtd: spi-nor: cadence-quadspi: add a delay in write sequence
  mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
    circuit
  mtd: spi-nor: cadence-quadspi: Add runtime PM support
  ARM: dts: keystone-k2g: Add QSPI DT entry
  ARM: dts: keystone-k2g-evm: Add QSPI node
  ARM: dts: keystone-k2g-ice: Add QSPI node
  ARM: configs: keystone: Enable Cadence QSPI driver

 .../devicetree/bindings/mtd/cadence-quadspi.txt    |  4 ++
 arch/arm/boot/dts/keystone-k2g-evm.dts             | 69 ++++++++++++++++++++++
 arch/arm/boot/dts/keystone-k2g-ice.dts             | 69 ++++++++++++++++++++++
 arch/arm/boot/dts/keystone-k2g.dtsi                | 15 +++++
 arch/arm/configs/keystone_defconfig                |  1 +
 drivers/mtd/spi-nor/cadence-quadspi.c              | 32 +++++++++-
 6 files changed, 188 insertions(+), 2 deletions(-)

-- 
2.13.3

[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Add a new compatible to handle the couple of
cycles of delay required in the indirect write sequence, since this
delay is specific to TI 66AK2G SoC.

[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
 drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index f248056da24c..fdd511a83511 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible : Should be "cdns,qspi-nor".
+	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
 - reg : Contains two entries, each of which is a tuple consisting of a
 	physical address and length. The first entry is the address and
 	length of the controller register set. The second entry is the
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 53c7d8e0327a..94571590371d 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -76,6 +76,7 @@ struct cqspi_st {
 	u32			fifo_depth;
 	u32			fifo_width;
 	u32			trigger_address;
+	u32			wr_delay;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
 };
 
@@ -608,6 +609,14 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
 	reinit_completion(&cqspi->transfer_complete);
 	writel(CQSPI_REG_INDIRECTWR_START_MASK,
 	       reg_base + CQSPI_REG_INDIRECTWR);
+	/*
+	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
+	 * Controller programming sequence, couple of cycles of
+	 * QSPI_REF_CLK delay is required for the above bit to
+	 * be internally synchronized by the QSPI module. Provide 5
+	 * cycles of delay.
+	 */
+	ndelay(cqspi->wr_delay);
 
 	while (remaining > 0) {
 		write_bytes = remaining > page_size ? page_size : remaining;
@@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
 	}
 
 	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
+	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
+		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
+						   cqspi->master_ref_clk_hz);
 
 	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
 			       pdev->name, cqspi);
@@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
 
 static const struct of_device_id cqspi_dt_ids[] = {
 	{.compatible = "cdns,qspi-nor",},
+	{.compatible = "ti,k2g-qspi",},
 	{ /* end of table */ }
 };
 
-- 
2.13.3

[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Add a new compatible to handle the couple of
cycles of delay required in the indirect write sequence, since this
delay is specific to TI 66AK2G SoC.

[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
 drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index f248056da24c..fdd511a83511 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible : Should be "cdns,qspi-nor".
+	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
 - reg : Contains two entries, each of which is a tuple consisting of a
 	physical address and length. The first entry is the address and
 	length of the controller register set. The second entry is the
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 53c7d8e0327a..94571590371d 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -76,6 +76,7 @@ struct cqspi_st {
 	u32			fifo_depth;
 	u32			fifo_width;
 	u32			trigger_address;
+	u32			wr_delay;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
 };
 
@@ -608,6 +609,14 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
 	reinit_completion(&cqspi->transfer_complete);
 	writel(CQSPI_REG_INDIRECTWR_START_MASK,
 	       reg_base + CQSPI_REG_INDIRECTWR);
+	/*
+	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
+	 * Controller programming sequence, couple of cycles of
+	 * QSPI_REF_CLK delay is required for the above bit to
+	 * be internally synchronized by the QSPI module. Provide 5
+	 * cycles of delay.
+	 */
+	ndelay(cqspi->wr_delay);
 
 	while (remaining > 0) {
 		write_bytes = remaining > page_size ? page_size : remaining;
@@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
 	}
 
 	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
+	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
+		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
+						   cqspi->master_ref_clk_hz);
 
 	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
 			       pdev->name, cqspi);
@@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
 
 static const struct of_device_id cqspi_dt_ids[] = {
 	{.compatible = "cdns,qspi-nor",},
+	{.compatible = "ti,k2g-qspi",},
 	{ /* end of table */ }
 };
 
-- 
2.13.3

[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Add a new compatible to handle the couple of
cycles of delay required in the indirect write sequence, since this
delay is specific to TI 66AK2G SoC.

[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
 drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index f248056da24c..fdd511a83511 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible : Should be "cdns,qspi-nor".
+	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
 - reg : Contains two entries, each of which is a tuple consisting of a
 	physical address and length. The first entry is the address and
 	length of the controller register set. The second entry is the
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 53c7d8e0327a..94571590371d 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -76,6 +76,7 @@ struct cqspi_st {
 	u32			fifo_depth;
 	u32			fifo_width;
 	u32			trigger_address;
+	u32			wr_delay;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
 };
 
@@ -608,6 +609,14 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
 	reinit_completion(&cqspi->transfer_complete);
 	writel(CQSPI_REG_INDIRECTWR_START_MASK,
 	       reg_base + CQSPI_REG_INDIRECTWR);
+	/*
+	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
+	 * Controller programming sequence, couple of cycles of
+	 * QSPI_REF_CLK delay is required for the above bit to
+	 * be internally synchronized by the QSPI module. Provide 5
+	 * cycles of delay.
+	 */
+	ndelay(cqspi->wr_delay);
 
 	while (remaining > 0) {
 		write_bytes = remaining > page_size ? page_size : remaining;
@@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
 	}
 
 	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
+	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
+		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
+						   cqspi->master_ref_clk_hz);
 
 	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
 			       pdev->name, cqspi);
@@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
 
 static const struct of_device_id cqspi_dt_ids[] = {
 	{.compatible = "cdns,qspi-nor",},
+	{.compatible = "ti,k2g-qspi",},
 	{ /* end of table */ }
 };
 
-- 
2.13.3

[PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Vignesh R]

Cadence QSPI IP has a adapted loopback circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loopback circuit
using QSPI return clock helps to increase data valid window.

Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
for boards which do have QSPI return clock provided.
This patch also modifies cqspi_readdata_capture() function's bypass
parameter to bool to match how its used in the function.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
 drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index fdd511a83511..6cc7d58ce7f6 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -15,6 +15,9 @@ Required properties:
 
 Optional properties:
 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+  the read data rather than the QSPI clock. Make sure that QSPI return
+  clock is populated on the board before using this property.
 
 Optional subnodes:
 Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 94571590371d..297c86a2d4a7 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -75,6 +75,7 @@ struct cqspi_st {
 	bool			is_decoded_cs;
 	u32			fifo_depth;
 	u32			fifo_width;
+	bool			rclk_en;
 	u32			trigger_address;
 	u32			wr_delay;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
@@ -784,7 +785,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 }
 
 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
-				   const unsigned int bypass,
+				   const bool bypass,
 				   const unsigned int delay)
 {
 	void __iomem *reg_base = cqspi->iobase;
@@ -848,7 +849,8 @@ static void cqspi_configure(struct spi_nor *nor)
 		cqspi->sclk = sclk;
 		cqspi_config_baudrate_div(cqspi);
 		cqspi_delay(nor);
-		cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
+		cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
+				       f_pdata->read_delay);
 	}
 
 	if (switch_cs || switch_ck)
@@ -1045,6 +1047,8 @@ static int cqspi_of_get_pdata(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
+
 	return 0;
 }
 
-- 
2.13.3

[PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Vignesh R]

Cadence QSPI IP has a adapted loopback circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loopback circuit
using QSPI return clock helps to increase data valid window.

Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
for boards which do have QSPI return clock provided.
This patch also modifies cqspi_readdata_capture() function's bypass
parameter to bool to match how its used in the function.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
 drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index fdd511a83511..6cc7d58ce7f6 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -15,6 +15,9 @@ Required properties:
 
 Optional properties:
 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+  the read data rather than the QSPI clock. Make sure that QSPI return
+  clock is populated on the board before using this property.
 
 Optional subnodes:
 Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 94571590371d..297c86a2d4a7 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -75,6 +75,7 @@ struct cqspi_st {
 	bool			is_decoded_cs;
 	u32			fifo_depth;
 	u32			fifo_width;
+	bool			rclk_en;
 	u32			trigger_address;
 	u32			wr_delay;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
@@ -784,7 +785,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 }
 
 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
-				   const unsigned int bypass,
+				   const bool bypass,
 				   const unsigned int delay)
 {
 	void __iomem *reg_base = cqspi->iobase;
@@ -848,7 +849,8 @@ static void cqspi_configure(struct spi_nor *nor)
 		cqspi->sclk = sclk;
 		cqspi_config_baudrate_div(cqspi);
 		cqspi_delay(nor);
-		cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
+		cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
+				       f_pdata->read_delay);
 	}
 
 	if (switch_cs || switch_ck)
@@ -1045,6 +1047,8 @@ static int cqspi_of_get_pdata(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
+
 	return 0;
 }
 
-- 
2.13.3

[PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Vignesh R]

Cadence QSPI IP has a adapted loopback circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loopback circuit
using QSPI return clock helps to increase data valid window.

Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
for boards which do have QSPI return clock provided.
This patch also modifies cqspi_readdata_capture() function's bypass
parameter to bool to match how its used in the function.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
 drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index fdd511a83511..6cc7d58ce7f6 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -15,6 +15,9 @@ Required properties:
 
 Optional properties:
 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+  the read data rather than the QSPI clock. Make sure that QSPI return
+  clock is populated on the board before using this property.
 
 Optional subnodes:
 Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 94571590371d..297c86a2d4a7 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -75,6 +75,7 @@ struct cqspi_st {
 	bool			is_decoded_cs;
 	u32			fifo_depth;
 	u32			fifo_width;
+	bool			rclk_en;
 	u32			trigger_address;
 	u32			wr_delay;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
@@ -784,7 +785,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 }
 
 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
-				   const unsigned int bypass,
+				   const bool bypass,
 				   const unsigned int delay)
 {
 	void __iomem *reg_base = cqspi->iobase;
@@ -848,7 +849,8 @@ static void cqspi_configure(struct spi_nor *nor)
 		cqspi->sclk = sclk;
 		cqspi_config_baudrate_div(cqspi);
 		cqspi_delay(nor);
-		cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
+		cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
+				       f_pdata->read_delay);
 	}
 
 	if (switch_cs || switch_ck)
@@ -1045,6 +1047,8 @@ static int cqspi_of_get_pdata(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
+
 	return 0;
 }
 
-- 
2.13.3

[PATCH 3/7] mtd: spi-nor: cadence-quadspi: Add runtime PM support

[Vignesh R]

Add pm_runtime* calls to cadence-quadspi driver. This is required to
switch on QSPI power domain on TI 66AK2G SoC during probe.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 297c86a2d4a7..1e432916e00b 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -31,6 +31,7 @@
 #include <linux/of_device.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/sched.h>
 #include <linux/spi/spi.h>
 #include <linux/timer.h>
@@ -1219,6 +1220,13 @@ static int cqspi_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(&pdev->dev);
+		return ret;
+	}
+
 	ret = clk_prepare_enable(cqspi->clk);
 	if (ret) {
 		dev_err(dev, "Cannot enable QSPI clock.\n");
@@ -1269,6 +1277,9 @@ static int cqspi_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(cqspi->clk);
 
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+
 	return 0;
 }
 
-- 
2.13.3

[PATCH 3/7] mtd: spi-nor: cadence-quadspi: Add runtime PM support

[Vignesh R]

Add pm_runtime* calls to cadence-quadspi driver. This is required to
switch on QSPI power domain on TI 66AK2G SoC during probe.

Signed-off-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
---
 drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 297c86a2d4a7..1e432916e00b 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -31,6 +31,7 @@
 #include <linux/of_device.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/sched.h>
 #include <linux/spi/spi.h>
 #include <linux/timer.h>
@@ -1219,6 +1220,13 @@ static int cqspi_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(&pdev->dev);
+		return ret;
+	}
+
 	ret = clk_prepare_enable(cqspi->clk);
 	if (ret) {
 		dev_err(dev, "Cannot enable QSPI clock.\n");
@@ -1269,6 +1277,9 @@ static int cqspi_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(cqspi->clk);
 
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+
 	return 0;
 }
 
-- 
2.13.3

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[PATCH 3/7] mtd: spi-nor: cadence-quadspi: Add runtime PM support

[Vignesh R]

Add pm_runtime* calls to cadence-quadspi driver. This is required to
switch on QSPI power domain on TI 66AK2G SoC during probe.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 297c86a2d4a7..1e432916e00b 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -31,6 +31,7 @@
 #include <linux/of_device.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/sched.h>
 #include <linux/spi/spi.h>
 #include <linux/timer.h>
@@ -1219,6 +1220,13 @@ static int cqspi_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
+	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (ret < 0) {
+		pm_runtime_put_noidle(&pdev->dev);
+		return ret;
+	}
+
 	ret = clk_prepare_enable(cqspi->clk);
 	if (ret) {
 		dev_err(dev, "Cannot enable QSPI clock.\n");
@@ -1269,6 +1277,9 @@ static int cqspi_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(cqspi->clk);
 
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+
 	return 0;
 }
 
-- 
2.13.3

[PATCH 4/7] ARM: dts: keystone-k2g: Add QSPI DT entry

[Vignesh R]

Add DT node for Cadence QSPI IP present in 66AK2G SoC.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/keystone-k2g.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index bf4d1fa30840..95327aabfaa4 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -168,5 +168,20 @@
 				#reset-cells = <2>;
 			};
 		};
+
+		qspi: qspi@2940000 {
+			compatible = "ti,k2g-qspi", "cdns,qspi-nor";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x02940000 0x1000>,
+			      <0x24000000 0x4000000>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x24000000>;
+			clocks = <&k2g_clks 0x43 0x0>;
+			power-domains = <&k2g_pds 0x43>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.13.3

[PATCH 4/7] ARM: dts: keystone-k2g: Add QSPI DT entry

[Vignesh R]

Add DT node for Cadence QSPI IP present in 66AK2G SoC.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/keystone-k2g.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index bf4d1fa30840..95327aabfaa4 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -168,5 +168,20 @@
 				#reset-cells = <2>;
 			};
 		};
+
+		qspi: qspi@2940000 {
+			compatible = "ti,k2g-qspi", "cdns,qspi-nor";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x02940000 0x1000>,
+			      <0x24000000 0x4000000>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x24000000>;
+			clocks = <&k2g_clks 0x43 0x0>;
+			power-domains = <&k2g_pds 0x43>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.13.3

[PATCH 4/7] ARM: dts: keystone-k2g: Add QSPI DT entry

[Vignesh R]

Add DT node for Cadence QSPI IP present in 66AK2G SoC.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/keystone-k2g.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index bf4d1fa30840..95327aabfaa4 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -168,5 +168,20 @@
 				#reset-cells = <2>;
 			};
 		};
+
+		qspi: qspi at 2940000 {
+			compatible = "ti,k2g-qspi", "cdns,qspi-nor";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x02940000 0x1000>,
+			      <0x24000000 0x4000000>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x24000000>;
+			clocks = <&k2g_clks 0x43 0x0>;
+			power-domains = <&k2g_pds 0x43>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.13.3

[PATCH 5/7] ARM: dts: keystone-k2g-evm: Add QSPI node

[Vignesh R]

66AK2G EVM has a s25fl512s flash connected to QSPI CS0. Add pinmux for
QSPI and DT entries for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/keystone-k2g-evm.dts | 69 ++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index 61883cb969d2..55d632977e8f 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -34,6 +34,18 @@
 			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
 		>;
 	};
+
+	qspi_pins: pinmux_qspi_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
+			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
+			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
+			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
+			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
+			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
+			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
+		>;
+	};
 };
 
 &uart0 {
@@ -41,3 +53,60 @@
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_pins>;
+	cdns,rclk-en;
+	status = "okay";
+
+	flash0: m25p80@0 {
+		compatible = "s25fl512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <96000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cdns,read-delay = <5>;
+		cdns,tshsl-ns = <500>;
+		cdns,tsd2d-ns = <500>;
+		cdns,tchsh-ns = <119>;
+		cdns,tslch-ns = <119>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "QSPI.u-boot";
+				reg = <0x00000000 0x00100000>;
+			};
+			partition@100000 {
+				label = "QSPI.u-boot-env";
+				reg = <0x00100000 0x00040000>;
+			};
+			partition@140000 {
+				label = "QSPI.skern";
+				reg = <0x00140000 0x0040000>;
+			};
+			partition@180000 {
+				label = "QSPI.sci-firmware";
+				reg = <0x00180000 0x0040000>;
+			};
+			partition@1c0000 {
+				label = "QSPI.kernel";
+				reg = <0x001c0000 0x0800000>;
+			};
+			partition@9c0000 {
+				label = "QSPI.u-boot-spl-os";
+				reg = <0x009c0000 0x0040000>;
+			};
+			partition@a00000 {
+				label = "QSPI.file-system";
+				reg = <0x00a00000 0x3600000>;
+			};
+		};
+	};
+};
-- 
2.13.3

[PATCH 5/7] ARM: dts: keystone-k2g-evm: Add QSPI node

[Vignesh R]

66AK2G EVM has a s25fl512s flash connected to QSPI CS0. Add pinmux for
QSPI and DT entries for the same.

Signed-off-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/keystone-k2g-evm.dts | 69 ++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index 61883cb969d2..55d632977e8f 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -34,6 +34,18 @@
 			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
 		>;
 	};
+
+	qspi_pins: pinmux_qspi_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
+			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
+			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
+			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
+			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
+			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
+			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
+		>;
+	};
 };
 
 &uart0 {
@@ -41,3 +53,60 @@
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_pins>;
+	cdns,rclk-en;
+	status = "okay";
+
+	flash0: m25p80@0 {
+		compatible = "s25fl512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <96000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cdns,read-delay = <5>;
+		cdns,tshsl-ns = <500>;
+		cdns,tsd2d-ns = <500>;
+		cdns,tchsh-ns = <119>;
+		cdns,tslch-ns = <119>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "QSPI.u-boot";
+				reg = <0x00000000 0x00100000>;
+			};
+			partition@100000 {
+				label = "QSPI.u-boot-env";
+				reg = <0x00100000 0x00040000>;
+			};
+			partition@140000 {
+				label = "QSPI.skern";
+				reg = <0x00140000 0x0040000>;
+			};
+			partition@180000 {
+				label = "QSPI.sci-firmware";
+				reg = <0x00180000 0x0040000>;
+			};
+			partition@1c0000 {
+				label = "QSPI.kernel";
+				reg = <0x001c0000 0x0800000>;
+			};
+			partition@9c0000 {
+				label = "QSPI.u-boot-spl-os";
+				reg = <0x009c0000 0x0040000>;
+			};
+			partition@a00000 {
+				label = "QSPI.file-system";
+				reg = <0x00a00000 0x3600000>;
+			};
+		};
+	};
+};
-- 
2.13.3

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH 5/7] ARM: dts: keystone-k2g-evm: Add QSPI node

[Vignesh R]

66AK2G EVM has a s25fl512s flash connected to QSPI CS0. Add pinmux for
QSPI and DT entries for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/keystone-k2g-evm.dts | 69 ++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index 61883cb969d2..55d632977e8f 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -34,6 +34,18 @@
 			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
 		>;
 	};
+
+	qspi_pins: pinmux_qspi_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
+			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
+			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
+			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
+			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
+			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
+			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
+		>;
+	};
 };
 
 &uart0 {
@@ -41,3 +53,60 @@
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_pins>;
+	cdns,rclk-en;
+	status = "okay";
+
+	flash0: m25p80 at 0 {
+		compatible = "s25fl512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <96000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cdns,read-delay = <5>;
+		cdns,tshsl-ns = <500>;
+		cdns,tsd2d-ns = <500>;
+		cdns,tchsh-ns = <119>;
+		cdns,tslch-ns = <119>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition at 0 {
+				label = "QSPI.u-boot";
+				reg = <0x00000000 0x00100000>;
+			};
+			partition at 100000 {
+				label = "QSPI.u-boot-env";
+				reg = <0x00100000 0x00040000>;
+			};
+			partition at 140000 {
+				label = "QSPI.skern";
+				reg = <0x00140000 0x0040000>;
+			};
+			partition at 180000 {
+				label = "QSPI.sci-firmware";
+				reg = <0x00180000 0x0040000>;
+			};
+			partition at 1c0000 {
+				label = "QSPI.kernel";
+				reg = <0x001c0000 0x0800000>;
+			};
+			partition at 9c0000 {
+				label = "QSPI.u-boot-spl-os";
+				reg = <0x009c0000 0x0040000>;
+			};
+			partition at a00000 {
+				label = "QSPI.file-system";
+				reg = <0x00a00000 0x3600000>;
+			};
+		};
+	};
+};
-- 
2.13.3

[PATCH 6/7] ARM: dts: keystone-k2g-ice: Add QSPI node

[Vignesh R]

66AK2G ICE board has a s25fl256s1 flash connected to QSPI CS0. Add
pinmux and DT entries for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/keystone-k2g-ice.dts | 69 ++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts
index d820d37b5148..075c3a605c8b 100644
--- a/arch/arm/boot/dts/keystone-k2g-ice.dts
+++ b/arch/arm/boot/dts/keystone-k2g-ice.dts
@@ -26,6 +26,18 @@
 			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
 		>;
 	};
+
+	qspi_pins: pinmux_qspi_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
+			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
+			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
+			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
+			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
+			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
+			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
+		>;
+	};
 };
 
 &uart0 {
@@ -33,3 +45,60 @@
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_pins>;
+	cdns,rclk-en;
+	status = "okay";
+
+	flash0: m25p80@0 {
+		compatible = "s25fl256s1", "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <96000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cdns,read-delay = <5>;
+		cdns,tshsl-ns = <500>;
+		cdns,tsd2d-ns = <500>;
+		cdns,tchsh-ns = <119>;
+		cdns,tslch-ns = <119>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "QSPI.u-boot";
+				reg = <0x00000000 0x00100000>;
+			};
+			partition@100000 {
+				label = "QSPI.u-boot-env";
+				reg = <0x00100000 0x00040000>;
+			};
+			partition@140000 {
+				label = "QSPI.skern";
+				reg = <0x00140000 0x0040000>;
+			};
+			partition@180000 {
+				label = "QSPI.sci-firmware";
+				reg = <0x00180000 0x0040000>;
+			};
+			partition@1c0000 {
+				label = "QSPI.kernel";
+				reg = <0x001c0000 0x0800000>;
+			};
+			partition@9c0000 {
+				label = "QSPI.u-boot-spl-os";
+				reg = <0x009c0000 0x0040000>;
+			};
+			partition@a00000 {
+				label = "QSPI.file-system";
+				reg = <0x00a00000 0x1600000>;
+			};
+		};
+	};
+};
-- 
2.13.3

[PATCH 6/7] ARM: dts: keystone-k2g-ice: Add QSPI node

[Vignesh R]

66AK2G ICE board has a s25fl256s1 flash connected to QSPI CS0. Add
pinmux and DT entries for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/keystone-k2g-ice.dts | 69 ++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts
index d820d37b5148..075c3a605c8b 100644
--- a/arch/arm/boot/dts/keystone-k2g-ice.dts
+++ b/arch/arm/boot/dts/keystone-k2g-ice.dts
@@ -26,6 +26,18 @@
 			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
 		>;
 	};
+
+	qspi_pins: pinmux_qspi_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
+			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
+			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
+			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
+			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
+			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
+			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
+		>;
+	};
 };
 
 &uart0 {
@@ -33,3 +45,60 @@
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_pins>;
+	cdns,rclk-en;
+	status = "okay";
+
+	flash0: m25p80@0 {
+		compatible = "s25fl256s1", "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <96000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cdns,read-delay = <5>;
+		cdns,tshsl-ns = <500>;
+		cdns,tsd2d-ns = <500>;
+		cdns,tchsh-ns = <119>;
+		cdns,tslch-ns = <119>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "QSPI.u-boot";
+				reg = <0x00000000 0x00100000>;
+			};
+			partition@100000 {
+				label = "QSPI.u-boot-env";
+				reg = <0x00100000 0x00040000>;
+			};
+			partition@140000 {
+				label = "QSPI.skern";
+				reg = <0x00140000 0x0040000>;
+			};
+			partition@180000 {
+				label = "QSPI.sci-firmware";
+				reg = <0x00180000 0x0040000>;
+			};
+			partition@1c0000 {
+				label = "QSPI.kernel";
+				reg = <0x001c0000 0x0800000>;
+			};
+			partition@9c0000 {
+				label = "QSPI.u-boot-spl-os";
+				reg = <0x009c0000 0x0040000>;
+			};
+			partition@a00000 {
+				label = "QSPI.file-system";
+				reg = <0x00a00000 0x1600000>;
+			};
+		};
+	};
+};
-- 
2.13.3

[PATCH 6/7] ARM: dts: keystone-k2g-ice: Add QSPI node

[Vignesh R]

66AK2G ICE board has a s25fl256s1 flash connected to QSPI CS0. Add
pinmux and DT entries for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/boot/dts/keystone-k2g-ice.dts | 69 ++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts
index d820d37b5148..075c3a605c8b 100644
--- a/arch/arm/boot/dts/keystone-k2g-ice.dts
+++ b/arch/arm/boot/dts/keystone-k2g-ice.dts
@@ -26,6 +26,18 @@
 			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
 		>;
 	};
+
+	qspi_pins: pinmux_qspi_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
+			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
+			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
+			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
+			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
+			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
+			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
+		>;
+	};
 };
 
 &uart0 {
@@ -33,3 +45,60 @@
 	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_pins>;
+	cdns,rclk-en;
+	status = "okay";
+
+	flash0: m25p80 at 0 {
+		compatible = "s25fl256s1", "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <96000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cdns,read-delay = <5>;
+		cdns,tshsl-ns = <500>;
+		cdns,tsd2d-ns = <500>;
+		cdns,tchsh-ns = <119>;
+		cdns,tslch-ns = <119>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition at 0 {
+				label = "QSPI.u-boot";
+				reg = <0x00000000 0x00100000>;
+			};
+			partition at 100000 {
+				label = "QSPI.u-boot-env";
+				reg = <0x00100000 0x00040000>;
+			};
+			partition at 140000 {
+				label = "QSPI.skern";
+				reg = <0x00140000 0x0040000>;
+			};
+			partition at 180000 {
+				label = "QSPI.sci-firmware";
+				reg = <0x00180000 0x0040000>;
+			};
+			partition at 1c0000 {
+				label = "QSPI.kernel";
+				reg = <0x001c0000 0x0800000>;
+			};
+			partition at 9c0000 {
+				label = "QSPI.u-boot-spl-os";
+				reg = <0x009c0000 0x0040000>;
+			};
+			partition at a00000 {
+				label = "QSPI.file-system";
+				reg = <0x00a00000 0x1600000>;
+			};
+		};
+	};
+};
-- 
2.13.3

[PATCH 7/7] ARM: configs: keystone: Enable Cadence QSPI driver

[Vignesh R]

66AK2G SoC has a Cadence QSPI IP. Therefore, enable cadence-quadspi
driver as part of keystone_defconfig. Since, QSPI flash can be used to
for root filesystem, built it into the kernel instead of module.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/configs/keystone_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index d47ea43d097e..4c8abf3c1ab1 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -124,6 +124,7 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_DAVINCI=y
 CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_SRAM=y
-- 
2.13.3

[PATCH 7/7] ARM: configs: keystone: Enable Cadence QSPI driver

[Vignesh R]

66AK2G SoC has a Cadence QSPI IP. Therefore, enable cadence-quadspi
driver as part of keystone_defconfig. Since, QSPI flash can be used to
for root filesystem, built it into the kernel instead of module.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/configs/keystone_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index d47ea43d097e..4c8abf3c1ab1 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -124,6 +124,7 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_DAVINCI=y
 CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_SRAM=y
-- 
2.13.3

[PATCH 7/7] ARM: configs: keystone: Enable Cadence QSPI driver

[Vignesh R]

66AK2G SoC has a Cadence QSPI IP. Therefore, enable cadence-quadspi
driver as part of keystone_defconfig. Since, QSPI flash can be used to
for root filesystem, built it into the kernel instead of module.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/configs/keystone_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index d47ea43d097e..4c8abf3c1ab1 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -124,6 +124,7 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_DAVINCI=y
 CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_SRAM=y
-- 
2.13.3

Re: [PATCH 0/7] K2G: Add QSPI support

[Santosh Shilimkar]

On 7/31/2017 9:54 PM, Vignesh R wrote:
> This series adds support for Cadence QSPI for 66AK2G SoC. The first
> three patches enhance the cadence-quadspi driver to support loopback
> clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
> DT nodes and enable the driver in defconfig.
> 
> Tested on 66AK2G GP and ICE boards.
> 
> Vignesh R (7):
>    mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>    mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
>      circuit
>    mtd: spi-nor: cadence-quadspi: Add runtime PM support
>    ARM: dts: keystone-k2g: Add QSPI DT entry
>    ARM: dts: keystone-k2g-evm: Add QSPI node
>    ARM: dts: keystone-k2g-ice: Add QSPI node
>    ARM: configs: keystone: Enable Cadence QSPI driver
> 
Please separate dts and driver patches in its own series
while posting next time since they go throgh different
subsystem trees. Get your driver patch queed
first before adding DTS and enabling config option.

Regards,
Santosh

[PATCH 0/7] K2G: Add QSPI support

[Santosh Shilimkar]

On 7/31/2017 9:54 PM, Vignesh R wrote:
> This series adds support for Cadence QSPI for 66AK2G SoC. The first
> three patches enhance the cadence-quadspi driver to support loopback
> clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
> DT nodes and enable the driver in defconfig.
> 
> Tested on 66AK2G GP and ICE boards.
> 
> Vignesh R (7):
>    mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>    mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
>      circuit
>    mtd: spi-nor: cadence-quadspi: Add runtime PM support
>    ARM: dts: keystone-k2g: Add QSPI DT entry
>    ARM: dts: keystone-k2g-evm: Add QSPI node
>    ARM: dts: keystone-k2g-ice: Add QSPI node
>    ARM: configs: keystone: Enable Cadence QSPI driver
> 
Please separate dts and driver patches in its own series
while posting next time since they go throgh different
subsystem trees. Get your driver patch queed
first before adding DTS and enabling config option.

Regards,
Santosh

Re: [PATCH 0/7] K2G: Add QSPI support

[Vignesh R]

Hi,

On Tuesday 01 August 2017 11:31 PM, Santosh Shilimkar wrote:
> On 7/31/2017 9:54 PM, Vignesh R wrote:
>> This series adds support for Cadence QSPI for 66AK2G SoC. The first
>> three patches enhance the cadence-quadspi driver to support loopback
>> clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
>> DT nodes and enable the driver in defconfig.
>>
>> Tested on 66AK2G GP and ICE boards.
>>
>> Vignesh R (7):
>>    mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>>    mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
>>      circuit
>>    mtd: spi-nor: cadence-quadspi: Add runtime PM support
>>    ARM: dts: keystone-k2g: Add QSPI DT entry
>>    ARM: dts: keystone-k2g-evm: Add QSPI node
>>    ARM: dts: keystone-k2g-ice: Add QSPI node
>>    ARM: configs: keystone: Enable Cadence QSPI driver
>>
> Please separate dts and driver patches in its own series
> while posting next time since they go throgh different
> subsystem trees. Get your driver patch queed
> first before adding DTS and enabling config option.

Okay. I thought it would be easy for you to know when driver patches are
queued, if DTS changes are part of the same series. Will post DT nodes
separately from next time or if I need to do a v2 of this series.

-- 
Regards
Vignesh

Re: [PATCH 0/7] K2G: Add QSPI support

[Vignesh R]

Hi,

On Tuesday 01 August 2017 11:31 PM, Santosh Shilimkar wrote:
> On 7/31/2017 9:54 PM, Vignesh R wrote:
>> This series adds support for Cadence QSPI for 66AK2G SoC. The first
>> three patches enhance the cadence-quadspi driver to support loopback
>> clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
>> DT nodes and enable the driver in defconfig.
>>
>> Tested on 66AK2G GP and ICE boards.
>>
>> Vignesh R (7):
>>    mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>>    mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
>>      circuit
>>    mtd: spi-nor: cadence-quadspi: Add runtime PM support
>>    ARM: dts: keystone-k2g: Add QSPI DT entry
>>    ARM: dts: keystone-k2g-evm: Add QSPI node
>>    ARM: dts: keystone-k2g-ice: Add QSPI node
>>    ARM: configs: keystone: Enable Cadence QSPI driver
>>
> Please separate dts and driver patches in its own series
> while posting next time since they go throgh different
> subsystem trees. Get your driver patch queed
> first before adding DTS and enabling config option.

Okay. I thought it would be easy for you to know when driver patches are
queued, if DTS changes are part of the same series. Will post DT nodes
separately from next time or if I need to do a v2 of this series.

-- 
Regards
Vignesh
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[PATCH 0/7] K2G: Add QSPI support

[Vignesh R]

Hi,

On Tuesday 01 August 2017 11:31 PM, Santosh Shilimkar wrote:
> On 7/31/2017 9:54 PM, Vignesh R wrote:
>> This series adds support for Cadence QSPI for 66AK2G SoC. The first
>> three patches enhance the cadence-quadspi driver to support loopback
>> clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
>> DT nodes and enable the driver in defconfig.
>>
>> Tested on 66AK2G GP and ICE boards.
>>
>> Vignesh R (7):
>>    mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>>    mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
>>      circuit
>>    mtd: spi-nor: cadence-quadspi: Add runtime PM support
>>    ARM: dts: keystone-k2g: Add QSPI DT entry
>>    ARM: dts: keystone-k2g-evm: Add QSPI node
>>    ARM: dts: keystone-k2g-ice: Add QSPI node
>>    ARM: configs: keystone: Enable Cadence QSPI driver
>>
> Please separate dts and driver patches in its own series
> while posting next time since they go throgh different
> subsystem trees. Get your driver patch queed
> first before adding DTS and enabling config option.

Okay. I thought it would be easy for you to know when driver patches are
queued, if DTS changes are part of the same series. Will post DT nodes
separately from next time or if I need to do a v2 of this series.

-- 
Regards
Vignesh

Re: [PATCH 0/7] K2G: Add QSPI support

[Santosh Shilimkar]

8/1/2017 10:52 PM, Vignesh R wrote:
> Hi,
> 
> On Tuesday 01 August 2017 11:31 PM, Santosh Shilimkar wrote:
>> On 7/31/2017 9:54 PM, Vignesh R wrote:
>>> This series adds support for Cadence QSPI for 66AK2G SoC. The first
>>> three patches enhance the cadence-quadspi driver to support loopback
>>> clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
>>> DT nodes and enable the driver in defconfig.
>>>
>>> Tested on 66AK2G GP and ICE boards.
>>>
>>> Vignesh R (7):
>>>     mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>>>     mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
>>>       circuit
>>>     mtd: spi-nor: cadence-quadspi: Add runtime PM support
>>>     ARM: dts: keystone-k2g: Add QSPI DT entry
>>>     ARM: dts: keystone-k2g-evm: Add QSPI node
>>>     ARM: dts: keystone-k2g-ice: Add QSPI node
>>>     ARM: configs: keystone: Enable Cadence QSPI driver
>>>
>> Please separate dts and driver patches in its own series
>> while posting next time since they go throgh different
>> subsystem trees. Get your driver patch queed
>> first before adding DTS and enabling config option.
> 
> Okay. I thought it would be easy for you to know when driver patches are
> queued, if DTS changes are part of the same series. Will post DT nodes
> separately from next time or if I need to do a v2 of this series.
> 
Thanks !!

[PATCH 0/7] K2G: Add QSPI support

[Santosh Shilimkar]

8/1/2017 10:52 PM, Vignesh R wrote:
> Hi,
> 
> On Tuesday 01 August 2017 11:31 PM, Santosh Shilimkar wrote:
>> On 7/31/2017 9:54 PM, Vignesh R wrote:
>>> This series adds support for Cadence QSPI for 66AK2G SoC. The first
>>> three patches enhance the cadence-quadspi driver to support loopback
>>> clock and pm_runtime and tweaks for 66AK2G SoC. Remaining patches add
>>> DT nodes and enable the driver in defconfig.
>>>
>>> Tested on 66AK2G GP and ICE boards.
>>>
>>> Vignesh R (7):
>>>     mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>>>     mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock
>>>       circuit
>>>     mtd: spi-nor: cadence-quadspi: Add runtime PM support
>>>     ARM: dts: keystone-k2g: Add QSPI DT entry
>>>     ARM: dts: keystone-k2g-evm: Add QSPI node
>>>     ARM: dts: keystone-k2g-ice: Add QSPI node
>>>     ARM: configs: keystone: Enable Cadence QSPI driver
>>>
>> Please separate dts and driver patches in its own series
>> while posting next time since they go throgh different
>> subsystem trees. Get your driver patch queed
>> first before adding DTS and enabling config option.
> 
> Okay. I thought it would be easy for you to know when driver patches are
> queued, if DTS changes are part of the same series. Will post DT nodes
> separately from next time or if I need to do a v2 of this series.
> 
Thanks !!

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
> Controller programming sequence, a delay equal to couple QSPI master
> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
> writing data to the flash. Add a new compatible to handle the couple of
> cycles of delay required in the indirect write sequence, since this
> delay is specific to TI 66AK2G SoC.
> 
> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> index f248056da24c..fdd511a83511 100644
> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> @@ -2,6 +2,7 @@
>  
>  Required properties:
>  - compatible : Should be "cdns,qspi-nor".
> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
>  - reg : Contains two entries, each of which is a tuple consisting of a
>  	physical address and length. The first entry is the address and
>  	length of the controller register set. The second entry is the
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 53c7d8e0327a..94571590371d 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -76,6 +76,7 @@ struct cqspi_st {
>  	u32			fifo_depth;
>  	u32			fifo_width;
>  	u32			trigger_address;
> +	u32			wr_delay;
>  	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
>  };
>  
> @@ -608,6 +609,14 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>  	reinit_completion(&cqspi->transfer_complete);
>  	writel(CQSPI_REG_INDIRECTWR_START_MASK,
>  	       reg_base + CQSPI_REG_INDIRECTWR);
> +	/*
> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
> +	 * Controller programming sequence, couple of cycles of
> +	 * QSPI_REF_CLK delay is required for the above bit to
> +	 * be internally synchronized by the QSPI module. Provide 5
> +	 * cycles of delay.
> +	 */
> +	ndelay(cqspi->wr_delay);
>  
>  	while (remaining > 0) {
>  		write_bytes = remaining > page_size ? page_size : remaining;
> @@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
>  	}
>  
>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
> +	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
> +						   cqspi->master_ref_clk_hz);

Use the data pointer in the of_device_id table and put the delay value 
there.

>  
>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>  			       pdev->name, cqspi);
> @@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>  
>  static const struct of_device_id cqspi_dt_ids[] = {
>  	{.compatible = "cdns,qspi-nor",},
> +	{.compatible = "ti,k2g-qspi",},
>  	{ /* end of table */ }
>  };
>  
> -- 
> 2.13.3
> 

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
> Controller programming sequence, a delay equal to couple QSPI master
> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
> writing data to the flash. Add a new compatible to handle the couple of
> cycles of delay required in the indirect write sequence, since this
> delay is specific to TI 66AK2G SoC.
> 
> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
> 
> Signed-off-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> index f248056da24c..fdd511a83511 100644
> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> @@ -2,6 +2,7 @@
>  
>  Required properties:
>  - compatible : Should be "cdns,qspi-nor".
> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
>  - reg : Contains two entries, each of which is a tuple consisting of a
>  	physical address and length. The first entry is the address and
>  	length of the controller register set. The second entry is the
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 53c7d8e0327a..94571590371d 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -76,6 +76,7 @@ struct cqspi_st {
>  	u32			fifo_depth;
>  	u32			fifo_width;
>  	u32			trigger_address;
> +	u32			wr_delay;
>  	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
>  };
>  
> @@ -608,6 +609,14 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>  	reinit_completion(&cqspi->transfer_complete);
>  	writel(CQSPI_REG_INDIRECTWR_START_MASK,
>  	       reg_base + CQSPI_REG_INDIRECTWR);
> +	/*
> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
> +	 * Controller programming sequence, couple of cycles of
> +	 * QSPI_REF_CLK delay is required for the above bit to
> +	 * be internally synchronized by the QSPI module. Provide 5
> +	 * cycles of delay.
> +	 */
> +	ndelay(cqspi->wr_delay);
>  
>  	while (remaining > 0) {
>  		write_bytes = remaining > page_size ? page_size : remaining;
> @@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
>  	}
>  
>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
> +	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
> +						   cqspi->master_ref_clk_hz);

Use the data pointer in the of_device_id table and put the delay value 
there.

>  
>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>  			       pdev->name, cqspi);
> @@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>  
>  static const struct of_device_id cqspi_dt_ids[] = {
>  	{.compatible = "cdns,qspi-nor",},
> +	{.compatible = "ti,k2g-qspi",},
>  	{ /* end of table */ }
>  };
>  
> -- 
> 2.13.3
> 
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[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
> Controller programming sequence, a delay equal to couple QSPI master
> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
> writing data to the flash. Add a new compatible to handle the couple of
> cycles of delay required in the indirect write sequence, since this
> delay is specific to TI 66AK2G SoC.
> 
> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> index f248056da24c..fdd511a83511 100644
> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> @@ -2,6 +2,7 @@
>  
>  Required properties:
>  - compatible : Should be "cdns,qspi-nor".
> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
>  - reg : Contains two entries, each of which is a tuple consisting of a
>  	physical address and length. The first entry is the address and
>  	length of the controller register set. The second entry is the
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 53c7d8e0327a..94571590371d 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -76,6 +76,7 @@ struct cqspi_st {
>  	u32			fifo_depth;
>  	u32			fifo_width;
>  	u32			trigger_address;
> +	u32			wr_delay;
>  	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
>  };
>  
> @@ -608,6 +609,14 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>  	reinit_completion(&cqspi->transfer_complete);
>  	writel(CQSPI_REG_INDIRECTWR_START_MASK,
>  	       reg_base + CQSPI_REG_INDIRECTWR);
> +	/*
> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
> +	 * Controller programming sequence, couple of cycles of
> +	 * QSPI_REF_CLK delay is required for the above bit to
> +	 * be internally synchronized by the QSPI module. Provide 5
> +	 * cycles of delay.
> +	 */
> +	ndelay(cqspi->wr_delay);
>  
>  	while (remaining > 0) {
>  		write_bytes = remaining > page_size ? page_size : remaining;
> @@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
>  	}
>  
>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
> +	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
> +						   cqspi->master_ref_clk_hz);

Use the data pointer in the of_device_id table and put the delay value 
there.

>  
>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>  			       pdev->name, cqspi);
> @@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>  
>  static const struct of_device_id cqspi_dt_ids[] = {
>  	{.compatible = "cdns,qspi-nor",},
> +	{.compatible = "ti,k2g-qspi",},
>  	{ /* end of table */ }
>  };
>  
> -- 
> 2.13.3
> 

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
> Controller programming sequence, a delay equal to couple QSPI master
> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
> writing data to the flash. Add a new compatible to handle the couple of
> cycles of delay required in the indirect write sequence, since this
> delay is specific to TI 66AK2G SoC.
> 
> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> index f248056da24c..fdd511a83511 100644
> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> @@ -2,6 +2,7 @@
>  
>  Required properties:
>  - compatible : Should be "cdns,qspi-nor".
> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.

Also, this doesn't indicate that "cdns,qspi-nor" is a fallback as you 
have in the dts files. Reformat to 1 valid combination per line.

>  - reg : Contains two entries, each of which is a tuple consisting of a
>  	physical address and length. The first entry is the address and
>  	length of the controller register set. The second entry is the

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
> Controller programming sequence, a delay equal to couple QSPI master
> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
> writing data to the flash. Add a new compatible to handle the couple of
> cycles of delay required in the indirect write sequence, since this
> delay is specific to TI 66AK2G SoC.
> 
> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
> 
> Signed-off-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> index f248056da24c..fdd511a83511 100644
> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> @@ -2,6 +2,7 @@
>  
>  Required properties:
>  - compatible : Should be "cdns,qspi-nor".
> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.

Also, this doesn't indicate that "cdns,qspi-nor" is a fallback as you 
have in the dts files. Reformat to 1 valid combination per line.

>  - reg : Contains two entries, each of which is a tuple consisting of a
>  	physical address and length. The first entry is the address and
>  	length of the controller register set. The second entry is the
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[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
> Controller programming sequence, a delay equal to couple QSPI master
> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
> writing data to the flash. Add a new compatible to handle the couple of
> cycles of delay required in the indirect write sequence, since this
> delay is specific to TI 66AK2G SoC.
> 
> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> index f248056da24c..fdd511a83511 100644
> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> @@ -2,6 +2,7 @@
>  
>  Required properties:
>  - compatible : Should be "cdns,qspi-nor".
> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.

Also, this doesn't indicate that "cdns,qspi-nor" is a fallback as you 
have in the dts files. Reformat to 1 valid combination per line.

>  - reg : Contains two entries, each of which is a tuple consisting of a
>  	physical address and length. The first entry is the address and
>  	length of the controller register set. The second entry is the

Re: [PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:29AM +0530, Vignesh R wrote:
> Cadence QSPI IP has a adapted loopback circuit which can be enabled by
> setting BYPASS field to 0 in READCAPTURE register. It enables use of
> QSPI return clock to latch the data rather than the internal QSPI
> reference clock. For high speed operations, adapted loopback circuit
> using QSPI return clock helps to increase data valid window.
> 
> Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
> for boards which do have QSPI return clock provided.
> This patch also modifies cqspi_readdata_capture() function's bypass
> parameter to bool to match how its used in the function.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
>  2 files changed, 9 insertions(+), 2 deletions(-)

Please separate bindings to a separate patch or patches.

Rob

Re: [PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:29AM +0530, Vignesh R wrote:
> Cadence QSPI IP has a adapted loopback circuit which can be enabled by
> setting BYPASS field to 0 in READCAPTURE register. It enables use of
> QSPI return clock to latch the data rather than the internal QSPI
> reference clock. For high speed operations, adapted loopback circuit
> using QSPI return clock helps to increase data valid window.
> 
> Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
> for boards which do have QSPI return clock provided.
> This patch also modifies cqspi_readdata_capture() function's bypass
> parameter to bool to match how its used in the function.
> 
> Signed-off-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
>  2 files changed, 9 insertions(+), 2 deletions(-)

Please separate bindings to a separate patch or patches.

Rob
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[PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Rob Herring]

On Tue, Aug 01, 2017 at 10:24:29AM +0530, Vignesh R wrote:
> Cadence QSPI IP has a adapted loopback circuit which can be enabled by
> setting BYPASS field to 0 in READCAPTURE register. It enables use of
> QSPI return clock to latch the data rather than the internal QSPI
> reference clock. For high speed operations, adapted loopback circuit
> using QSPI return clock helps to increase data valid window.
> 
> Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
> for boards which do have QSPI return clock provided.
> This patch also modifies cqspi_readdata_capture() function's bypass
> parameter to bool to match how its used in the function.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
>  2 files changed, 9 insertions(+), 2 deletions(-)

Please separate bindings to a separate patch or patches.

Rob

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

On Thursday 10 August 2017 05:35 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>> Controller programming sequence, a delay equal to couple QSPI master
>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
>> writing data to the flash. Add a new compatible to handle the couple of
>> cycles of delay required in the indirect write sequence, since this
>> delay is specific to TI 66AK2G SoC.
>>
>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
>>
[...]
>> +	/*
>> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
>> +	 * Controller programming sequence, couple of cycles of
>> +	 * QSPI_REF_CLK delay is required for the above bit to
>> +	 * be internally synchronized by the QSPI module. Provide 5
>> +	 * cycles of delay.
>> +	 */
>> +	ndelay(cqspi->wr_delay);
>>  
>>  	while (remaining > 0) {
>>  		write_bytes = remaining > page_size ? page_size : remaining;
>> @@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
>>  	}
>>  
>>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
>> +	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
>> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
>> +						   cqspi->master_ref_clk_hz);
> 
> Use the data pointer in the of_device_id table and put the delay value 
> there.
> 

I thought about this, but for a given SoC, delay value might vary
depending on what frequency QSPI master_ref_clk is set to. So hard
coding will not help. How about having a flag (CQSPI_NEEDS_WR_DELAY) in
data pointer and then using that to determine whether or not to
calculate and set delay here?

>>  
>>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>>  			       pdev->name, cqspi);
>> @@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>>  
>>  static const struct of_device_id cqspi_dt_ids[] = {
>>  	{.compatible = "cdns,qspi-nor",},
>> +	{.compatible = "ti,k2g-qspi",},
>>  	{ /* end of table */ }
>>  };
>>  
>> -- 
>> 2.13.3
>>

-- 
Regards
Vignesh

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

On Thursday 10 August 2017 05:35 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>> Controller programming sequence, a delay equal to couple QSPI master
>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
>> writing data to the flash. Add a new compatible to handle the couple of
>> cycles of delay required in the indirect write sequence, since this
>> delay is specific to TI 66AK2G SoC.
>>
>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
>>
[...]
>> +	/*
>> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
>> +	 * Controller programming sequence, couple of cycles of
>> +	 * QSPI_REF_CLK delay is required for the above bit to
>> +	 * be internally synchronized by the QSPI module. Provide 5
>> +	 * cycles of delay.
>> +	 */
>> +	ndelay(cqspi->wr_delay);
>>  
>>  	while (remaining > 0) {
>>  		write_bytes = remaining > page_size ? page_size : remaining;
>> @@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
>>  	}
>>  
>>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
>> +	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
>> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
>> +						   cqspi->master_ref_clk_hz);
> 
> Use the data pointer in the of_device_id table and put the delay value 
> there.
> 

I thought about this, but for a given SoC, delay value might vary
depending on what frequency QSPI master_ref_clk is set to. So hard
coding will not help. How about having a flag (CQSPI_NEEDS_WR_DELAY) in
data pointer and then using that to determine whether or not to
calculate and set delay here?

>>  
>>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>>  			       pdev->name, cqspi);
>> @@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>>  
>>  static const struct of_device_id cqspi_dt_ids[] = {
>>  	{.compatible = "cdns,qspi-nor",},
>> +	{.compatible = "ti,k2g-qspi",},
>>  	{ /* end of table */ }
>>  };
>>  
>> -- 
>> 2.13.3
>>

-- 
Regards
Vignesh
--
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[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

On Thursday 10 August 2017 05:35 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>> Controller programming sequence, a delay equal to couple QSPI master
>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
>> writing data to the flash. Add a new compatible to handle the couple of
>> cycles of delay required in the indirect write sequence, since this
>> delay is specific to TI 66AK2G SoC.
>>
>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
>>
[...]
>> +	/*
>> +	 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
>> +	 * Controller programming sequence, couple of cycles of
>> +	 * QSPI_REF_CLK delay is required for the above bit to
>> +	 * be internally synchronized by the QSPI module. Provide 5
>> +	 * cycles of delay.
>> +	 */
>> +	ndelay(cqspi->wr_delay);
>>  
>>  	while (remaining > 0) {
>>  		write_bytes = remaining > page_size ? page_size : remaining;
>> @@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev)
>>  	}
>>  
>>  	cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
>> +	if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi"))
>> +		cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
>> +						   cqspi->master_ref_clk_hz);
> 
> Use the data pointer in the of_device_id table and put the delay value 
> there.
> 

I thought about this, but for a given SoC, delay value might vary
depending on what frequency QSPI master_ref_clk is set to. So hard
coding will not help. How about having a flag (CQSPI_NEEDS_WR_DELAY) in
data pointer and then using that to determine whether or not to
calculate and set delay here?

>>  
>>  	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
>>  			       pdev->name, cqspi);
>> @@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
>>  
>>  static const struct of_device_id cqspi_dt_ids[] = {
>>  	{.compatible = "cdns,qspi-nor",},
>> +	{.compatible = "ti,k2g-qspi",},
>>  	{ /* end of table */ }
>>  };
>>  
>> -- 
>> 2.13.3
>>

-- 
Regards
Vignesh

Re: [PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Vignesh R]

On Thursday 10 August 2017 05:40 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:29AM +0530, Vignesh R wrote:
>> Cadence QSPI IP has a adapted loopback circuit which can be enabled by
>> setting BYPASS field to 0 in READCAPTURE register. It enables use of
>> QSPI return clock to latch the data rather than the internal QSPI
>> reference clock. For high speed operations, adapted loopback circuit
>> using QSPI return clock helps to increase data valid window.
>>
>> Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
>> for boards which do have QSPI return clock provided.
>> This patch also modifies cqspi_readdata_capture() function's bypass
>> parameter to bool to match how its used in the function.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
>>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
>>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> Please separate bindings to a separate patch or patches.
> 
Ok, Will do that in v2.


-- 
Regards
Vignesh

Re: [PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Vignesh R]

On Thursday 10 August 2017 05:40 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:29AM +0530, Vignesh R wrote:
>> Cadence QSPI IP has a adapted loopback circuit which can be enabled by
>> setting BYPASS field to 0 in READCAPTURE register. It enables use of
>> QSPI return clock to latch the data rather than the internal QSPI
>> reference clock. For high speed operations, adapted loopback circuit
>> using QSPI return clock helps to increase data valid window.
>>
>> Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
>> for boards which do have QSPI return clock provided.
>> This patch also modifies cqspi_readdata_capture() function's bypass
>> parameter to bool to match how its used in the function.
>>
>> Signed-off-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
>> ---
>>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
>>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
>>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> Please separate bindings to a separate patch or patches.
> 
Ok, Will do that in v2.


-- 
Regards
Vignesh
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH 2/7] mtd: spi-nor: cadence-quadspi: Add support to enable loopback clock circuit

[Vignesh R]

On Thursday 10 August 2017 05:40 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:29AM +0530, Vignesh R wrote:
>> Cadence QSPI IP has a adapted loopback circuit which can be enabled by
>> setting BYPASS field to 0 in READCAPTURE register. It enables use of
>> QSPI return clock to latch the data rather than the internal QSPI
>> reference clock. For high speed operations, adapted loopback circuit
>> using QSPI return clock helps to increase data valid window.
>>
>> Add DT parameter cdns,rclk-en to help enable adapted loopback circuit
>> for boards which do have QSPI return clock provided.
>> This patch also modifies cqspi_readdata_capture() function's bypass
>> parameter to bool to match how its used in the function.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
>>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 8 ++++++--
>>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> Please separate bindings to a separate patch or patches.
> 
Ok, Will do that in v2.


-- 
Regards
Vignesh

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

On Thursday 10 August 2017 05:38 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>> Controller programming sequence, a delay equal to couple QSPI master
>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
>> writing data to the flash. Add a new compatible to handle the couple of
>> cycles of delay required in the indirect write sequence, since this
>> delay is specific to TI 66AK2G SoC.
>>
>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>>  2 files changed, 14 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> index f248056da24c..fdd511a83511 100644
>> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> @@ -2,6 +2,7 @@
>>  
>>  Required properties:
>>  - compatible : Should be "cdns,qspi-nor".
>> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
> 
> Also, this doesn't indicate that "cdns,qspi-nor" is a fallback as you 
> have in the dts files. Reformat to 1 valid combination per line.
> 

Agreed, will fix it in v2.

-- 
Regards
Vignesh

Re: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

On Thursday 10 August 2017 05:38 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>> Controller programming sequence, a delay equal to couple QSPI master
>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
>> writing data to the flash. Add a new compatible to handle the couple of
>> cycles of delay required in the indirect write sequence, since this
>> delay is specific to TI 66AK2G SoC.
>>
>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>>  2 files changed, 14 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> index f248056da24c..fdd511a83511 100644
>> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> @@ -2,6 +2,7 @@
>>  
>>  Required properties:
>>  - compatible : Should be "cdns,qspi-nor".
>> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
> 
> Also, this doesn't indicate that "cdns,qspi-nor" is a fallback as you 
> have in the dts files. Reformat to 1 valid combination per line.
> 

Agreed, will fix it in v2.

-- 
Regards
Vignesh

[PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence

[Vignesh R]

On Thursday 10 August 2017 05:38 AM, Rob Herring wrote:
> On Tue, Aug 01, 2017 at 10:24:28AM +0530, Vignesh R wrote:
>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
>> Controller programming sequence, a delay equal to couple QSPI master
>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
>> writing data to the flash. Add a new compatible to handle the couple of
>> cycles of delay required in the indirect write sequence, since this
>> delay is specific to TI 66AK2G SoC.
>>
>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt |  1 +
>>  drivers/mtd/spi-nor/cadence-quadspi.c                     | 13 +++++++++++++
>>  2 files changed, 14 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> index f248056da24c..fdd511a83511 100644
>> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> @@ -2,6 +2,7 @@
>>  
>>  Required properties:
>>  - compatible : Should be "cdns,qspi-nor".
>> +	       Should be "ti,k2g-qspi" for TI 66AK2G platform.
> 
> Also, this doesn't indicate that "cdns,qspi-nor" is a fallback as you 
> have in the dts files. Reformat to 1 valid combination per line.
> 

Agreed, will fix it in v2.

-- 
Regards
Vignesh