[PATCH-for-8.0 0/7] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API

[PATCH-for-8.0 0/7] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API

[Philippe Mathieu-Daudé]

Bernhard posted his "Consolidate PIIX south bridges" v3 series:
https://lore.kernel.org/qemu-devel/20221204190553.3274-1-shentey@gmail.com/

However in order to simplify it, on the Malta board we need to set
the PIIX IRQC[A:D] routing values via the embedded bootloader (used
when no external BIOS is provided). Jiaxun added a "bootloader
generator API" for 32-bit wide instructions, and we use it in the
write_bootloader() function.
This series provides the nanoMIPS equivalent generated instructions
and update the write_bootloader_nanomips() function.
That allow fixing the TODO left in
https://lore.kernel.org/qemu-devel/20221027204720.33611-3-philmd@linaro.org/
and apply Bernhard's consolidation.

Please review,

Phil.

Philippe Mathieu-Daudé (7):
  hw/mips/bootloader: Handle buffers as opaque arrays
  hw/mips/bootloader: Pass 32-bit immediate value to LUI opcode
    generator
  hw/mips/bootloader: Implement nanoMIPS NOP opcode
  hw/mips/bootloader: Implement nanoMIPS LUI opcode
  hw/mips/bootloader: Implement nanoMIPS SW opcode
  hw/mips/bootloader: Implement nanoMIPS SW opcode
  hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs

 hw/mips/bootloader.c         | 140 +++++++++++++++++++++++------
 hw/mips/malta.c              | 167 ++++++++++-------------------------
 include/hw/mips/bootloader.h |  10 +--
 3 files changed, 162 insertions(+), 155 deletions(-)

-- 
2.38.1

[PATCH-for-8.0 1/7] hw/mips/bootloader: Handle buffers as opaque arrays

[Philippe Mathieu-Daudé]

It is irrelevant to the API what the buffers to fill are made of.
In particular, some MIPS ISA have 16-bit wide instructions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c         | 55 +++++++++++++++++++++---------------
 hw/mips/malta.c              | 19 +++++++------
 include/hw/mips/bootloader.h | 10 +++----
 3 files changed, 48 insertions(+), 36 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index f5f42f2bf2..fc14eb0894 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -55,16 +55,20 @@ static bool bootcpu_supports_isa(uint64_t isa_mask)
 }
 
 /* Base types */
-static void bl_gen_nop(uint32_t **p)
+static void bl_gen_nop(void **ptr)
 {
-    stl_p(*p, 0);
-    *p = *p + 1;
+    uint32_t *p = (uint32_t *)*ptr;
+
+    stl_p(p, 0);
+    p++;
+    *ptr = p;
 }
 
-static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
+static void bl_gen_r_type(void **ptr, uint8_t opcode,
                           bl_reg rs, bl_reg rt, bl_reg rd,
                           uint8_t shift, uint8_t funct)
 {
+    uint32_t *p = (uint32_t *)*ptr;
     uint32_t insn = 0;
 
     insn = deposit32(insn, 26, 6, opcode);
@@ -74,13 +78,16 @@ static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
     insn = deposit32(insn, 6, 5, shift);
     insn = deposit32(insn, 0, 6, funct);
 
-    stl_p(*p, insn);
-    *p = *p + 1;
+    stl_p(p, insn);
+    p++;
+
+    *ptr = p;
 }
 
-static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
+static void bl_gen_i_type(void **ptr, uint8_t opcode,
                           bl_reg rs, bl_reg rt, uint16_t imm)
 {
+    uint32_t *p = (uint32_t *)*ptr;
     uint32_t insn = 0;
 
     insn = deposit32(insn, 26, 6, opcode);
@@ -88,12 +95,14 @@ static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
     insn = deposit32(insn, 16, 5, rt);
     insn = deposit32(insn, 0, 16, imm);
 
-    stl_p(*p, insn);
-    *p = *p + 1;
+    stl_p(p, insn);
+    p++;
+
+    *ptr = p;
 }
 
 /* Single instructions */
-static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
+static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
@@ -102,28 +111,28 @@ static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
     }
 }
 
-static void bl_gen_jalr(uint32_t **p, bl_reg rs)
+static void bl_gen_jalr(void **p, bl_reg rs)
 {
     bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
 }
 
-static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm)
+static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
 {
     /* R6: It's a alias of AUI with RS = 0 */
     bl_gen_i_type(p, 0x0f, 0, rt, imm);
 }
 
-static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm)
+static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
 {
     bl_gen_i_type(p, 0x0d, rs, rt, imm);
 }
 
-static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
+static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 {
     bl_gen_i_type(p, 0x2b, base, rt, offset);
 }
 
-static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
+static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_i_type(p, 0x3f, base, rt, offset);
@@ -133,13 +142,13 @@ static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
 }
 
 /* Pseudo instructions */
-static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm)
+static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
 {
     bl_gen_lui(p, rt, extract32(imm, 16, 16));
     bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
 }
 
-static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
+static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
 {
     bl_gen_li(p, rt, extract64(imm, 32, 32));
     bl_gen_dsll(p, rt, rt, 16);
@@ -148,7 +157,7 @@ static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
     bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
 }
 
-static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
+static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_dli(p, rt, imm); /* 64bit */
@@ -158,14 +167,14 @@ static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
 }
 
 /* Helpers */
-void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
+void bl_gen_jump_to(void **p, target_ulong jump_addr)
 {
     bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
     bl_gen_jalr(p, BL_REG_T9);
     bl_gen_nop(p); /* delay slot */
 }
 
-void bl_gen_jump_kernel(uint32_t **p,
+void bl_gen_jump_kernel(void **p,
                         bool set_sp, target_ulong sp,
                         bool set_a0, target_ulong a0,
                         bool set_a1, target_ulong a1,
@@ -192,7 +201,7 @@ void bl_gen_jump_kernel(uint32_t **p,
     bl_gen_jump_to(p, kernel_addr);
 }
 
-void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
+void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
 {
     bl_gen_load_ulong(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
@@ -203,14 +212,14 @@ void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
     }
 }
 
-void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val)
+void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val)
 {
     bl_gen_li(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
     bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
 }
 
-void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val)
+void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val)
 {
     bl_gen_dli(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 1f4e0c7acc..944730af98 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -838,6 +838,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
                              uint64_t kernel_entry)
 {
     uint32_t *p;
+    void *v;
 
     /* Small bootloader */
     p = (uint32_t *)base;
@@ -880,38 +881,39 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
 #else
 #define cpu_to_gt32 cpu_to_be32
 #endif
+    v = p;
 
     /* move GT64120 registers from 0x14000000 to 0x1be00000 */
-    bl_gen_write_u32(&p, /* GT_ISD */
+    bl_gen_write_u32(&v, /* GT_ISD */
                      cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
                      cpu_to_gt32(0x1be00000 << 3));
 
     /* setup MEM-to-PCI0 mapping */
     /* setup PCI0 io window to 0x18000000-0x181fffff */
-    bl_gen_write_u32(&p, /* GT_PCI0IOLD */
+    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
                      cpu_to_gt32(0x18000000 << 3));
-    bl_gen_write_u32(&p, /* GT_PCI0IOHD */
+    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
                      cpu_to_gt32(0x08000000 << 3));
     /* setup PCI0 mem windows */
-    bl_gen_write_u32(&p, /* GT_PCI0M0LD */
+    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
                      cpu_to_gt32(0x10000000 << 3));
-    bl_gen_write_u32(&p, /* GT_PCI0M0HD */
+    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
                      cpu_to_gt32(0x07e00000 << 3));
 
-    bl_gen_write_u32(&p, /* GT_PCI0M1LD */
+    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
                      cpu_to_gt32(0x18200000 << 3));
-    bl_gen_write_u32(&p, /* GT_PCI0M1HD */
+    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
                      cpu_to_gt32(0x0bc00000 << 3));
 
 #undef cpu_to_gt32
 
-    bl_gen_jump_kernel(&p,
+    bl_gen_jump_kernel(&v,
                        true, ENVP_VADDR - 64,
                        /*
                         * If semihosting is used, arguments have already been
@@ -922,6 +924,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
                        true, ENVP_VADDR + 8,
                        true, loaderparams.ram_low_size,
                        kernel_entry);
+    p = (uint32_t *)v;
 
     /* YAMON subroutines */
     p = (uint32_t *) (base + 0x800);
diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index fffb0b7da8..c32f6c2835 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -11,16 +11,16 @@
 
 #include "exec/cpu-defs.h"
 
-void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
-void bl_gen_jump_kernel(uint32_t **p,
+void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
+void bl_gen_jump_kernel(void **ptr,
                         bool set_sp, target_ulong sp,
                         bool set_a0, target_ulong a0,
                         bool set_a1, target_ulong a1,
                         bool set_a2, target_ulong a2,
                         bool set_a3, target_ulong a3,
                         target_ulong kernel_addr);
-void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val);
-void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val);
-void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val);
+void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
+void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
+void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
 
 #endif
-- 
2.38.1

[PATCH-for-8.0 2/7] hw/mips/bootloader: Pass 32-bit immediate value to LUI opcode generator

[Philippe Mathieu-Daudé]

While 32-bit wide instructions ISA restricts LUI to a 16-bit
immediate value, some 16-bit ones allow up to 20-bit immediate
(in particular nanoMIPS).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index fc14eb0894..3a4573118c 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -116,10 +116,11 @@ static void bl_gen_jalr(void **p, bl_reg rs)
     bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
 }
 
-static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
+static void bl_gen_lui(void **p, bl_reg rt, uint32_t imm32)
 {
     /* R6: It's a alias of AUI with RS = 0 */
-    bl_gen_i_type(p, 0x0f, 0, rt, imm);
+    assert(imm32 <= UINT16_MAX);
+    bl_gen_i_type(p, 0x0f, 0, rt, extract32(imm32, 16, 16));
 }
 
 static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
@@ -142,10 +143,10 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 }
 
 /* Pseudo instructions */
-static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
+static void bl_gen_li(void **p, bl_reg rt, uint32_t imm32)
 {
-    bl_gen_lui(p, rt, extract32(imm, 16, 16));
-    bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
+    bl_gen_lui(p, rt, imm32);
+    bl_gen_ori(p, rt, rt, extract32(imm32, 0, 16));
 }
 
 static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
-- 
2.38.1

[PATCH-for-8.0 3/7] hw/mips/bootloader: Implement nanoMIPS NOP opcode

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 3a4573118c..7f7d938f2e 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -59,7 +59,11 @@ static void bl_gen_nop(void **ptr)
 {
     uint32_t *p = (uint32_t *)*ptr;
 
-    stl_p(p, 0);
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        stl_p(p, 0x8000c000);
+    } else {
+        stl_p(p, 0);
+    }
     p++;
     *ptr = p;
 }
-- 
2.38.1

[PATCH-for-8.0 4/7] hw/mips/bootloader: Implement nanoMIPS LUI opcode

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 7f7d938f2e..997e74ee52 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -120,11 +120,34 @@ static void bl_gen_jalr(void **p, bl_reg rs)
     bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
 }
 
+static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
+{
+    uint16_t *p = (uint16_t *)*ptr;
+    uint32_t insn = 0;
+
+    insn = deposit32(insn, 26, 6, 0b111000);
+    insn = deposit32(insn, 21, 5, rt);
+    insn = deposit32(insn, 12, 9, extract32(imm20, 12, 9));
+    insn = deposit32(insn, 2, 10, extract32(imm20, 21, 10));
+    insn = deposit32(insn, 0, 1, sextract32(imm20, 31, 1));
+
+    stw_p(p, insn >> 16);
+    p++;
+    stw_p(p, insn >> 0);
+    p++;
+
+    *ptr = p;
+}
+
 static void bl_gen_lui(void **p, bl_reg rt, uint32_t imm32)
 {
-    /* R6: It's a alias of AUI with RS = 0 */
-    assert(imm32 <= UINT16_MAX);
-    bl_gen_i_type(p, 0x0f, 0, rt, extract32(imm32, 16, 16));
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        bl_gen_lui_nm(p, rt, imm32);
+    } else {
+        /* R6: It's a alias of AUI with RS = 0 */
+        assert(imm32 <= UINT16_MAX);
+        bl_gen_i_type(p, 0x0f, 0, rt, extract32(imm32, 16, 16));
+    }
 }
 
 static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
-- 
2.38.1

[PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 997e74ee52..cc3df385df 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -150,9 +150,31 @@ static void bl_gen_lui(void **p, bl_reg rt, uint32_t imm32)
     }
 }
 
+static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm)
+{
+    uint16_t *p = (uint16_t *)*ptr;
+    uint32_t insn = 0;
+
+    insn = deposit32(insn, 26, 6, 0b100000);
+    insn = deposit32(insn, 21, 5, rt);
+    insn = deposit32(insn, 16, 5, rs);
+    insn = deposit32(insn, 0, 12, imm);
+
+    stw_p(p, insn >> 16);
+    p++;
+    stw_p(p, insn >> 0);
+    p++;
+
+    *ptr = p;
+}
+
 static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
 {
-    bl_gen_i_type(p, 0x0d, rs, rt, imm);
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        bl_gen_ori_nm(p, rt, rs, imm);
+    } else {
+        bl_gen_i_type(p, 0x0d, rs, rt, imm);
+    }
 }
 
 static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
-- 
2.38.1

[PATCH-for-8.0 6/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index cc3df385df..541b59bf84 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -177,9 +177,32 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
     }
 }
 
+static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t offset)
+{
+    uint16_t *p = (uint16_t *)*ptr;
+    uint32_t insn = 0;
+
+    insn = deposit32(insn, 26, 6, 0b100001);
+    insn = deposit32(insn, 21, 5, rt);
+    insn = deposit32(insn, 16, 5, rs);
+    insn = deposit32(insn, 12, 4, 0b1001);
+    insn = deposit32(insn, 0, 12, offset);
+
+    stw_p(p, insn >> 16);
+    p++;
+    stw_p(p, insn >> 0);
+    p++;
+
+    *ptr = p;
+}
+
 static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 {
-    bl_gen_i_type(p, 0x2b, base, rt, offset);
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        bl_gen_sw_nm(p, rt, base, offset);
+    } else {
+        bl_gen_i_type(p, 0x2b, base, rt, offset);
+    }
 }
 
 static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
-- 
2.38.1

[PATCH-for-8.0 7/7] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs

[Philippe Mathieu-Daudé]

Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader
helper to set BAR registers") converted write_bootloader(), convert
the equivalent write_bootloader_nanomips(), allowing us to modify
the bootloader code more easily in the future.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 148 ++++++++++++------------------------------------
 1 file changed, 35 insertions(+), 113 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 944730af98..d0da0b71eb 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -614,6 +614,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
                                       uint64_t kernel_entry)
 {
     uint16_t *p;
+    void *v;
 
     /* Small bootloader */
     p = (uint16_t *)base;
@@ -682,123 +683,44 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
     stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
                                 /* ori a3,a3,%lo(loaderparams.ram_low_size) */
 
-    /*
-     * Load BAR registers as done by YAMON:
-     *
-     *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
-     *  - set up PCI0 MEM0 at 0x10000000, size 0x8000000
-     *  - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
-     *
-     */
-    stw_p(p++, 0xe040); stw_p(p++, 0x0681);
-                                /* lui t1, %hi(0xb4000000)      */
-
 #if TARGET_BIG_ENDIAN
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
-                                /* lui t0, %hi(0xdf000000)      */
-
-    /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c)  */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
-                                /* sw t0, 0x68(t1)              */
-
-    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
-                                /* lui t1, %hi(0xbbe00000)      */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0801);
-                                /* lui t0, %hi(0xc0000000)      */
-
-    /* 0x48 corresponds to GT_PCI0IOLD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
-                                /* sw t0, 0x48(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0800);
-                                /* lui t0, %hi(0x40000000)      */
-
-    /* 0x50 corresponds to GT_PCI0IOHD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
-                                /* sw t0, 0x50(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0001);
-                                /* lui t0, %hi(0x80000000)      */
-
-    /* 0x58 corresponds to GT_PCI0M0LD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
-                                /* sw t0, 0x58(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
-                                /* lui t0, %hi(0x3f000000)      */
-
-    /* 0x60 corresponds to GT_PCI0M0HD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
-                                /* sw t0, 0x60(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0821);
-                                /* lui t0, %hi(0xc1000000)      */
-
-    /* 0x80 corresponds to GT_PCI0M1LD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9080);
-                                /* sw t0, 0x80(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
-                                /* lui t0, %hi(0x5e000000)      */
-
+#define cpu_to_gt32 cpu_to_le32
 #else
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x00df);
-                                /* addiu[32] t0, $0, 0xdf       */
-
-    /* 0x68 corresponds to GT_ISD                               */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
-                                /* sw t0, 0x68(t1)              */
-
-    /* Use kseg2 remapped address 0x1be00000                    */
-    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
-                                /* lui t1, %hi(0xbbe00000)      */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
-                                /* addiu[32] t0, $0, 0xc0       */
-
-    /* 0x48 corresponds to GT_PCI0IOLD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
-                                /* sw t0, 0x48(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x0040);
-                                /* addiu[32] t0, $0, 0x40       */
-
-    /* 0x50 corresponds to GT_PCI0IOHD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
-                                /* sw t0, 0x50(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x0080);
-                                /* addiu[32] t0, $0, 0x80       */
-
-    /* 0x58 corresponds to GT_PCI0M0LD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
-                                /* sw t0, 0x58(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x003f);
-                                /* addiu[32] t0, $0, 0x3f       */
-
-    /* 0x60 corresponds to GT_PCI0M0HD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
-                                /* sw t0, 0x60(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
-                                /* addiu[32] t0, $0, 0xc1       */
-
-    /* 0x80 corresponds to GT_PCI0M1LD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9080);
-                                /* sw t0, 0x80(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x005e);
-                                /* addiu[32] t0, $0, 0x5e       */
-
+#define cpu_to_gt32 cpu_to_be32
 #endif
+    v = p;
 
-    /* 0x88 corresponds to GT_PCI0M1HD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9088);
-                                /* sw t0, 0x88(t1)              */
+    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+    bl_gen_write_u32(&v, /* GT_ISD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
+                     cpu_to_gt32(0x1be00000 << 3));
+
+    /* setup MEM-to-PCI0 mapping */
+    /* setup PCI0 io window to 0x18000000-0x181fffff */
+    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+                     cpu_to_gt32(0x18000000 << 3));
+    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+                     cpu_to_gt32(0x08000000 << 3));
+    /* setup PCI0 mem windows */
+    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
+                     cpu_to_gt32(0x10000000 << 3));
+    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
+                     cpu_to_gt32(0x07e00000 << 3));
+
+    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
+                     cpu_to_gt32(0x18200000 << 3));
+    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
+                     cpu_to_gt32(0x0bc00000 << 3));
+
+    p = (uint16_t *)v;
+
+#undef cpu_to_gt32
 
     stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
 
-- 
2.38.1

Re: [PATCH-for-8.0 4/7] hw/mips/bootloader: Implement nanoMIPS LUI opcode

[Philippe Mathieu-Daudé]

On 10/12/22 16:54, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/bootloader.c | 29 ++++++++++++++++++++++++++---
>   1 file changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index 7f7d938f2e..997e74ee52 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -120,11 +120,34 @@ static void bl_gen_jalr(void **p, bl_reg rs)
>       bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
>   }
>   
> +static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
> +{
> +    uint16_t *p = (uint16_t *)*ptr;
> +    uint32_t insn = 0;

Hmm we should check if imm20 fits in 20-bit.

> +    insn = deposit32(insn, 26, 6, 0b111000);
> +    insn = deposit32(insn, 21, 5, rt);
> +    insn = deposit32(insn, 12, 9, extract32(imm20, 12, 9));
> +    insn = deposit32(insn, 2, 10, extract32(imm20, 21, 10));
> +    insn = deposit32(insn, 0, 1, sextract32(imm20, 31, 1));
> +
> +    stw_p(p, insn >> 16);
> +    p++;
> +    stw_p(p, insn >> 0);
> +    p++;
> +
> +    *ptr = p;
> +}

Re: [PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Philippe Mathieu-Daudé]

On 10/12/22 16:55, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/bootloader.c | 24 +++++++++++++++++++++++-
>   1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index 997e74ee52..cc3df385df 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -150,9 +150,31 @@ static void bl_gen_lui(void **p, bl_reg rt, uint32_t imm32)
>       }
>   }
>   
> +static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm)
> +{
> +    uint16_t *p = (uint16_t *)*ptr;
> +    uint32_t insn = 0;

Similarly, we should check whether imm fits in 12-bit.

> +    insn = deposit32(insn, 26, 6, 0b100000);
> +    insn = deposit32(insn, 21, 5, rt);
> +    insn = deposit32(insn, 16, 5, rs);
> +    insn = deposit32(insn, 0, 12, imm);
> +
> +    stw_p(p, insn >> 16);
> +    p++;
> +    stw_p(p, insn >> 0);
> +    p++;
> +
> +    *ptr = p;
> +}

Re: [PATCH-for-8.0 1/7] hw/mips/bootloader: Handle buffers as opaque arrays

[BALATON Zoltan]

[-- Attachment #1: Type: text/plain, Size: 10444 bytes --]

On Sat, 10 Dec 2022, Philippe Mathieu-Daudé wrote:
> It is irrelevant to the API what the buffers to fill are made of.
> In particular, some MIPS ISA have 16-bit wide instructions.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/mips/bootloader.c         | 55 +++++++++++++++++++++---------------
> hw/mips/malta.c              | 19 +++++++------
> include/hw/mips/bootloader.h | 10 +++----
> 3 files changed, 48 insertions(+), 36 deletions(-)
>
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index f5f42f2bf2..fc14eb0894 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -55,16 +55,20 @@ static bool bootcpu_supports_isa(uint64_t isa_mask)
> }
>
> /* Base types */
> -static void bl_gen_nop(uint32_t **p)
> +static void bl_gen_nop(void **ptr)
> {
> -    stl_p(*p, 0);
> -    *p = *p + 1;
> +    uint32_t *p = (uint32_t *)*ptr;

Do you need to cast void * ? I thought in C that's not necessary but maybe 
I'm missing why it's needed here.

> +
> +    stl_p(p, 0);
> +    p++;
> +    *ptr = p;

Do you need a cast here though? (You could also combine the ++ either in 
stl_p(p++, 0) or *ptr = ++p but not sure you want to.)

Regards,
BALATON Zoltan

> }
>
> -static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
> +static void bl_gen_r_type(void **ptr, uint8_t opcode,
>                           bl_reg rs, bl_reg rt, bl_reg rd,
>                           uint8_t shift, uint8_t funct)
> {
> +    uint32_t *p = (uint32_t *)*ptr;
>     uint32_t insn = 0;
>
>     insn = deposit32(insn, 26, 6, opcode);
> @@ -74,13 +78,16 @@ static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
>     insn = deposit32(insn, 6, 5, shift);
>     insn = deposit32(insn, 0, 6, funct);
>
> -    stl_p(*p, insn);
> -    *p = *p + 1;
> +    stl_p(p, insn);
> +    p++;
> +
> +    *ptr = p;
> }
>
> -static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
> +static void bl_gen_i_type(void **ptr, uint8_t opcode,
>                           bl_reg rs, bl_reg rt, uint16_t imm)
> {
> +    uint32_t *p = (uint32_t *)*ptr;
>     uint32_t insn = 0;
>
>     insn = deposit32(insn, 26, 6, opcode);
> @@ -88,12 +95,14 @@ static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
>     insn = deposit32(insn, 16, 5, rt);
>     insn = deposit32(insn, 0, 16, imm);
>
> -    stl_p(*p, insn);
> -    *p = *p + 1;
> +    stl_p(p, insn);
> +    p++;
> +
> +    *ptr = p;
> }
>
> /* Single instructions */
> -static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
> +static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
> {
>     if (bootcpu_supports_isa(ISA_MIPS3)) {
>         bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
> @@ -102,28 +111,28 @@ static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
>     }
> }
>
> -static void bl_gen_jalr(uint32_t **p, bl_reg rs)
> +static void bl_gen_jalr(void **p, bl_reg rs)
> {
>     bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
> }
>
> -static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm)
> +static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
> {
>     /* R6: It's a alias of AUI with RS = 0 */
>     bl_gen_i_type(p, 0x0f, 0, rt, imm);
> }
>
> -static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm)
> +static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
> {
>     bl_gen_i_type(p, 0x0d, rs, rt, imm);
> }
>
> -static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
> +static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
> {
>     bl_gen_i_type(p, 0x2b, base, rt, offset);
> }
>
> -static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
> +static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
> {
>     if (bootcpu_supports_isa(ISA_MIPS3)) {
>         bl_gen_i_type(p, 0x3f, base, rt, offset);
> @@ -133,13 +142,13 @@ static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
> }
>
> /* Pseudo instructions */
> -static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm)
> +static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
> {
>     bl_gen_lui(p, rt, extract32(imm, 16, 16));
>     bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
> }
>
> -static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
> +static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
> {
>     bl_gen_li(p, rt, extract64(imm, 32, 32));
>     bl_gen_dsll(p, rt, rt, 16);
> @@ -148,7 +157,7 @@ static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
>     bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
> }
>
> -static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
> +static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
> {
>     if (bootcpu_supports_isa(ISA_MIPS3)) {
>         bl_gen_dli(p, rt, imm); /* 64bit */
> @@ -158,14 +167,14 @@ static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
> }
>
> /* Helpers */
> -void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
> +void bl_gen_jump_to(void **p, target_ulong jump_addr)
> {
>     bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
>     bl_gen_jalr(p, BL_REG_T9);
>     bl_gen_nop(p); /* delay slot */
> }
>
> -void bl_gen_jump_kernel(uint32_t **p,
> +void bl_gen_jump_kernel(void **p,
>                         bool set_sp, target_ulong sp,
>                         bool set_a0, target_ulong a0,
>                         bool set_a1, target_ulong a1,
> @@ -192,7 +201,7 @@ void bl_gen_jump_kernel(uint32_t **p,
>     bl_gen_jump_to(p, kernel_addr);
> }
>
> -void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
> +void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
> {
>     bl_gen_load_ulong(p, BL_REG_K0, val);
>     bl_gen_load_ulong(p, BL_REG_K1, addr);
> @@ -203,14 +212,14 @@ void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
>     }
> }
>
> -void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val)
> +void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val)
> {
>     bl_gen_li(p, BL_REG_K0, val);
>     bl_gen_load_ulong(p, BL_REG_K1, addr);
>     bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
> }
>
> -void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val)
> +void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val)
> {
>     bl_gen_dli(p, BL_REG_K0, val);
>     bl_gen_load_ulong(p, BL_REG_K1, addr);
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 1f4e0c7acc..944730af98 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -838,6 +838,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
>                              uint64_t kernel_entry)
> {
>     uint32_t *p;
> +    void *v;
>
>     /* Small bootloader */
>     p = (uint32_t *)base;
> @@ -880,38 +881,39 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
> #else
> #define cpu_to_gt32 cpu_to_be32
> #endif
> +    v = p;
>
>     /* move GT64120 registers from 0x14000000 to 0x1be00000 */
> -    bl_gen_write_u32(&p, /* GT_ISD */
> +    bl_gen_write_u32(&v, /* GT_ISD */
>                      cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
>                      cpu_to_gt32(0x1be00000 << 3));
>
>     /* setup MEM-to-PCI0 mapping */
>     /* setup PCI0 io window to 0x18000000-0x181fffff */
> -    bl_gen_write_u32(&p, /* GT_PCI0IOLD */
> +    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
>                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
>                      cpu_to_gt32(0x18000000 << 3));
> -    bl_gen_write_u32(&p, /* GT_PCI0IOHD */
> +    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
>                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
>                      cpu_to_gt32(0x08000000 << 3));
>     /* setup PCI0 mem windows */
> -    bl_gen_write_u32(&p, /* GT_PCI0M0LD */
> +    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
>                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
>                      cpu_to_gt32(0x10000000 << 3));
> -    bl_gen_write_u32(&p, /* GT_PCI0M0HD */
> +    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
>                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
>                      cpu_to_gt32(0x07e00000 << 3));
>
> -    bl_gen_write_u32(&p, /* GT_PCI0M1LD */
> +    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
>                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
>                      cpu_to_gt32(0x18200000 << 3));
> -    bl_gen_write_u32(&p, /* GT_PCI0M1HD */
> +    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
>                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
>                      cpu_to_gt32(0x0bc00000 << 3));
>
> #undef cpu_to_gt32
>
> -    bl_gen_jump_kernel(&p,
> +    bl_gen_jump_kernel(&v,
>                        true, ENVP_VADDR - 64,
>                        /*
>                         * If semihosting is used, arguments have already been
> @@ -922,6 +924,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
>                        true, ENVP_VADDR + 8,
>                        true, loaderparams.ram_low_size,
>                        kernel_entry);
> +    p = (uint32_t *)v;
>
>     /* YAMON subroutines */
>     p = (uint32_t *) (base + 0x800);
> diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
> index fffb0b7da8..c32f6c2835 100644
> --- a/include/hw/mips/bootloader.h
> +++ b/include/hw/mips/bootloader.h
> @@ -11,16 +11,16 @@
>
> #include "exec/cpu-defs.h"
>
> -void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
> -void bl_gen_jump_kernel(uint32_t **p,
> +void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
> +void bl_gen_jump_kernel(void **ptr,
>                         bool set_sp, target_ulong sp,
>                         bool set_a0, target_ulong a0,
>                         bool set_a1, target_ulong a1,
>                         bool set_a2, target_ulong a2,
>                         bool set_a3, target_ulong a3,
>                         target_ulong kernel_addr);
> -void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val);
> -void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val);
> -void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val);
> +void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
> +void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
> +void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
>
> #endif
>

Re: [PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Bernhard Beschow]

Am 10. Dezember 2022 15:55:00 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>:

s/SW/ORI/ in the title?

Best regards,
Bernhard

>Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>---
> hw/mips/bootloader.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
>diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
>index 997e74ee52..cc3df385df 100644
>--- a/hw/mips/bootloader.c
>+++ b/hw/mips/bootloader.c
>@@ -150,9 +150,31 @@ static void bl_gen_lui(void **p, bl_reg rt, uint32_t imm32)
>     }
> }
> 
>+static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm)
>+{
>+    uint16_t *p = (uint16_t *)*ptr;
>+    uint32_t insn = 0;
>+
>+    insn = deposit32(insn, 26, 6, 0b100000);
>+    insn = deposit32(insn, 21, 5, rt);
>+    insn = deposit32(insn, 16, 5, rs);
>+    insn = deposit32(insn, 0, 12, imm);
>+
>+    stw_p(p, insn >> 16);
>+    p++;
>+    stw_p(p, insn >> 0);
>+    p++;
>+
>+    *ptr = p;
>+}
>+
> static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
> {
>-    bl_gen_i_type(p, 0x0d, rs, rt, imm);
>+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
>+        bl_gen_ori_nm(p, rt, rs, imm);
>+    } else {
>+        bl_gen_i_type(p, 0x0d, rs, rt, imm);
>+    }
> }
> 
> static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)

Re: [PATCH-for-8.0 7/7] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs

[Bernhard Beschow]

Am 10. Dezember 2022 15:55:02 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>:
>Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader
>helper to set BAR registers") converted write_bootloader(), convert
>the equivalent write_bootloader_nanomips(), allowing us to modify
>the bootloader code more easily in the future.
>
>Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>---
> hw/mips/malta.c | 148 ++++++++++++------------------------------------
> 1 file changed, 35 insertions(+), 113 deletions(-)
>
>diff --git a/hw/mips/malta.c b/hw/mips/malta.c
>index 944730af98..d0da0b71eb 100644
>--- a/hw/mips/malta.c
>+++ b/hw/mips/malta.c
>@@ -614,6 +614,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>                                       uint64_t kernel_entry)
> {
>     uint16_t *p;
>+    void *v;
> 
>     /* Small bootloader */
>     p = (uint16_t *)base;
>@@ -682,123 +683,44 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>     stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
>                                 /* ori a3,a3,%lo(loaderparams.ram_low_size) */
> 
>-    /*
>-     * Load BAR registers as done by YAMON:
>-     *
>-     *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
>-     *  - set up PCI0 MEM0 at 0x10000000, size 0x8000000
>-     *  - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
>-     *
>-     */
>-    stw_p(p++, 0xe040); stw_p(p++, 0x0681);
>-                                /* lui t1, %hi(0xb4000000)      */
>-
> #if TARGET_BIG_ENDIAN
>-
>-    stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
>-                                /* lui t0, %hi(0xdf000000)      */
>-
>-    /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c)  */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
>-                                /* sw t0, 0x68(t1)              */
>-
>-    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
>-                                /* lui t1, %hi(0xbbe00000)      */
>-
>-    stw_p(p++, 0xe020); stw_p(p++, 0x0801);
>-                                /* lui t0, %hi(0xc0000000)      */
>-
>-    /* 0x48 corresponds to GT_PCI0IOLD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
>-                                /* sw t0, 0x48(t1)              */
>-
>-    stw_p(p++, 0xe020); stw_p(p++, 0x0800);
>-                                /* lui t0, %hi(0x40000000)      */
>-
>-    /* 0x50 corresponds to GT_PCI0IOHD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
>-                                /* sw t0, 0x50(t1)              */
>-
>-    stw_p(p++, 0xe020); stw_p(p++, 0x0001);
>-                                /* lui t0, %hi(0x80000000)      */
>-
>-    /* 0x58 corresponds to GT_PCI0M0LD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
>-                                /* sw t0, 0x58(t1)              */
>-
>-    stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
>-                                /* lui t0, %hi(0x3f000000)      */
>-
>-    /* 0x60 corresponds to GT_PCI0M0HD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
>-                                /* sw t0, 0x60(t1)              */
>-
>-    stw_p(p++, 0xe020); stw_p(p++, 0x0821);
>-                                /* lui t0, %hi(0xc1000000)      */
>-
>-    /* 0x80 corresponds to GT_PCI0M1LD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9080);
>-                                /* sw t0, 0x80(t1)              */
>-
>-    stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
>-                                /* lui t0, %hi(0x5e000000)      */
>-
>+#define cpu_to_gt32 cpu_to_le32
> #else
>-
>-    stw_p(p++, 0x0020); stw_p(p++, 0x00df);
>-                                /* addiu[32] t0, $0, 0xdf       */
>-
>-    /* 0x68 corresponds to GT_ISD                               */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9068);
>-                                /* sw t0, 0x68(t1)              */
>-
>-    /* Use kseg2 remapped address 0x1be00000                    */
>-    stw_p(p++, 0xe040); stw_p(p++, 0x077d);
>-                                /* lui t1, %hi(0xbbe00000)      */
>-
>-    stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
>-                                /* addiu[32] t0, $0, 0xc0       */
>-
>-    /* 0x48 corresponds to GT_PCI0IOLD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
>-                                /* sw t0, 0x48(t1)              */
>-
>-    stw_p(p++, 0x0020); stw_p(p++, 0x0040);
>-                                /* addiu[32] t0, $0, 0x40       */
>-
>-    /* 0x50 corresponds to GT_PCI0IOHD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
>-                                /* sw t0, 0x50(t1)              */
>-
>-    stw_p(p++, 0x0020); stw_p(p++, 0x0080);
>-                                /* addiu[32] t0, $0, 0x80       */
>-
>-    /* 0x58 corresponds to GT_PCI0M0LD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9058);
>-                                /* sw t0, 0x58(t1)              */
>-
>-    stw_p(p++, 0x0020); stw_p(p++, 0x003f);
>-                                /* addiu[32] t0, $0, 0x3f       */
>-
>-    /* 0x60 corresponds to GT_PCI0M0HD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9060);
>-                                /* sw t0, 0x60(t1)              */
>-
>-    stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
>-                                /* addiu[32] t0, $0, 0xc1       */
>-
>-    /* 0x80 corresponds to GT_PCI0M1LD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9080);
>-                                /* sw t0, 0x80(t1)              */
>-
>-    stw_p(p++, 0x0020); stw_p(p++, 0x005e);
>-                                /* addiu[32] t0, $0, 0x5e       */
>-
>+#define cpu_to_gt32 cpu_to_be32
> #endif
>+    v = p;
> 
>-    /* 0x88 corresponds to GT_PCI0M1HD                          */
>-    stw_p(p++, 0x8422); stw_p(p++, 0x9088);
>-                                /* sw t0, 0x88(t1)              */
>+    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
>+    bl_gen_write_u32(&v, /* GT_ISD */
>+                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
>+                     cpu_to_gt32(0x1be00000 << 3));
>+
>+    /* setup MEM-to-PCI0 mapping */

+ as done by YAMON

That would preserve an existing comment and would document where these numbers come from (if the comment is correct).

Best regards,
Bernhard

>+    /* setup PCI0 io window to 0x18000000-0x181fffff */
>+    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
>+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
>+                     cpu_to_gt32(0x18000000 << 3));
>+    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
>+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
>+                     cpu_to_gt32(0x08000000 << 3));
>+    /* setup PCI0 mem windows */
>+    bl_gen_write_u32(&v, /* GT_PCI0M0LD */
>+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
>+                     cpu_to_gt32(0x10000000 << 3));
>+    bl_gen_write_u32(&v, /* GT_PCI0M0HD */
>+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
>+                     cpu_to_gt32(0x07e00000 << 3));
>+
>+    bl_gen_write_u32(&v, /* GT_PCI0M1LD */
>+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
>+                     cpu_to_gt32(0x18200000 << 3));
>+    bl_gen_write_u32(&v, /* GT_PCI0M1HD */
>+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
>+                     cpu_to_gt32(0x0bc00000 << 3));
>+
>+    p = (uint16_t *)v;
>+
>+#undef cpu_to_gt32
> 
>     stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
> 

Re: [PATCH-for-8.0 4/7] hw/mips/bootloader: Implement nanoMIPS LUI opcode

[Jiaxun Yang]

> 2022年12月10日 16:01，Philippe Mathieu-Daudé <philmd@linaro.org> 写道：
> 
> On 10/12/22 16:54, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>  hw/mips/bootloader.c | 29 ++++++++++++++++++++++++++---
>>  1 file changed, 26 insertions(+), 3 deletions(-)
>> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
>> index 7f7d938f2e..997e74ee52 100644
>> --- a/hw/mips/bootloader.c
>> +++ b/hw/mips/bootloader.c
>> @@ -120,11 +120,34 @@ static void bl_gen_jalr(void **p, bl_reg rs)
>>      bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
>>  }
>>  +static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
>> +{
>> +    uint16_t *p = (uint16_t *)*ptr;
>> +    uint32_t insn = 0;
> 
> Hmm we should check if imm20 fits in 20-bit.

Perhaps it will be easier to use 48bit addiu instruction to generate LI?

Thanks
- Jiaxun

> 
>> +    insn = deposit32(insn, 26, 6, 0b111000);
>> +    insn = deposit32(insn, 21, 5, rt);
>> +    insn = deposit32(insn, 12, 9, extract32(imm20, 12, 9));
>> +    insn = deposit32(insn, 2, 10, extract32(imm20, 21, 10));
>> +    insn = deposit32(insn, 0, 1, sextract32(imm20, 31, 1));
>> +
>> +    stw_p(p, insn >> 16);
>> +    p++;
>> +    stw_p(p, insn >> 0);
>> +    p++;
>> +
>> +    *ptr = p;
>> +}

Re: [PATCH-for-8.0 6/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Jiaxun Yang]

> 2022年12月10日 15:55，Philippe Mathieu-Daudé <philmd@linaro.org> 写道：
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/mips/bootloader.c | 25 ++++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index cc3df385df..541b59bf84 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -177,9 +177,32 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
>     }
> }
> 
> +static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t offset)
> +{
> +    uint16_t *p = (uint16_t *)*ptr;
> +    uint32_t insn = 0;
> +
> +    insn = deposit32(insn, 26, 6, 0b100001);
> +    insn = deposit32(insn, 21, 5, rt);
> +    insn = deposit32(insn, 16, 5, rs);
> +    insn = deposit32(insn, 12, 4, 0b1001);
> +    insn = deposit32(insn, 0, 12, offset);
> +
> +    stw_p(p, insn >> 16);
> +    p++;
> +    stw_p(p, insn >> 0);
> +    p++;

Think we can have a helper function like st_nm32_p.

Thanks
- Jiaxun

> +
> +    *ptr = p;
> +}
> +
> static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
> {
> -    bl_gen_i_type(p, 0x2b, base, rt, offset);
> +    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
> +        bl_gen_sw_nm(p, rt, base, offset);
> +    } else {
> +        bl_gen_i_type(p, 0x2b, base, rt, offset);
> +    }
> }
> 
> static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
> -- 
> 2.38.1
> 

Re: [PATCH-for-8.0 2/7] hw/mips/bootloader: Pass 32-bit immediate value to LUI opcode generator

[Richard Henderson]

On 12/10/22 09:54, Philippe Mathieu-Daudé wrote:
> -static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
> +static void bl_gen_lui(void **p, bl_reg rt, uint32_t imm32)
>   {
>       /* R6: It's a alias of AUI with RS = 0 */
> -    bl_gen_i_type(p, 0x0f, 0, rt, imm);
> +    assert(imm32 <= UINT16_MAX);
> +    bl_gen_i_type(p, 0x0f, 0, rt, extract32(imm32, 16, 16));

This assert is obviously incorrect.  You wanted to test

    (imm32 & 0xffff) == 0


r~

Re: [PATCH-for-8.0 3/7] hw/mips/bootloader: Implement nanoMIPS NOP opcode

[Richard Henderson]

On 12/10/22 09:54, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/bootloader.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index 3a4573118c..7f7d938f2e 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -59,7 +59,11 @@ static void bl_gen_nop(void **ptr)
>   {
>       uint32_t *p = (uint32_t *)*ptr;
>   
> -    stl_p(p, 0);
> +    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
> +        stl_p(p, 0x8000c000);
> +    } else {
> +        stl_p(p, 0);
> +    }
>       p++;
>       *ptr = p;
>   }

Re: [PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Richard Henderson]

On 12/10/22 10:02, Philippe Mathieu-Daudé wrote:
> On 10/12/22 16:55, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   hw/mips/bootloader.c | 24 +++++++++++++++++++++++-
>>   1 file changed, 23 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
>> index 997e74ee52..cc3df385df 100644
>> --- a/hw/mips/bootloader.c
>> +++ b/hw/mips/bootloader.c
>> @@ -150,9 +150,31 @@ static void bl_gen_lui(void **p, bl_reg rt, uint32_t imm32)
>>       }
>>   }
>> +static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm)
>> +{
>> +    uint16_t *p = (uint16_t *)*ptr;
>> +    uint32_t insn = 0;
> 
> Similarly, we should check whether imm fits in 12-bit.

I think you should simply split at the "li" level instead of lui+ori.


r~

> 
>> +    insn = deposit32(insn, 26, 6, 0b100000);
>> +    insn = deposit32(insn, 21, 5, rt);
>> +    insn = deposit32(insn, 16, 5, rs);
>> +    insn = deposit32(insn, 0, 12, imm);
>> +
>> +    stw_p(p, insn >> 16);
>> +    p++;
>> +    stw_p(p, insn >> 0);
>> +    p++;
>> +
>> +    *ptr = p;
>> +}
> 
> 

Re: [PATCH-for-8.0 1/7] hw/mips/bootloader: Handle buffers as opaque arrays

[Philippe Mathieu-Daudé]

On 11/12/22 01:16, BALATON Zoltan wrote:
> On Sat, 10 Dec 2022, Philippe Mathieu-Daudé wrote:
>> It is irrelevant to the API what the buffers to fill are made of.
>> In particular, some MIPS ISA have 16-bit wide instructions.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> hw/mips/bootloader.c         | 55 +++++++++++++++++++++---------------
>> hw/mips/malta.c              | 19 +++++++------
>> include/hw/mips/bootloader.h | 10 +++----
>> 3 files changed, 48 insertions(+), 36 deletions(-)
>>
>> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
>> index f5f42f2bf2..fc14eb0894 100644
>> --- a/hw/mips/bootloader.c
>> +++ b/hw/mips/bootloader.c
>> @@ -55,16 +55,20 @@ static bool bootcpu_supports_isa(uint64_t isa_mask)
>> }
>>
>> /* Base types */
>> -static void bl_gen_nop(uint32_t **p)
>> +static void bl_gen_nop(void **ptr)
>> {
>> -    stl_p(*p, 0);
>> -    *p = *p + 1;
>> +    uint32_t *p = (uint32_t *)*ptr;
> 
> Do you need to cast void * ? I thought in C that's not necessary but 
> maybe I'm missing why it's needed here.

No, you are right.

>> +
>> +    stl_p(p, 0);
>> +    p++;
>> +    *ptr = p;
> 
> Do you need a cast here though? (You could also combine the ++ either in 
> stl_p(p++, 0) or *ptr = ++p but not sure you want to.)

If the compiler were unhappy it would have complained :)

Re: [PATCH-for-8.0 5/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Philippe Mathieu-Daudé]

On 11/12/22 17:24, Richard Henderson wrote:
> On 12/10/22 10:02, Philippe Mathieu-Daudé wrote:
>> On 10/12/22 16:55, Philippe Mathieu-Daudé wrote:
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>>   hw/mips/bootloader.c | 24 +++++++++++++++++++++++-
>>>   1 file changed, 23 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
>>> index 997e74ee52..cc3df385df 100644
>>> --- a/hw/mips/bootloader.c
>>> +++ b/hw/mips/bootloader.c
>>> @@ -150,9 +150,31 @@ static void bl_gen_lui(void **p, bl_reg rt, 
>>> uint32_t imm32)
>>>       }
>>>   }
>>> +static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t 
>>> imm)
>>> +{
>>> +    uint16_t *p = (uint16_t *)*ptr;
>>> +    uint32_t insn = 0;
>>
>> Similarly, we should check whether imm fits in 12-bit.
> 
> I think you should simply split at the "li" level instead of lui+ori.

Clever.

Re: [PATCH-for-8.0 6/7] hw/mips/bootloader: Implement nanoMIPS SW opcode

[Philippe Mathieu-Daudé]

On 11/12/22 11:40, Jiaxun Yang wrote:
> 
> 
>> 2022年12月10日 15:55，Philippe Mathieu-Daudé <philmd@linaro.org> 写道：
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> hw/mips/bootloader.c | 25 ++++++++++++++++++++++++-
>> 1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
>> index cc3df385df..541b59bf84 100644
>> --- a/hw/mips/bootloader.c
>> +++ b/hw/mips/bootloader.c
>> @@ -177,9 +177,32 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
>>      }
>> }
>>
>> +static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t offset)
>> +{
>> +    uint16_t *p = (uint16_t *)*ptr;
>> +    uint32_t insn = 0;
>> +
>> +    insn = deposit32(insn, 26, 6, 0b100001);
>> +    insn = deposit32(insn, 21, 5, rt);
>> +    insn = deposit32(insn, 16, 5, rs);
>> +    insn = deposit32(insn, 12, 4, 0b1001);
>> +    insn = deposit32(insn, 0, 12, offset);
>> +
>> +    stw_p(p, insn >> 16);
>> +    p++;
>> +    stw_p(p, insn >> 0);
>> +    p++;
> 
> Think we can have a helper function like st_nm32_p.

Good idea.