[PATCH 01/10] [ARM] pxa: extend to support 96 IRQs

[PATCH 01/10] [ARM] pxa: extend to support 96 IRQs

[Haojian Zhuang]

[PATCH 01/10] [ARM] pxa: extend to support 96 IRQs

[Eric Miao]

On Thu, Apr 29, 2010 at 4:15 PM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> From ea9bcffc52bb7ee542c3615530e1c8e87100c884 Mon Sep 17 00:00:00 2001
> From: Haojian Zhuang <haojian.zhuang@marvell.com>
> Date: Thu, 29 Apr 2010 10:22:12 -0400
> Subject: [PATCH] [ARM] pxa: extend to support 96 IRQs
>
> Extend to support 96 IRQs for PXA950.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
> ---
> ?arch/arm/mach-pxa/irq.c ? ?| ? ?9 ++++++---
> ?arch/arm/mach-pxa/pxa3xx.c | ? ?2 +-
> ?2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
> index 1beb40f..bb5a0c7 100644
> --- a/arch/arm/mach-pxa/irq.c
> +++ b/arch/arm/mach-pxa/irq.c
> @@ -27,9 +27,12 @@
>
> ?#define MAX_INTERNAL_IRQS ? ? ?128
>
> -#define IRQ_BIT(n) ? ? (((n) - PXA_IRQ(0)) & 0x1f)
> -#define _ICMR(n) ? ? ? (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
> -#define _ICLR(n) ? ? ? (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
> +#define _IDX(n) ? ? ? ? ? ? ? ?((n) - PXA_IRQ(0))
> +#define IRQ_BIT(n) ? ? (_IDX(n) & 0x1f)
> +#define _ICMR(n) ? ? ? (*((_IDX(n) < 32) ? &ICMR ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? : ((_IDX(n) < 64) ? &ICMR2 : &ICMR3)))
> +#define _ICLR(n) ? ? ? (*((_IDX(n) < 32) ? &ICLR ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? : ((_IDX(n) < 64) ? &ICLR2 : &ICLR3)))
>

Instead of making these macros more complicated, I'd prefer that
we separate them as three IRQ register banks, with the base I/O
address of these banks in irq_desc.chip_data or some where.

> ?/*
> ?* This is for peripheral IRQs internal to the PXA chip.
> diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
> index 4d7c03e..6285951 100644
> --- a/arch/arm/mach-pxa/pxa3xx.c
> +++ b/arch/arm/mach-pxa/pxa3xx.c
> @@ -581,7 +581,7 @@ void __init pxa3xx_init_irq(void)
> ? ? ? ?value |= (1 << 6);
> ? ? ? ?__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
>
> - ? ? ? pxa_init_irq(56, pxa3xx_set_wake);
> + ? ? ? pxa_init_irq(96, pxa3xx_set_wake);
> ? ? ? ?pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
> ? ? ? ?pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
> ?}
> --
> 1.5.6.5
>

[PATCH 01/10] [ARM] pxa: extend to support 96 IRQs

[Haojian Zhuang]

On Tue, May 4, 2010 at 9:28 PM, Eric Miao <eric.y.miao@gmail.com> wrote:
> On Thu, Apr 29, 2010 at 4:15 PM, Haojian Zhuang
> <haojian.zhuang@gmail.com> wrote:
>> From ea9bcffc52bb7ee542c3615530e1c8e87100c884 Mon Sep 17 00:00:00 2001
>> From: Haojian Zhuang <haojian.zhuang@marvell.com>
>> Date: Thu, 29 Apr 2010 10:22:12 -0400
>> Subject: [PATCH] [ARM] pxa: extend to support 96 IRQs
>>
>> Extend to support 96 IRQs for PXA950.
>>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
>> ---
>> ?arch/arm/mach-pxa/irq.c ? ?| ? ?9 ++++++---
>> ?arch/arm/mach-pxa/pxa3xx.c | ? ?2 +-
>> ?2 files changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
>> index 1beb40f..bb5a0c7 100644
>> --- a/arch/arm/mach-pxa/irq.c
>> +++ b/arch/arm/mach-pxa/irq.c
>> @@ -27,9 +27,12 @@
>>
>> ?#define MAX_INTERNAL_IRQS ? ? ?128
>>
>> -#define IRQ_BIT(n) ? ? (((n) - PXA_IRQ(0)) & 0x1f)
>> -#define _ICMR(n) ? ? ? (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
>> -#define _ICLR(n) ? ? ? (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
>> +#define _IDX(n) ? ? ? ? ? ? ? ?((n) - PXA_IRQ(0))
>> +#define IRQ_BIT(n) ? ? (_IDX(n) & 0x1f)
>> +#define _ICMR(n) ? ? ? (*((_IDX(n) < 32) ? &ICMR ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? ? : ((_IDX(n) < 64) ? &ICMR2 : &ICMR3)))
>> +#define _ICLR(n) ? ? ? (*((_IDX(n) < 32) ? &ICLR ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? ? : ((_IDX(n) < 64) ? &ICLR2 : &ICLR3)))
>>
>
> Instead of making these macros more complicated, I'd prefer that
> we separate them as three IRQ register banks, with the base I/O
> address of these banks in irq_desc.chip_data or some where.
>

If we use irq_desc.chip_data, we have to divide init_irq() into more
parts. Each part is focus on one interrupt bank registers. The
assignment of interrupt priority have to be divided into more parts.
And saving interrupt registers in suspend() may be more complex.

Thanks
Haojian

[PATCH 01/10] [ARM] pxa: extend to support 96 IRQs

[Eric Miao]

>> Instead of making these macros more complicated, I'd prefer that
>> we separate them as three IRQ register banks, with the base I/O
>> address of these banks in irq_desc.chip_data or some where.
>>
>
> If we use irq_desc.chip_data, we have to divide init_irq() into more
> parts. Each part is focus on one interrupt bank registers. The
> assignment of interrupt priority have to be divided into more parts.
> And saving interrupt registers in suspend() may be more complex.
>

Haojian,

Could you please help test a bit the following patch? Might be applicable
only to my 'devel' branch. Thanks.

commit c9d2b6b09297ac00e73289db38d692cc648619de
Author: Eric Miao <eric.y.miao@gmail.com>
Date: ? Wed May 5 16:44:22 2010 +0800

? ?[ARM] pxa: sanitize IRQ registers access based on offset

? ?Signed-off-by: Eric Miao <eric.y.miao@gmail.com>

diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 1beb40f..7db9416 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -16,20 +16,36 @@
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
+#include <linux/io.h>
+#include <linux/irq.h>

#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
+#include <mach/irqs.h>
#include <mach/gpio.h>
-#include <mach/regs-intc.h>

#include "generic.h"

+#define IRQ_BASE (void __iomem *)io_p2v(0x40d00000)
+
+#define ICIP (0x000)
+#define ICMR (0x004)
+#define ICLR (0x008)
+#define ICFR (0x00c)
+#define ICPR (0x010)
+#define ICCR (0x014)
+#define ICHP (0x018)
+#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
+ ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
+ ? ? ?(0x144 + (((i) - 64) << 2)))
+#define IPR_VALID (1 << 31)
+
#define MAX_INTERNAL_IRQS 128
+#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)

-#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
-#define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
-#define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
+static inline int cpu_has_ipr(void)
+{
+ return cpu_is_pxa27x() || cpu_is_pxa3xx();
+}

/*
?* This is for peripheral IRQs internal to the PXA chip.
@@ -39,12 +55,20 @@ static int pxa_internal_irq_nr;

static void pxa_mask_irq(unsigned int irq)
{
- _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
+ void __iomem *base = get_irq_chip_data(irq);
+ uint32_t icmr = __raw_readl(base + ICMR);
+
+ icmr &= ~(1 << IRQ_BIT(irq));
+ __raw_writel(icmr, base + ICMR);
}

static void pxa_unmask_irq(unsigned int irq)
{
- _ICMR(irq) |= 1 << IRQ_BIT(irq);
+ void __iomem *base = get_irq_chip_data(irq);
+ uint32_t icmr = __raw_readl(base + ICMR);
+
+ icmr |= 1 << IRQ_BIT(irq);
+ __raw_writel(icmr, base + ICMR);
}

static struct irq_chip pxa_internal_irq_chip = {
@@ -86,12 +110,16 @@ static void pxa_ack_low_gpio(unsigned int irq)

static void pxa_mask_low_gpio(unsigned int irq)
{
- ICMR &= ~(1 << (irq - PXA_IRQ(0)));
+ struct irq_desc *desc = irq_to_desc(irq);
+
+ desc->chip->mask(irq);
}

static void pxa_unmask_low_gpio(unsigned int irq)
{
- ICMR |= 1 << (irq - PXA_IRQ(0));
+ struct irq_desc *desc = irq_to_desc(irq);
+
+ desc->chip->unmask(irq);
}

static struct irq_chip pxa_low_gpio_chip = {
@@ -120,34 +148,47 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
pxa_low_gpio_chip.set_wake = fn;
}

+static inline void __iomem *irq_base(int i)
+{
+ static unsigned long phys_base[] = {
+ 0x40d00000,
+ 0x40d0009c,
+ 0x40d00130,
+ };
+
+ return (void __iomem *)io_p2v(phys_base[i >> 5]);
+}
+
void __init pxa_init_irq(int irq_nr, set_wake_t fn)
{
- int irq, i;
+ int irq, i, n;

BUG_ON(irq_nr > MAX_INTERNAL_IRQS);

pxa_internal_irq_nr = irq_nr;

- for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
- _ICMR(irq) = 0; /* disable all IRQs */
- _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
- }
+ for (n = 0; n < irq_nr; n += 32) {
+ void __iomem *base = irq_base(n);

- /* initialize interrupt priority */
- if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
- for (i = 0; i < irq_nr; i++)
- IPR(i) = i | (1 << 31);
- }
+ __raw_writel(0, base + ICMR); /* disable all IRQs */
+ __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */

- /* only unmasked interrupts kick us out of idle */
- ICCR = 1;
+ for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
+ /* initialize interrupt priority */
+ if (cpu_has_ipr())
+ __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));

- for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
- set_irq_chip(irq, &pxa_internal_irq_chip);
- set_irq_handler(irq, handle_level_irq);
- set_irq_flags(irq, IRQF_VALID);
+ irq = PXA_IRQ(i);
+ set_irq_chip(irq, &pxa_internal_irq_chip);
+ set_irq_chip_data(irq, base);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
}

+ /* only unmasked interrupts kick us out of idle */
+ __raw_writel(1, irq_base(0) + ICCR);
+
pxa_internal_irq_chip.set_wake = fn;
pxa_init_low_gpio_irq(fn);
}
@@ -158,36 +199,38 @@ static unsigned long saved_ipr[MAX_INTERNAL_IRQS];

static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
{
- int i, irq = PXA_IRQ(0);
+ int i;

- for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
- saved_icmr[i] = _ICMR(irq);
- _ICMR(irq) = 0;
+ for (i = 0; i < pxa_internal_irq_nr; i += 32) {
+ void __iomem *base = irq_base(i);
+
+ saved_icmr[i] = __raw_readl(base + ICMR);
+ __raw_writel(0, base + ICMR);
}

- if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
+ if (cpu_has_ipr())
for (i = 0; i < pxa_internal_irq_nr; i++)
- saved_ipr[i] = IPR(i);
- }
+ saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));

return 0;
}

static int pxa_irq_resume(struct sys_device *dev)
{
- int i, irq = PXA_IRQ(0);
+ int i;

- if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
- for (i = 0; i < pxa_internal_irq_nr; i++)
- IPR(i) = saved_ipr[i];
- }
+ for (i = 0; i < pxa_internal_irq_nr; i += 32) {
+ void __iomem *base = irq_base(i);

- for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
- _ICMR(irq) = saved_icmr[i];
- _ICLR(irq) = 0;
+ __raw_writel(saved_icmr[i], base + ICMR);
+ __raw_writel(0, base + ICLR);
}

- ICCR = 1;
+ if (cpu_has_ipr())
+ for (i = 0; i < pxa_internal_irq_nr; i++)
+ __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
+
+ __raw_writel(1, IRQ_BASE + ICCR);
return 0;
}
#else
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