* [PATCH v4 0/5] Provide sdhci driver for mmp2 and pxa9xx
@ 2011-06-08 9:41 ` Zhangfei Gao
0 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:41 UTC (permalink / raw)
To: Arnd Bergmann, Nicolas Pitre, Philip Rakity, Wolfram Sang,
Chris Ball, linux-mmc
Cc: Zhangfei Gao
v3->v4
Update patch sequence and mmp2_defconfig
update driver/mmc/host/Kconfig
Remove get_ro
The patches to provide separate sdhci driver for mmp2 and pxa910
based on sdhci-platfm.
Rename to sdhci-pxav3.c and sdhci-pxav2.c
Remove obsolete sdhci-pxa.c, which is used to share among pxa serious, since
under this method, platform difference have to be put under arch/arm,
which is not easy to track.
As a result, mmp2 mmc resource should be updated accordingly.
Zhangfei Gao (5):
mmc: support sdhci-pxav3.c
mmc: support sdhci-pxav2.c
ARM: mmp2: update mmp2 mmc resource
mmc: delete obsolete sdhci-pxa.c
ARM: mmp2: update mmp2_defconfig to support mmc
arch/arm/configs/mmp2_defconfig | 9 +-
arch/arm/mach-mmp/brownstone.c | 10 +-
arch/arm/mach-mmp/jasper.c | 2 +-
arch/arm/mach-mmp/mmp2.c | 16 +-
arch/arm/plat-pxa/include/plat/sdhci.h | 35 +++-
drivers/mmc/host/Kconfig | 24 ++-
drivers/mmc/host/Makefile | 3 +-
drivers/mmc/host/sdhci-pxa.c | 303 --------------------------------
drivers/mmc/host/sdhci-pxav2.c | 244 +++++++++++++++++++++++++
drivers/mmc/host/sdhci-pxav3.c | 289 ++++++++++++++++++++++++++++++
10 files changed, 609 insertions(+), 326 deletions(-)
delete mode 100644 drivers/mmc/host/sdhci-pxa.c
create mode 100644 drivers/mmc/host/sdhci-pxav2.c
create mode 100644 drivers/mmc/host/sdhci-pxav3.c
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 0/5] Provide sdhci driver for mmp2 and pxa9xx
@ 2011-06-08 9:41 ` Zhangfei Gao
0 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:41 UTC (permalink / raw)
To: linux-arm-kernel
v3->v4
Update patch sequence and mmp2_defconfig
update driver/mmc/host/Kconfig
Remove get_ro
The patches to provide separate sdhci driver for mmp2 and pxa910
based on sdhci-platfm.
Rename to sdhci-pxav3.c and sdhci-pxav2.c
Remove obsolete sdhci-pxa.c, which is used to share among pxa serious, since
under this method, platform difference have to be put under arch/arm,
which is not easy to track.
As a result, mmp2 mmc resource should be updated accordingly.
Zhangfei Gao (5):
mmc: support sdhci-pxav3.c
mmc: support sdhci-pxav2.c
ARM: mmp2: update mmp2 mmc resource
mmc: delete obsolete sdhci-pxa.c
ARM: mmp2: update mmp2_defconfig to support mmc
arch/arm/configs/mmp2_defconfig | 9 +-
arch/arm/mach-mmp/brownstone.c | 10 +-
arch/arm/mach-mmp/jasper.c | 2 +-
arch/arm/mach-mmp/mmp2.c | 16 +-
arch/arm/plat-pxa/include/plat/sdhci.h | 35 +++-
drivers/mmc/host/Kconfig | 24 ++-
drivers/mmc/host/Makefile | 3 +-
drivers/mmc/host/sdhci-pxa.c | 303 --------------------------------
drivers/mmc/host/sdhci-pxav2.c | 244 +++++++++++++++++++++++++
drivers/mmc/host/sdhci-pxav3.c | 289 ++++++++++++++++++++++++++++++
10 files changed, 609 insertions(+), 326 deletions(-)
delete mode 100644 drivers/mmc/host/sdhci-pxa.c
create mode 100644 drivers/mmc/host/sdhci-pxav2.c
create mode 100644 drivers/mmc/host/sdhci-pxav3.c
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 1/5] mmc: support sdhci-pxav3.c
2011-06-08 9:41 ` Zhangfei Gao
@ 2011-06-08 9:41 ` Zhangfei Gao
-1 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:41 UTC (permalink / raw)
To: Arnd Bergmann, Nicolas Pitre, Wolfram Sang, Chris Ball, linux-mmc
Cc: Zhangfei Gao, Philip Rakity
SDHCI driver for PXAV3 SoCs, such as MMP2, the driver based on sdhci-pltfm to handle resource etc.
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Philip Rakity <prakity@marvell.com>
---
arch/arm/plat-pxa/include/plat/sdhci.h | 35 ++++-
drivers/mmc/host/Kconfig | 12 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-pxav3.c | 289 ++++++++++++++++++++++++++++++++
4 files changed, 332 insertions(+), 5 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-pxav3.c
diff --git a/arch/arm/plat-pxa/include/plat/sdhci.h b/arch/arm/plat-pxa/include/plat/sdhci.h
index 1ab332e..6873dc5 100644
--- a/arch/arm/plat-pxa/include/plat/sdhci.h
+++ b/arch/arm/plat-pxa/include/plat/sdhci.h
@@ -15,21 +15,46 @@
/* pxa specific flag */
/* Require clock free running */
-#define PXA_FLAG_DISABLE_CLOCK_GATING (1<<0)
-
+#define PXA_FLAG_ENABLE_CLOCK_GATING (1<<0)
+/* card alwayes wired to host, like on-chip emmc */
+#define PXA_FLAG_CARD_PERMANENT (1<<1)
/* Board design supports 8-bit data on SD/SDIO BUS */
#define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2)
/*
* struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
- * @max_speed: the maximum speed supported
- * @quirks: quirks of specific device
* @flags: flags for platform requirement
+ * @clk_delay_cycles:
+ * mmp2: each step is roughly 100ps, 5bits width
+ * pxa910: each step is 1ns, 4bits width
+ * @clk_delay_sel: select clk_delay, used on pxa910
+ * 0: choose feedback clk
+ * 1: choose feedback clk + delay value
+ * 2: choose internal clk
+ * @clk_delay_enable: enable clk_delay or not, used on pxa910
+ * @ext_cd_gpio: gpio pin used for external CD line
+ * @ext_cd_gpio_invert: invert values for external CD gpio line
+ * @max_speed: the maximum speed supported
+ * @host_caps: Standard MMC host capabilities bit field.
+ * @quirks: quirks of platfrom
+ * @pm_caps: pm_caps of platfrom
*/
struct sdhci_pxa_platdata {
+ unsigned int flags;
+ unsigned int clk_delay_cycles;
+ unsigned int clk_delay_sel;
+ bool clk_delay_enable;
+ unsigned int ext_cd_gpio;
+ bool ext_cd_gpio_invert;
unsigned int max_speed;
+ unsigned int host_caps;
unsigned int quirks;
- unsigned int flags;
+ unsigned int pm_caps;
+};
+
+struct sdhci_pxa {
+ u8 clk_enable;
+ u8 power_mode;
};
#endif /* __PLAT_PXA_SDHCI_H */
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 74e77c9..6525a04 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -193,6 +193,18 @@ config MMC_SDHCI_PXA
If unsure, say N.
+config MMC_SDHCI_PXAV3
+ tristate "Marvell MMP2 SD Host Controller support (PXAV3)"
+ select MMC_SDHCI
+ select MMC_SDHCI_PLTFM
+ default CPU_MMP2
+ help
+ This selects the Marvell(R) PXAV3 SD Host Controller.
+ If you have a MMP2 platform with SD Host Controller
+ and a card slot, say Y or M here.
+
+ If unsure, say N.
+
config MMC_SDHCI_SPEAR
tristate "SDHCI support on ST SPEAr platform"
depends on MMC_SDHCI && PLAT_SPEAR
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index bf479ab..688cc52 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
obj-$(CONFIG_MMC_SDHCI_PXA) += sdhci-pxa.o
+obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
new file mode 100644
index 0000000..901f00f
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2010 Marvell International Ltd.
+ * Zhangfei Gao <zhangfei.gao@marvell.com>
+ * Kevin Wang <dwang4@marvell.com>
+ * Mingwei Wang <mwwang@marvell.com>
+ * Philip Rakity <prakity@marvell.com>
+ * Mark Brown <markb@marvell.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <plat/sdhci.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+
+#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
+#define SDCLK_SEL 0x100
+#define SDCLK_DELAY_SHIFT 9
+#define SDCLK_DELAY_MASK 0x1f
+
+#define SD_CFG_FIFO_PARAM 0x100
+#define SDCFG_GEN_PAD_CLK_ON (1<<6)
+#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
+#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
+
+#define SD_SPI_MODE 0x108
+#define SD_CE_ATA_1 0x10C
+
+#define SD_CE_ATA_2 0x10E
+#define SDCE_MISC_INT (1<<2)
+#define SDCE_MISC_INT_EN (1<<1)
+
+static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
+{
+ struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
+ if (mask == SDHCI_RESET_ALL) {
+ /*
+ * tune timing of read data/command when crc error happen
+ * no performance impact
+ */
+ if (pdata && 0 != pdata->clk_delay_cycles) {
+ u16 tmp;
+
+ tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+ tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
+ << SDCLK_DELAY_SHIFT;
+ tmp |= SDCLK_SEL;
+ writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+ }
+ }
+}
+
+#define MAX_WAIT_COUNT 5
+static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
+ u16 tmp;
+ int count;
+
+ if (pxa->power_mode == MMC_POWER_UP
+ && power_mode == MMC_POWER_ON) {
+
+ dev_dbg(mmc_dev(host->mmc),
+ "%s: slot->power_mode = %d,"
+ "ios->power_mode = %d\n",
+ __func__,
+ pxa->power_mode,
+ power_mode);
+
+ /* set we want notice of when 74 clocks are sent */
+ tmp = readw(host->ioaddr + SD_CE_ATA_2);
+ tmp |= SDCE_MISC_INT_EN;
+ writew(tmp, host->ioaddr + SD_CE_ATA_2);
+
+ /* start sending the 74 clocks */
+ tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
+ tmp |= SDCFG_GEN_PAD_CLK_ON;
+ writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
+
+ /* slowest speed is about 100KHz or 10usec per clock */
+ udelay(740);
+ count = 0;
+
+ while (count++ < MAX_WAIT_COUNT) {
+ if ((readw(host->ioaddr + SD_CE_ATA_2)
+ & SDCE_MISC_INT) == 0)
+ break;
+ udelay(10);
+ }
+
+ if (count == MAX_WAIT_COUNT)
+ dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
+
+ /* clear the interrupt bit if posted */
+ tmp = readw(host->ioaddr + SD_CE_ATA_2);
+ tmp |= SDCE_MISC_INT;
+ writew(tmp, host->ioaddr + SD_CE_ATA_2);
+ }
+ pxa->power_mode = power_mode;
+}
+
+static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
+{
+ u16 ctrl_2;
+
+ /*
+ * Set V18_EN -- UHS modes do not work without this.
+ * does not change signaling voltage
+ */
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ /* Select Bus Speed Mode for host */
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ switch (uhs) {
+ case MMC_TIMING_UHS_SDR12:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+ break;
+ case MMC_TIMING_UHS_SDR25:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+ break;
+ case MMC_TIMING_UHS_SDR50:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
+ break;
+ case MMC_TIMING_UHS_SDR104:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
+ break;
+ }
+
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+ dev_dbg(mmc_dev(host->mmc),
+ "%s uhs = %d, ctrl_2 = %04X\n",
+ __func__, uhs, ctrl_2);
+
+ return 0;
+}
+
+static struct sdhci_ops pxav3_sdhci_ops = {
+ .platform_reset_exit = pxav3_set_private_registers,
+ .set_uhs_signaling = pxav3_set_uhs_signaling,
+ .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
+};
+
+static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct sdhci_host *host = NULL;
+ struct sdhci_pxa *pxa = NULL;
+ int ret;
+ struct clk *clk;
+
+ pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
+ if (!pxa)
+ return -ENOMEM;
+
+ host = sdhci_pltfm_init(pdev, NULL);
+ if (IS_ERR(host)) {
+ kfree(pxa);
+ return PTR_ERR(host);
+ }
+ pltfm_host = sdhci_priv(host);
+ pltfm_host->priv = pxa;
+
+ clk = clk_get(dev, "PXA-SDHCLK");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get io clock\n");
+ ret = PTR_ERR(clk);
+ goto err_clk_get;
+ }
+ pltfm_host->clk = clk;
+ clk_enable(clk);
+
+ host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
+ | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
+
+ /* enable 1/8V DDR capable */
+ host->mmc->caps |= MMC_CAP_1_8V_DDR;
+
+ if (pdata) {
+ if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
+ /* on-chip device */
+ host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+ host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+ }
+
+ /* If slot design supports 8 bit data, indicate this to MMC. */
+ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
+ host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+ if (pdata->quirks)
+ host->quirks |= pdata->quirks;
+ if (pdata->host_caps)
+ host->mmc->caps |= pdata->host_caps;
+ if (pdata->pm_caps)
+ host->mmc->pm_caps |= pdata->pm_caps;
+ }
+
+ host->ops = &pxav3_sdhci_ops;
+
+ ret = sdhci_add_host(host);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add host\n");
+ goto err_add_host;
+ }
+
+ platform_set_drvdata(pdev, host);
+
+ return 0;
+
+err_add_host:
+ clk_disable(clk);
+ clk_put(clk);
+err_clk_get:
+ sdhci_pltfm_free(pdev);
+ kfree(pxa);
+ return ret;
+}
+
+static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
+
+ sdhci_remove_host(host, 1);
+
+ clk_disable(pltfm_host->clk);
+ clk_put(pltfm_host->clk);
+ sdhci_pltfm_free(pdev);
+ kfree(pxa);
+
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver sdhci_pxav3_driver = {
+ .driver = {
+ .name = "sdhci-pxav3",
+ .owner = THIS_MODULE,
+ },
+ .probe = sdhci_pxav3_probe,
+ .remove = __devexit_p(sdhci_pxav3_remove),
+#ifdef CONFIG_PM
+ .suspend = sdhci_pltfm_suspend,
+ .resume = sdhci_pltfm_resume,
+#endif
+};
+static int __init sdhci_pxav3_init(void)
+{
+ return platform_driver_register(&sdhci_pxav3_driver);
+}
+
+static void __exit sdhci_pxav3_exit(void)
+{
+ platform_driver_unregister(&sdhci_pxav3_driver);
+}
+
+module_init(sdhci_pxav3_init);
+module_exit(sdhci_pxav3_exit);
+
+MODULE_DESCRIPTION("SDHCI driver for pxav3");
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_LICENSE("GPL v2");
+
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 1/5] mmc: support sdhci-pxav3.c
@ 2011-06-08 9:41 ` Zhangfei Gao
0 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:41 UTC (permalink / raw)
To: linux-arm-kernel
SDHCI driver for PXAV3 SoCs, such as MMP2, the driver based on sdhci-pltfm to handle resource etc.
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Philip Rakity <prakity@marvell.com>
---
arch/arm/plat-pxa/include/plat/sdhci.h | 35 ++++-
drivers/mmc/host/Kconfig | 12 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-pxav3.c | 289 ++++++++++++++++++++++++++++++++
4 files changed, 332 insertions(+), 5 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-pxav3.c
diff --git a/arch/arm/plat-pxa/include/plat/sdhci.h b/arch/arm/plat-pxa/include/plat/sdhci.h
index 1ab332e..6873dc5 100644
--- a/arch/arm/plat-pxa/include/plat/sdhci.h
+++ b/arch/arm/plat-pxa/include/plat/sdhci.h
@@ -15,21 +15,46 @@
/* pxa specific flag */
/* Require clock free running */
-#define PXA_FLAG_DISABLE_CLOCK_GATING (1<<0)
-
+#define PXA_FLAG_ENABLE_CLOCK_GATING (1<<0)
+/* card alwayes wired to host, like on-chip emmc */
+#define PXA_FLAG_CARD_PERMANENT (1<<1)
/* Board design supports 8-bit data on SD/SDIO BUS */
#define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2)
/*
* struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
- * @max_speed: the maximum speed supported
- * @quirks: quirks of specific device
* @flags: flags for platform requirement
+ * @clk_delay_cycles:
+ * mmp2: each step is roughly 100ps, 5bits width
+ * pxa910: each step is 1ns, 4bits width
+ * @clk_delay_sel: select clk_delay, used on pxa910
+ * 0: choose feedback clk
+ * 1: choose feedback clk + delay value
+ * 2: choose internal clk
+ * @clk_delay_enable: enable clk_delay or not, used on pxa910
+ * @ext_cd_gpio: gpio pin used for external CD line
+ * @ext_cd_gpio_invert: invert values for external CD gpio line
+ * @max_speed: the maximum speed supported
+ * @host_caps: Standard MMC host capabilities bit field.
+ * @quirks: quirks of platfrom
+ * @pm_caps: pm_caps of platfrom
*/
struct sdhci_pxa_platdata {
+ unsigned int flags;
+ unsigned int clk_delay_cycles;
+ unsigned int clk_delay_sel;
+ bool clk_delay_enable;
+ unsigned int ext_cd_gpio;
+ bool ext_cd_gpio_invert;
unsigned int max_speed;
+ unsigned int host_caps;
unsigned int quirks;
- unsigned int flags;
+ unsigned int pm_caps;
+};
+
+struct sdhci_pxa {
+ u8 clk_enable;
+ u8 power_mode;
};
#endif /* __PLAT_PXA_SDHCI_H */
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 74e77c9..6525a04 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -193,6 +193,18 @@ config MMC_SDHCI_PXA
If unsure, say N.
+config MMC_SDHCI_PXAV3
+ tristate "Marvell MMP2 SD Host Controller support (PXAV3)"
+ select MMC_SDHCI
+ select MMC_SDHCI_PLTFM
+ default CPU_MMP2
+ help
+ This selects the Marvell(R) PXAV3 SD Host Controller.
+ If you have a MMP2 platform with SD Host Controller
+ and a card slot, say Y or M here.
+
+ If unsure, say N.
+
config MMC_SDHCI_SPEAR
tristate "SDHCI support on ST SPEAr platform"
depends on MMC_SDHCI && PLAT_SPEAR
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index bf479ab..688cc52 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
obj-$(CONFIG_MMC_SDHCI_PXA) += sdhci-pxa.o
+obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
new file mode 100644
index 0000000..901f00f
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2010 Marvell International Ltd.
+ * Zhangfei Gao <zhangfei.gao@marvell.com>
+ * Kevin Wang <dwang4@marvell.com>
+ * Mingwei Wang <mwwang@marvell.com>
+ * Philip Rakity <prakity@marvell.com>
+ * Mark Brown <markb@marvell.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <plat/sdhci.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+
+#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
+#define SDCLK_SEL 0x100
+#define SDCLK_DELAY_SHIFT 9
+#define SDCLK_DELAY_MASK 0x1f
+
+#define SD_CFG_FIFO_PARAM 0x100
+#define SDCFG_GEN_PAD_CLK_ON (1<<6)
+#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
+#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
+
+#define SD_SPI_MODE 0x108
+#define SD_CE_ATA_1 0x10C
+
+#define SD_CE_ATA_2 0x10E
+#define SDCE_MISC_INT (1<<2)
+#define SDCE_MISC_INT_EN (1<<1)
+
+static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
+{
+ struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
+ if (mask == SDHCI_RESET_ALL) {
+ /*
+ * tune timing of read data/command when crc error happen
+ * no performance impact
+ */
+ if (pdata && 0 != pdata->clk_delay_cycles) {
+ u16 tmp;
+
+ tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+ tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
+ << SDCLK_DELAY_SHIFT;
+ tmp |= SDCLK_SEL;
+ writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+ }
+ }
+}
+
+#define MAX_WAIT_COUNT 5
+static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
+ u16 tmp;
+ int count;
+
+ if (pxa->power_mode == MMC_POWER_UP
+ && power_mode == MMC_POWER_ON) {
+
+ dev_dbg(mmc_dev(host->mmc),
+ "%s: slot->power_mode = %d,"
+ "ios->power_mode = %d\n",
+ __func__,
+ pxa->power_mode,
+ power_mode);
+
+ /* set we want notice of when 74 clocks are sent */
+ tmp = readw(host->ioaddr + SD_CE_ATA_2);
+ tmp |= SDCE_MISC_INT_EN;
+ writew(tmp, host->ioaddr + SD_CE_ATA_2);
+
+ /* start sending the 74 clocks */
+ tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
+ tmp |= SDCFG_GEN_PAD_CLK_ON;
+ writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
+
+ /* slowest speed is about 100KHz or 10usec per clock */
+ udelay(740);
+ count = 0;
+
+ while (count++ < MAX_WAIT_COUNT) {
+ if ((readw(host->ioaddr + SD_CE_ATA_2)
+ & SDCE_MISC_INT) == 0)
+ break;
+ udelay(10);
+ }
+
+ if (count == MAX_WAIT_COUNT)
+ dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
+
+ /* clear the interrupt bit if posted */
+ tmp = readw(host->ioaddr + SD_CE_ATA_2);
+ tmp |= SDCE_MISC_INT;
+ writew(tmp, host->ioaddr + SD_CE_ATA_2);
+ }
+ pxa->power_mode = power_mode;
+}
+
+static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
+{
+ u16 ctrl_2;
+
+ /*
+ * Set V18_EN -- UHS modes do not work without this.
+ * does not change signaling voltage
+ */
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ /* Select Bus Speed Mode for host */
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ switch (uhs) {
+ case MMC_TIMING_UHS_SDR12:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+ break;
+ case MMC_TIMING_UHS_SDR25:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+ break;
+ case MMC_TIMING_UHS_SDR50:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
+ break;
+ case MMC_TIMING_UHS_SDR104:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
+ break;
+ }
+
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+ dev_dbg(mmc_dev(host->mmc),
+ "%s uhs = %d, ctrl_2 = %04X\n",
+ __func__, uhs, ctrl_2);
+
+ return 0;
+}
+
+static struct sdhci_ops pxav3_sdhci_ops = {
+ .platform_reset_exit = pxav3_set_private_registers,
+ .set_uhs_signaling = pxav3_set_uhs_signaling,
+ .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
+};
+
+static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct sdhci_host *host = NULL;
+ struct sdhci_pxa *pxa = NULL;
+ int ret;
+ struct clk *clk;
+
+ pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
+ if (!pxa)
+ return -ENOMEM;
+
+ host = sdhci_pltfm_init(pdev, NULL);
+ if (IS_ERR(host)) {
+ kfree(pxa);
+ return PTR_ERR(host);
+ }
+ pltfm_host = sdhci_priv(host);
+ pltfm_host->priv = pxa;
+
+ clk = clk_get(dev, "PXA-SDHCLK");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get io clock\n");
+ ret = PTR_ERR(clk);
+ goto err_clk_get;
+ }
+ pltfm_host->clk = clk;
+ clk_enable(clk);
+
+ host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
+ | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
+
+ /* enable 1/8V DDR capable */
+ host->mmc->caps |= MMC_CAP_1_8V_DDR;
+
+ if (pdata) {
+ if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
+ /* on-chip device */
+ host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+ host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+ }
+
+ /* If slot design supports 8 bit data, indicate this to MMC. */
+ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
+ host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+ if (pdata->quirks)
+ host->quirks |= pdata->quirks;
+ if (pdata->host_caps)
+ host->mmc->caps |= pdata->host_caps;
+ if (pdata->pm_caps)
+ host->mmc->pm_caps |= pdata->pm_caps;
+ }
+
+ host->ops = &pxav3_sdhci_ops;
+
+ ret = sdhci_add_host(host);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add host\n");
+ goto err_add_host;
+ }
+
+ platform_set_drvdata(pdev, host);
+
+ return 0;
+
+err_add_host:
+ clk_disable(clk);
+ clk_put(clk);
+err_clk_get:
+ sdhci_pltfm_free(pdev);
+ kfree(pxa);
+ return ret;
+}
+
+static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
+
+ sdhci_remove_host(host, 1);
+
+ clk_disable(pltfm_host->clk);
+ clk_put(pltfm_host->clk);
+ sdhci_pltfm_free(pdev);
+ kfree(pxa);
+
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver sdhci_pxav3_driver = {
+ .driver = {
+ .name = "sdhci-pxav3",
+ .owner = THIS_MODULE,
+ },
+ .probe = sdhci_pxav3_probe,
+ .remove = __devexit_p(sdhci_pxav3_remove),
+#ifdef CONFIG_PM
+ .suspend = sdhci_pltfm_suspend,
+ .resume = sdhci_pltfm_resume,
+#endif
+};
+static int __init sdhci_pxav3_init(void)
+{
+ return platform_driver_register(&sdhci_pxav3_driver);
+}
+
+static void __exit sdhci_pxav3_exit(void)
+{
+ platform_driver_unregister(&sdhci_pxav3_driver);
+}
+
+module_init(sdhci_pxav3_init);
+module_exit(sdhci_pxav3_exit);
+
+MODULE_DESCRIPTION("SDHCI driver for pxav3");
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_LICENSE("GPL v2");
+
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 2/5] mmc: support sdhci-pxav2.c
2011-06-08 9:41 ` Zhangfei Gao
@ 2011-06-08 9:41 ` Zhangfei Gao
-1 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:41 UTC (permalink / raw)
To: Arnd Bergmann, Nicolas Pitre, Philip Rakity, Wolfram Sang,
Chris Ball, linux-mmc
Cc: Zhangfei Gao, Jun Nie, Qiming Wu
SDHCI driver for PXAV2 SoCs, such as pxa910, the driver based on sdhci-pltfm to handle resource etc.
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Jun Nie <njun@marvell.com>
Signed-off-by: Qiming Wu <wuqm@marvell.com>
---
drivers/mmc/host/Kconfig | 12 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-pxav2.c | 244 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 257 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-pxav2.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6525a04..97b8322 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -205,6 +205,18 @@ config MMC_SDHCI_PXAV3
If unsure, say N.
+config MMC_SDHCI_PXAV2
+ tristate "Marvell PXA9XX SD Host Controller support (PXAV2)"
+ select MMC_SDHCI
+ select MMC_SDHCI_PLTFM
+ default CPU_PXA910
+ help
+ This selects the Marvell(R) PXAV2 SD Host Controller.
+ If you have a PXA9XX platform with SD Host Controller
+ and a card slot, say Y or M here.
+
+ If unsure, say N.
+
config MMC_SDHCI_SPEAR
tristate "SDHCI support on ST SPEAr platform"
depends on MMC_SDHCI && PLAT_SPEAR
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 688cc52..99f7d79 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
obj-$(CONFIG_MMC_SDHCI_PXA) += sdhci-pxa.o
obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
+obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
new file mode 100644
index 0000000..7a6fa8c
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pxav2.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2010 Marvell International Ltd.
+ * Zhangfei Gao <zhangfei.gao@marvell.com>
+ * Kevin Wang <dwang4@marvell.com>
+ * Jun Nie <njun@marvell.com>
+ * Qiming Wu <wuqm@marvell.com>
+ * Philip Rakity <prakity@marvell.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <plat/sdhci.h>
+#include <linux/slab.h>
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+
+#define SD_FIFO_PARAM 0xe0
+#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
+#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
+#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
+#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
+ CLK_GATE_ON | CLK_GATE_CTL)
+
+#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
+#define SDCLK_SEL_SHIFT 8
+#define SDCLK_SEL_MASK 0x3
+#define SDCLK_DELAY_SHIFT 10
+#define SDCLK_DELAY_MASK 0x3c
+
+#define SD_CE_ATA_2 0xea
+#define MMC_CARD 0x1000
+#define MMC_WIDTH 0x0100
+
+static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
+{
+ struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
+ if (mask == SDHCI_RESET_ALL) {
+ u16 tmp = 0;
+
+ /*
+ * tune timing of read data/command when crc error happen
+ * no performance impact
+ */
+ if (pdata->clk_delay_sel == 1) {
+ tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+
+ tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
+ tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
+ << SDCLK_DELAY_SHIFT;
+ tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
+ tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
+
+ writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+ }
+
+ if (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING) {
+ tmp = readw(host->ioaddr + SD_FIFO_PARAM);
+ tmp &= ~CLK_GATE_SETTING_BITS;
+ writew(tmp, host->ioaddr + SD_FIFO_PARAM);
+ } else {
+ tmp = readw(host->ioaddr + SD_FIFO_PARAM);
+ tmp &= ~CLK_GATE_SETTING_BITS;
+ tmp |= CLK_GATE_SETTING_BITS;
+ writew(tmp, host->ioaddr + SD_FIFO_PARAM);
+ }
+ }
+}
+
+static int pxav2_mmc_set_width(struct sdhci_host *host, int width)
+{
+ u8 ctrl;
+ u16 tmp;
+
+ ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
+ tmp = readw(host->ioaddr + SD_CE_ATA_2);
+ if (width == MMC_BUS_WIDTH_8) {
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ tmp |= MMC_CARD | MMC_WIDTH;
+ } else {
+ tmp &= ~(MMC_CARD | MMC_WIDTH);
+ if (width == MMC_BUS_WIDTH_4)
+ ctrl |= SDHCI_CTRL_4BITBUS;
+ else
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ }
+ writew(tmp, host->ioaddr + SD_CE_ATA_2);
+ writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
+
+ return 0;
+}
+
+static u32 pxav2_get_max_clock(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+ return clk_get_rate(pltfm_host->clk);
+}
+
+static struct sdhci_ops pxav2_sdhci_ops = {
+ .get_max_clock = pxav2_get_max_clock,
+ .platform_reset_exit = pxav2_set_private_registers,
+ .platform_8bit_width = pxav2_mmc_set_width,
+};
+
+static int __devinit sdhci_pxav2_probe(struct platform_device *pdev)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct sdhci_host *host = NULL;
+ struct sdhci_pxa *pxa = NULL;
+ int ret;
+ struct clk *clk;
+
+ pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
+ if (!pxa)
+ return -ENOMEM;
+
+ host = sdhci_pltfm_init(pdev, NULL);
+ if (IS_ERR(host)) {
+ kfree(pxa);
+ return PTR_ERR(host);
+ }
+ pltfm_host = sdhci_priv(host);
+ pltfm_host->priv = pxa;
+
+ clk = clk_get(dev, "PXA-SDHCLK");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get io clock\n");
+ ret = PTR_ERR(clk);
+ goto err_clk_get;
+ }
+ pltfm_host->clk = clk;
+ clk_enable(clk);
+
+ host->quirks = SDHCI_QUIRK_BROKEN_ADMA
+ | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
+ | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
+
+ if (pdata) {
+ if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
+ /* on-chip device */
+ host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+ host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+ }
+
+ /* If slot design supports 8 bit data, indicate this to MMC. */
+ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
+ host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+ if (pdata->quirks)
+ host->quirks |= pdata->quirks;
+ if (pdata->host_caps)
+ host->mmc->caps |= pdata->host_caps;
+ if (pdata->pm_caps)
+ host->mmc->pm_caps |= pdata->pm_caps;
+ }
+
+ host->ops = &pxav2_sdhci_ops;
+
+ ret = sdhci_add_host(host);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add host\n");
+ goto err_add_host;
+ }
+
+ platform_set_drvdata(pdev, host);
+
+ return 0;
+
+err_add_host:
+ clk_disable(clk);
+ clk_put(clk);
+err_clk_get:
+ sdhci_pltfm_free(pdev);
+ kfree(pxa);
+ return ret;
+}
+
+static int __devexit sdhci_pxav2_remove(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
+
+ sdhci_remove_host(host, 1);
+
+ clk_disable(pltfm_host->clk);
+ clk_put(pltfm_host->clk);
+ sdhci_pltfm_free(pdev);
+ kfree(pxa);
+
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver sdhci_pxav2_driver = {
+ .driver = {
+ .name = "sdhci-pxav2",
+ .owner = THIS_MODULE,
+ },
+ .probe = sdhci_pxav2_probe,
+ .remove = __devexit_p(sdhci_pxav2_remove),
+#ifdef CONFIG_PM
+ .suspend = sdhci_pltfm_suspend,
+ .resume = sdhci_pltfm_resume,
+#endif
+};
+static int __init sdhci_pxav2_init(void)
+{
+ return platform_driver_register(&sdhci_pxav2_driver);
+}
+
+static void __exit sdhci_pxav2_exit(void)
+{
+ platform_driver_unregister(&sdhci_pxav2_driver);
+}
+
+module_init(sdhci_pxav2_init);
+module_exit(sdhci_pxav2_exit);
+
+MODULE_DESCRIPTION("SDHCI driver for pxav2");
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_LICENSE("GPL v2");
+
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 2/5] mmc: support sdhci-pxav2.c
@ 2011-06-08 9:41 ` Zhangfei Gao
0 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:41 UTC (permalink / raw)
To: linux-arm-kernel
SDHCI driver for PXAV2 SoCs, such as pxa910, the driver based on sdhci-pltfm to handle resource etc.
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Jun Nie <njun@marvell.com>
Signed-off-by: Qiming Wu <wuqm@marvell.com>
---
drivers/mmc/host/Kconfig | 12 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-pxav2.c | 244 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 257 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-pxav2.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6525a04..97b8322 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -205,6 +205,18 @@ config MMC_SDHCI_PXAV3
If unsure, say N.
+config MMC_SDHCI_PXAV2
+ tristate "Marvell PXA9XX SD Host Controller support (PXAV2)"
+ select MMC_SDHCI
+ select MMC_SDHCI_PLTFM
+ default CPU_PXA910
+ help
+ This selects the Marvell(R) PXAV2 SD Host Controller.
+ If you have a PXA9XX platform with SD Host Controller
+ and a card slot, say Y or M here.
+
+ If unsure, say N.
+
config MMC_SDHCI_SPEAR
tristate "SDHCI support on ST SPEAr platform"
depends on MMC_SDHCI && PLAT_SPEAR
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 688cc52..99f7d79 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
obj-$(CONFIG_MMC_SDHCI_PXA) += sdhci-pxa.o
obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
+obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
new file mode 100644
index 0000000..7a6fa8c
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pxav2.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2010 Marvell International Ltd.
+ * Zhangfei Gao <zhangfei.gao@marvell.com>
+ * Kevin Wang <dwang4@marvell.com>
+ * Jun Nie <njun@marvell.com>
+ * Qiming Wu <wuqm@marvell.com>
+ * Philip Rakity <prakity@marvell.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <plat/sdhci.h>
+#include <linux/slab.h>
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+
+#define SD_FIFO_PARAM 0xe0
+#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
+#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
+#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
+#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
+ CLK_GATE_ON | CLK_GATE_CTL)
+
+#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
+#define SDCLK_SEL_SHIFT 8
+#define SDCLK_SEL_MASK 0x3
+#define SDCLK_DELAY_SHIFT 10
+#define SDCLK_DELAY_MASK 0x3c
+
+#define SD_CE_ATA_2 0xea
+#define MMC_CARD 0x1000
+#define MMC_WIDTH 0x0100
+
+static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
+{
+ struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
+ if (mask == SDHCI_RESET_ALL) {
+ u16 tmp = 0;
+
+ /*
+ * tune timing of read data/command when crc error happen
+ * no performance impact
+ */
+ if (pdata->clk_delay_sel == 1) {
+ tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+
+ tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
+ tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
+ << SDCLK_DELAY_SHIFT;
+ tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
+ tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
+
+ writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+ }
+
+ if (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING) {
+ tmp = readw(host->ioaddr + SD_FIFO_PARAM);
+ tmp &= ~CLK_GATE_SETTING_BITS;
+ writew(tmp, host->ioaddr + SD_FIFO_PARAM);
+ } else {
+ tmp = readw(host->ioaddr + SD_FIFO_PARAM);
+ tmp &= ~CLK_GATE_SETTING_BITS;
+ tmp |= CLK_GATE_SETTING_BITS;
+ writew(tmp, host->ioaddr + SD_FIFO_PARAM);
+ }
+ }
+}
+
+static int pxav2_mmc_set_width(struct sdhci_host *host, int width)
+{
+ u8 ctrl;
+ u16 tmp;
+
+ ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
+ tmp = readw(host->ioaddr + SD_CE_ATA_2);
+ if (width == MMC_BUS_WIDTH_8) {
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ tmp |= MMC_CARD | MMC_WIDTH;
+ } else {
+ tmp &= ~(MMC_CARD | MMC_WIDTH);
+ if (width == MMC_BUS_WIDTH_4)
+ ctrl |= SDHCI_CTRL_4BITBUS;
+ else
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ }
+ writew(tmp, host->ioaddr + SD_CE_ATA_2);
+ writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
+
+ return 0;
+}
+
+static u32 pxav2_get_max_clock(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+
+ return clk_get_rate(pltfm_host->clk);
+}
+
+static struct sdhci_ops pxav2_sdhci_ops = {
+ .get_max_clock = pxav2_get_max_clock,
+ .platform_reset_exit = pxav2_set_private_registers,
+ .platform_8bit_width = pxav2_mmc_set_width,
+};
+
+static int __devinit sdhci_pxav2_probe(struct platform_device *pdev)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct sdhci_host *host = NULL;
+ struct sdhci_pxa *pxa = NULL;
+ int ret;
+ struct clk *clk;
+
+ pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
+ if (!pxa)
+ return -ENOMEM;
+
+ host = sdhci_pltfm_init(pdev, NULL);
+ if (IS_ERR(host)) {
+ kfree(pxa);
+ return PTR_ERR(host);
+ }
+ pltfm_host = sdhci_priv(host);
+ pltfm_host->priv = pxa;
+
+ clk = clk_get(dev, "PXA-SDHCLK");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get io clock\n");
+ ret = PTR_ERR(clk);
+ goto err_clk_get;
+ }
+ pltfm_host->clk = clk;
+ clk_enable(clk);
+
+ host->quirks = SDHCI_QUIRK_BROKEN_ADMA
+ | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
+ | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
+
+ if (pdata) {
+ if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
+ /* on-chip device */
+ host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+ host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+ }
+
+ /* If slot design supports 8 bit data, indicate this to MMC. */
+ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
+ host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+ if (pdata->quirks)
+ host->quirks |= pdata->quirks;
+ if (pdata->host_caps)
+ host->mmc->caps |= pdata->host_caps;
+ if (pdata->pm_caps)
+ host->mmc->pm_caps |= pdata->pm_caps;
+ }
+
+ host->ops = &pxav2_sdhci_ops;
+
+ ret = sdhci_add_host(host);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add host\n");
+ goto err_add_host;
+ }
+
+ platform_set_drvdata(pdev, host);
+
+ return 0;
+
+err_add_host:
+ clk_disable(clk);
+ clk_put(clk);
+err_clk_get:
+ sdhci_pltfm_free(pdev);
+ kfree(pxa);
+ return ret;
+}
+
+static int __devexit sdhci_pxav2_remove(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
+
+ sdhci_remove_host(host, 1);
+
+ clk_disable(pltfm_host->clk);
+ clk_put(pltfm_host->clk);
+ sdhci_pltfm_free(pdev);
+ kfree(pxa);
+
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver sdhci_pxav2_driver = {
+ .driver = {
+ .name = "sdhci-pxav2",
+ .owner = THIS_MODULE,
+ },
+ .probe = sdhci_pxav2_probe,
+ .remove = __devexit_p(sdhci_pxav2_remove),
+#ifdef CONFIG_PM
+ .suspend = sdhci_pltfm_suspend,
+ .resume = sdhci_pltfm_resume,
+#endif
+};
+static int __init sdhci_pxav2_init(void)
+{
+ return platform_driver_register(&sdhci_pxav2_driver);
+}
+
+static void __exit sdhci_pxav2_exit(void)
+{
+ platform_driver_unregister(&sdhci_pxav2_driver);
+}
+
+module_init(sdhci_pxav2_init);
+module_exit(sdhci_pxav2_exit);
+
+MODULE_DESCRIPTION("SDHCI driver for pxav2");
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_LICENSE("GPL v2");
+
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 3/5] ARM: mmp2: update mmp2 mmc resource
2011-06-08 9:41 ` Zhangfei Gao
@ 2011-06-08 9:41 ` Zhangfei Gao
-1 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:41 UTC (permalink / raw)
To: Arnd Bergmann, Nicolas Pitre, Philip Rakity, Wolfram Sang,
Chris Ball, linux-mmc
Cc: Zhangfei Gao
mmp2 mmc driver name update to sdhci-pxav3 according to sdhci-pxav3.c
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
---
arch/arm/mach-mmp/brownstone.c | 10 +++++++++-
arch/arm/mach-mmp/jasper.c | 2 +-
arch/arm/mach-mmp/mmp2.c | 16 ++++++++--------
3 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index 7bb78fd..c79162a 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -177,9 +177,16 @@ static struct i2c_board_info brownstone_twsi1_info[] = {
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
- .max_speed = 25000000,
+ .clk_delay_cycles = 0x1f,
};
+static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
+ .clk_delay_cycles = 0x1f,
+ .flags = PXA_FLAG_CARD_PERMANENT
+ | PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
+};
+
+
static void __init brownstone_init(void)
{
mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
@@ -189,6 +196,7 @@ static void __init brownstone_init(void)
mmp2_add_uart(3);
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
+ mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
/* enable 5v regulator */
platform_device_register(&brownstone_v_5vp_device);
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 24172a0..5d6421d 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -154,7 +154,7 @@ static struct i2c_board_info jasper_twsi1_info[] = {
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
- .max_speed = 25000000,
+ .clk_delay_cycles = 0x1f,
};
static void __init jasper_init(void)
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 8e6c3ac..079c188 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -168,10 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = {
INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
- INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
};
static int __init mmp2_init(void)
@@ -222,8 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
-MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120);
-MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120);
-MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120);
-MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120);
+MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
+MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
+MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
+MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 3/5] ARM: mmp2: update mmp2 mmc resource
@ 2011-06-08 9:41 ` Zhangfei Gao
0 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:41 UTC (permalink / raw)
To: linux-arm-kernel
mmp2 mmc driver name update to sdhci-pxav3 according to sdhci-pxav3.c
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
---
arch/arm/mach-mmp/brownstone.c | 10 +++++++++-
arch/arm/mach-mmp/jasper.c | 2 +-
arch/arm/mach-mmp/mmp2.c | 16 ++++++++--------
3 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index 7bb78fd..c79162a 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -177,9 +177,16 @@ static struct i2c_board_info brownstone_twsi1_info[] = {
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
- .max_speed = 25000000,
+ .clk_delay_cycles = 0x1f,
};
+static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
+ .clk_delay_cycles = 0x1f,
+ .flags = PXA_FLAG_CARD_PERMANENT
+ | PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
+};
+
+
static void __init brownstone_init(void)
{
mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
@@ -189,6 +196,7 @@ static void __init brownstone_init(void)
mmp2_add_uart(3);
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
+ mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
/* enable 5v regulator */
platform_device_register(&brownstone_v_5vp_device);
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 24172a0..5d6421d 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -154,7 +154,7 @@ static struct i2c_board_info jasper_twsi1_info[] = {
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
- .max_speed = 25000000,
+ .clk_delay_cycles = 0x1f,
};
static void __init jasper_init(void)
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 8e6c3ac..079c188 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -168,10 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = {
INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
- INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
};
static int __init mmp2_init(void)
@@ -222,8 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
-MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120);
-MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120);
-MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120);
-MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120);
+MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
+MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
+MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
+MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 4/5] mmc: delete obsolete sdhci-pxa.c
2011-06-08 9:41 ` Zhangfei Gao
@ 2011-06-08 9:42 ` Zhangfei Gao
-1 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:42 UTC (permalink / raw)
To: Arnd Bergmann, Nicolas Pitre, Philip Rakity, Wolfram Sang,
Chris Ball, linux-mmc
Cc: Zhangfei Gao
Delete obsolete sdhci-pxa.c, which is used to be shared among pxa serious.
The method may not eady to track, since platfrom difference are put under arch/arm.
Instead, use sdhci-pxav3.c for mmp2, and sdhci-pxav2.c for pxa9xx.
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
---
drivers/mmc/host/Kconfig | 12 --
drivers/mmc/host/Makefile | 1 -
drivers/mmc/host/sdhci-pxa.c | 303 ------------------------------------------
3 files changed, 0 insertions(+), 316 deletions(-)
delete mode 100644 drivers/mmc/host/sdhci-pxa.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 97b8322..198ddda 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -181,18 +181,6 @@ config MMC_SDHCI_S3C
If unsure, say N.
-config MMC_SDHCI_PXA
- tristate "Marvell PXA168/PXA910/MMP2 SD Host Controller support"
- depends on ARCH_PXA || ARCH_MMP
- select MMC_SDHCI
- select MMC_SDHCI_IO_ACCESSORS
- help
- This selects the Marvell(R) PXA168/PXA910/MMP2 SD Host Controller.
- If you have a PXA168/PXA910/MMP2 platform with SD Host Controller
- and a card slot, say Y or M here.
-
- If unsure, say N.
-
config MMC_SDHCI_PXAV3
tristate "Marvell MMP2 SD Host Controller support (PXAV3)"
select MMC_SDHCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 99f7d79..cf95330 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_MMC_MXC) += mxcmmc.o
obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
-obj-$(CONFIG_MMC_SDHCI_PXA) += sdhci-pxa.o
obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c
deleted file mode 100644
index 089c9a6..0000000
--- a/drivers/mmc/host/sdhci-pxa.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/* linux/drivers/mmc/host/sdhci-pxa.c
- *
- * Copyright (C) 2010 Marvell International Ltd.
- * Zhangfei Gao <zhangfei.gao@marvell.com>
- * Kevin Wang <dwang4@marvell.com>
- * Mingwei Wang <mwwang@marvell.com>
- * Philip Rakity <prakity@marvell.com>
- * Mark Brown <markb@marvell.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/* Supports:
- * SDHCI support for MMP2/PXA910/PXA168
- *
- * Refer to sdhci-s3c.c.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/mmc/host.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <plat/sdhci.h>
-#include "sdhci.h"
-
-#define DRIVER_NAME "sdhci-pxa"
-
-#define SD_FIFO_PARAM 0x104
-#define DIS_PAD_SD_CLK_GATE 0x400
-
-struct sdhci_pxa {
- struct sdhci_host *host;
- struct sdhci_pxa_platdata *pdata;
- struct clk *clk;
- struct resource *res;
-
- u8 clk_enable;
-};
-
-/*****************************************************************************\
- * *
- * SDHCI core callbacks *
- * *
-\*****************************************************************************/
-static void set_clock(struct sdhci_host *host, unsigned int clock)
-{
- struct sdhci_pxa *pxa = sdhci_priv(host);
- u32 tmp = 0;
-
- if (clock == 0) {
- if (pxa->clk_enable) {
- clk_disable(pxa->clk);
- pxa->clk_enable = 0;
- }
- } else {
- if (0 == pxa->clk_enable) {
- if (pxa->pdata->flags & PXA_FLAG_DISABLE_CLOCK_GATING) {
- tmp = readl(host->ioaddr + SD_FIFO_PARAM);
- tmp |= DIS_PAD_SD_CLK_GATE;
- writel(tmp, host->ioaddr + SD_FIFO_PARAM);
- }
- clk_enable(pxa->clk);
- pxa->clk_enable = 1;
- }
- }
-}
-
-static int set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
-{
- u16 ctrl_2;
-
- /*
- * Set V18_EN -- UHS modes do not work without this.
- * does not change signaling voltage
- */
- ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
-
- /* Select Bus Speed Mode for host */
- ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
- switch (uhs) {
- case MMC_TIMING_UHS_SDR12:
- ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
- break;
- case MMC_TIMING_UHS_SDR25:
- ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
- break;
- case MMC_TIMING_UHS_SDR50:
- ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
- break;
- case MMC_TIMING_UHS_SDR104:
- ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
- break;
- case MMC_TIMING_UHS_DDR50:
- ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
- break;
- }
-
- sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
- pr_debug("%s:%s uhs = %d, ctrl_2 = %04X\n",
- __func__, mmc_hostname(host->mmc), uhs, ctrl_2);
-
- return 0;
-}
-
-static struct sdhci_ops sdhci_pxa_ops = {
- .set_uhs_signaling = set_uhs_signaling,
- .set_clock = set_clock,
-};
-
-/*****************************************************************************\
- * *
- * Device probing/removal *
- * *
-\*****************************************************************************/
-
-static int __devinit sdhci_pxa_probe(struct platform_device *pdev)
-{
- struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
- struct device *dev = &pdev->dev;
- struct sdhci_host *host = NULL;
- struct resource *iomem = NULL;
- struct sdhci_pxa *pxa = NULL;
- int ret, irq;
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- dev_err(dev, "no irq specified\n");
- return irq;
- }
-
- iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!iomem) {
- dev_err(dev, "no memory specified\n");
- return -ENOENT;
- }
-
- host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pxa));
- if (IS_ERR(host)) {
- dev_err(dev, "failed to alloc host\n");
- return PTR_ERR(host);
- }
-
- pxa = sdhci_priv(host);
- pxa->host = host;
- pxa->pdata = pdata;
- pxa->clk_enable = 0;
-
- pxa->clk = clk_get(dev, "PXA-SDHCLK");
- if (IS_ERR(pxa->clk)) {
- dev_err(dev, "failed to get io clock\n");
- ret = PTR_ERR(pxa->clk);
- goto out;
- }
-
- pxa->res = request_mem_region(iomem->start, resource_size(iomem),
- mmc_hostname(host->mmc));
- if (!pxa->res) {
- dev_err(&pdev->dev, "cannot request region\n");
- ret = -EBUSY;
- goto out;
- }
-
- host->ioaddr = ioremap(iomem->start, resource_size(iomem));
- if (!host->ioaddr) {
- dev_err(&pdev->dev, "failed to remap registers\n");
- ret = -ENOMEM;
- goto out;
- }
-
- host->hw_name = "MMC";
- host->ops = &sdhci_pxa_ops;
- host->irq = irq;
- host->quirks = SDHCI_QUIRK_BROKEN_ADMA
- | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
- | SDHCI_QUIRK_32BIT_DMA_ADDR
- | SDHCI_QUIRK_32BIT_DMA_SIZE
- | SDHCI_QUIRK_32BIT_ADMA_SIZE
- | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
-
- if (pdata->quirks)
- host->quirks |= pdata->quirks;
-
- /* enable 1/8V DDR capable */
- host->mmc->caps |= MMC_CAP_1_8V_DDR;
-
- /* If slot design supports 8 bit data, indicate this to MMC. */
- if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
- host->mmc->caps |= MMC_CAP_8_BIT_DATA;
-
- ret = sdhci_add_host(host);
- if (ret) {
- dev_err(&pdev->dev, "failed to add host\n");
- goto out;
- }
-
- if (pxa->pdata->max_speed)
- host->mmc->f_max = pxa->pdata->max_speed;
-
- platform_set_drvdata(pdev, host);
-
- return 0;
-out:
- if (host) {
- clk_put(pxa->clk);
- if (host->ioaddr)
- iounmap(host->ioaddr);
- if (pxa->res)
- release_mem_region(pxa->res->start,
- resource_size(pxa->res));
- sdhci_free_host(host);
- }
-
- return ret;
-}
-
-static int __devexit sdhci_pxa_remove(struct platform_device *pdev)
-{
- struct sdhci_host *host = platform_get_drvdata(pdev);
- struct sdhci_pxa *pxa = sdhci_priv(host);
- int dead = 0;
- u32 scratch;
-
- if (host) {
- scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
- if (scratch == (u32)-1)
- dead = 1;
-
- sdhci_remove_host(host, dead);
-
- if (host->ioaddr)
- iounmap(host->ioaddr);
- if (pxa->res)
- release_mem_region(pxa->res->start,
- resource_size(pxa->res));
- if (pxa->clk_enable) {
- clk_disable(pxa->clk);
- pxa->clk_enable = 0;
- }
- clk_put(pxa->clk);
-
- sdhci_free_host(host);
- platform_set_drvdata(pdev, NULL);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int sdhci_pxa_suspend(struct platform_device *dev, pm_message_t state)
-{
- struct sdhci_host *host = platform_get_drvdata(dev);
-
- return sdhci_suspend_host(host, state);
-}
-
-static int sdhci_pxa_resume(struct platform_device *dev)
-{
- struct sdhci_host *host = platform_get_drvdata(dev);
-
- return sdhci_resume_host(host);
-}
-#else
-#define sdhci_pxa_suspend NULL
-#define sdhci_pxa_resume NULL
-#endif
-
-static struct platform_driver sdhci_pxa_driver = {
- .probe = sdhci_pxa_probe,
- .remove = __devexit_p(sdhci_pxa_remove),
- .suspend = sdhci_pxa_suspend,
- .resume = sdhci_pxa_resume,
- .driver = {
- .name = DRIVER_NAME,
- .owner = THIS_MODULE,
- },
-};
-
-/*****************************************************************************\
- * *
- * Driver init/exit *
- * *
-\*****************************************************************************/
-
-static int __init sdhci_pxa_init(void)
-{
- return platform_driver_register(&sdhci_pxa_driver);
-}
-
-static void __exit sdhci_pxa_exit(void)
-{
- platform_driver_unregister(&sdhci_pxa_driver);
-}
-
-module_init(sdhci_pxa_init);
-module_exit(sdhci_pxa_exit);
-
-MODULE_DESCRIPTION("SDH controller driver for PXA168/PXA910/MMP2");
-MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
-MODULE_LICENSE("GPL v2");
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 4/5] mmc: delete obsolete sdhci-pxa.c
@ 2011-06-08 9:42 ` Zhangfei Gao
0 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:42 UTC (permalink / raw)
To: linux-arm-kernel
Delete obsolete sdhci-pxa.c, which is used to be shared among pxa serious.
The method may not eady to track, since platfrom difference are put under arch/arm.
Instead, use sdhci-pxav3.c for mmp2, and sdhci-pxav2.c for pxa9xx.
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
---
drivers/mmc/host/Kconfig | 12 --
drivers/mmc/host/Makefile | 1 -
drivers/mmc/host/sdhci-pxa.c | 303 ------------------------------------------
3 files changed, 0 insertions(+), 316 deletions(-)
delete mode 100644 drivers/mmc/host/sdhci-pxa.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 97b8322..198ddda 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -181,18 +181,6 @@ config MMC_SDHCI_S3C
If unsure, say N.
-config MMC_SDHCI_PXA
- tristate "Marvell PXA168/PXA910/MMP2 SD Host Controller support"
- depends on ARCH_PXA || ARCH_MMP
- select MMC_SDHCI
- select MMC_SDHCI_IO_ACCESSORS
- help
- This selects the Marvell(R) PXA168/PXA910/MMP2 SD Host Controller.
- If you have a PXA168/PXA910/MMP2 platform with SD Host Controller
- and a card slot, say Y or M here.
-
- If unsure, say N.
-
config MMC_SDHCI_PXAV3
tristate "Marvell MMP2 SD Host Controller support (PXAV3)"
select MMC_SDHCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 99f7d79..cf95330 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_MMC_MXC) += mxcmmc.o
obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
-obj-$(CONFIG_MMC_SDHCI_PXA) += sdhci-pxa.o
obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c
deleted file mode 100644
index 089c9a6..0000000
--- a/drivers/mmc/host/sdhci-pxa.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/* linux/drivers/mmc/host/sdhci-pxa.c
- *
- * Copyright (C) 2010 Marvell International Ltd.
- * Zhangfei Gao <zhangfei.gao@marvell.com>
- * Kevin Wang <dwang4@marvell.com>
- * Mingwei Wang <mwwang@marvell.com>
- * Philip Rakity <prakity@marvell.com>
- * Mark Brown <markb@marvell.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/* Supports:
- * SDHCI support for MMP2/PXA910/PXA168
- *
- * Refer to sdhci-s3c.c.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/mmc/host.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <plat/sdhci.h>
-#include "sdhci.h"
-
-#define DRIVER_NAME "sdhci-pxa"
-
-#define SD_FIFO_PARAM 0x104
-#define DIS_PAD_SD_CLK_GATE 0x400
-
-struct sdhci_pxa {
- struct sdhci_host *host;
- struct sdhci_pxa_platdata *pdata;
- struct clk *clk;
- struct resource *res;
-
- u8 clk_enable;
-};
-
-/*****************************************************************************\
- * *
- * SDHCI core callbacks *
- * *
-\*****************************************************************************/
-static void set_clock(struct sdhci_host *host, unsigned int clock)
-{
- struct sdhci_pxa *pxa = sdhci_priv(host);
- u32 tmp = 0;
-
- if (clock == 0) {
- if (pxa->clk_enable) {
- clk_disable(pxa->clk);
- pxa->clk_enable = 0;
- }
- } else {
- if (0 == pxa->clk_enable) {
- if (pxa->pdata->flags & PXA_FLAG_DISABLE_CLOCK_GATING) {
- tmp = readl(host->ioaddr + SD_FIFO_PARAM);
- tmp |= DIS_PAD_SD_CLK_GATE;
- writel(tmp, host->ioaddr + SD_FIFO_PARAM);
- }
- clk_enable(pxa->clk);
- pxa->clk_enable = 1;
- }
- }
-}
-
-static int set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
-{
- u16 ctrl_2;
-
- /*
- * Set V18_EN -- UHS modes do not work without this.
- * does not change signaling voltage
- */
- ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
-
- /* Select Bus Speed Mode for host */
- ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
- switch (uhs) {
- case MMC_TIMING_UHS_SDR12:
- ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
- break;
- case MMC_TIMING_UHS_SDR25:
- ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
- break;
- case MMC_TIMING_UHS_SDR50:
- ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
- break;
- case MMC_TIMING_UHS_SDR104:
- ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
- break;
- case MMC_TIMING_UHS_DDR50:
- ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
- break;
- }
-
- sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
- pr_debug("%s:%s uhs = %d, ctrl_2 = %04X\n",
- __func__, mmc_hostname(host->mmc), uhs, ctrl_2);
-
- return 0;
-}
-
-static struct sdhci_ops sdhci_pxa_ops = {
- .set_uhs_signaling = set_uhs_signaling,
- .set_clock = set_clock,
-};
-
-/*****************************************************************************\
- * *
- * Device probing/removal *
- * *
-\*****************************************************************************/
-
-static int __devinit sdhci_pxa_probe(struct platform_device *pdev)
-{
- struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
- struct device *dev = &pdev->dev;
- struct sdhci_host *host = NULL;
- struct resource *iomem = NULL;
- struct sdhci_pxa *pxa = NULL;
- int ret, irq;
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- dev_err(dev, "no irq specified\n");
- return irq;
- }
-
- iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!iomem) {
- dev_err(dev, "no memory specified\n");
- return -ENOENT;
- }
-
- host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pxa));
- if (IS_ERR(host)) {
- dev_err(dev, "failed to alloc host\n");
- return PTR_ERR(host);
- }
-
- pxa = sdhci_priv(host);
- pxa->host = host;
- pxa->pdata = pdata;
- pxa->clk_enable = 0;
-
- pxa->clk = clk_get(dev, "PXA-SDHCLK");
- if (IS_ERR(pxa->clk)) {
- dev_err(dev, "failed to get io clock\n");
- ret = PTR_ERR(pxa->clk);
- goto out;
- }
-
- pxa->res = request_mem_region(iomem->start, resource_size(iomem),
- mmc_hostname(host->mmc));
- if (!pxa->res) {
- dev_err(&pdev->dev, "cannot request region\n");
- ret = -EBUSY;
- goto out;
- }
-
- host->ioaddr = ioremap(iomem->start, resource_size(iomem));
- if (!host->ioaddr) {
- dev_err(&pdev->dev, "failed to remap registers\n");
- ret = -ENOMEM;
- goto out;
- }
-
- host->hw_name = "MMC";
- host->ops = &sdhci_pxa_ops;
- host->irq = irq;
- host->quirks = SDHCI_QUIRK_BROKEN_ADMA
- | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
- | SDHCI_QUIRK_32BIT_DMA_ADDR
- | SDHCI_QUIRK_32BIT_DMA_SIZE
- | SDHCI_QUIRK_32BIT_ADMA_SIZE
- | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
-
- if (pdata->quirks)
- host->quirks |= pdata->quirks;
-
- /* enable 1/8V DDR capable */
- host->mmc->caps |= MMC_CAP_1_8V_DDR;
-
- /* If slot design supports 8 bit data, indicate this to MMC. */
- if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
- host->mmc->caps |= MMC_CAP_8_BIT_DATA;
-
- ret = sdhci_add_host(host);
- if (ret) {
- dev_err(&pdev->dev, "failed to add host\n");
- goto out;
- }
-
- if (pxa->pdata->max_speed)
- host->mmc->f_max = pxa->pdata->max_speed;
-
- platform_set_drvdata(pdev, host);
-
- return 0;
-out:
- if (host) {
- clk_put(pxa->clk);
- if (host->ioaddr)
- iounmap(host->ioaddr);
- if (pxa->res)
- release_mem_region(pxa->res->start,
- resource_size(pxa->res));
- sdhci_free_host(host);
- }
-
- return ret;
-}
-
-static int __devexit sdhci_pxa_remove(struct platform_device *pdev)
-{
- struct sdhci_host *host = platform_get_drvdata(pdev);
- struct sdhci_pxa *pxa = sdhci_priv(host);
- int dead = 0;
- u32 scratch;
-
- if (host) {
- scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
- if (scratch == (u32)-1)
- dead = 1;
-
- sdhci_remove_host(host, dead);
-
- if (host->ioaddr)
- iounmap(host->ioaddr);
- if (pxa->res)
- release_mem_region(pxa->res->start,
- resource_size(pxa->res));
- if (pxa->clk_enable) {
- clk_disable(pxa->clk);
- pxa->clk_enable = 0;
- }
- clk_put(pxa->clk);
-
- sdhci_free_host(host);
- platform_set_drvdata(pdev, NULL);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int sdhci_pxa_suspend(struct platform_device *dev, pm_message_t state)
-{
- struct sdhci_host *host = platform_get_drvdata(dev);
-
- return sdhci_suspend_host(host, state);
-}
-
-static int sdhci_pxa_resume(struct platform_device *dev)
-{
- struct sdhci_host *host = platform_get_drvdata(dev);
-
- return sdhci_resume_host(host);
-}
-#else
-#define sdhci_pxa_suspend NULL
-#define sdhci_pxa_resume NULL
-#endif
-
-static struct platform_driver sdhci_pxa_driver = {
- .probe = sdhci_pxa_probe,
- .remove = __devexit_p(sdhci_pxa_remove),
- .suspend = sdhci_pxa_suspend,
- .resume = sdhci_pxa_resume,
- .driver = {
- .name = DRIVER_NAME,
- .owner = THIS_MODULE,
- },
-};
-
-/*****************************************************************************\
- * *
- * Driver init/exit *
- * *
-\*****************************************************************************/
-
-static int __init sdhci_pxa_init(void)
-{
- return platform_driver_register(&sdhci_pxa_driver);
-}
-
-static void __exit sdhci_pxa_exit(void)
-{
- platform_driver_unregister(&sdhci_pxa_driver);
-}
-
-module_init(sdhci_pxa_init);
-module_exit(sdhci_pxa_exit);
-
-MODULE_DESCRIPTION("SDH controller driver for PXA168/PXA910/MMP2");
-MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
-MODULE_LICENSE("GPL v2");
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
2011-06-08 9:41 ` Zhangfei Gao
@ 2011-06-08 9:42 ` Zhangfei Gao
-1 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:42 UTC (permalink / raw)
To: Arnd Bergmann, Nicolas Pitre, Philip Rakity, Wolfram Sang,
Chris Ball, linux-mmc
Cc: Zhangfei Gao
1. support brownstone
2. support mmc
3. support basic filesystem and language
4. remove dynamic_debug, since too many log during access sd
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
---
arch/arm/configs/mmp2_defconfig | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 47ad3b1..5a58452 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MMP=y
+CONFIG_MACH_BROWNSTONE=y
CONFIG_MACH_FLINT=y
CONFIG_MACH_MARVELL_JASPER=y
CONFIG_HIGH_RES_TIMERS=y
@@ -63,10 +64,16 @@ CONFIG_BACKLIGHT_MAX8925=y
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MAX8925=y
+CONFIG_MMC=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
@@ -81,7 +88,7 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_DYNAMIC_DEBUG is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
@ 2011-06-08 9:42 ` Zhangfei Gao
0 siblings, 0 replies; 25+ messages in thread
From: Zhangfei Gao @ 2011-06-08 9:42 UTC (permalink / raw)
To: linux-arm-kernel
1. support brownstone
2. support mmc
3. support basic filesystem and language
4. remove dynamic_debug, since too many log during access sd
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
---
arch/arm/configs/mmp2_defconfig | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 47ad3b1..5a58452 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MMP=y
+CONFIG_MACH_BROWNSTONE=y
CONFIG_MACH_FLINT=y
CONFIG_MACH_MARVELL_JASPER=y
CONFIG_HIGH_RES_TIMERS=y
@@ -63,10 +64,16 @@ CONFIG_BACKLIGHT_MAX8925=y
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MAX8925=y
+CONFIG_MMC=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
@@ -81,7 +88,7 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_DYNAMIC_DEBUG is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
--
1.7.0.4
^ permalink raw reply related [flat|nested] 25+ messages in thread
* RE: [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
2011-06-08 9:42 ` Zhangfei Gao
@ 2011-06-08 12:53 ` Sachin Nikam
-1 siblings, 0 replies; 25+ messages in thread
From: Sachin Nikam @ 2011-06-08 12:53 UTC (permalink / raw)
To: 'Zhangfei Gao',
Arnd Bergmann, Nicolas Pitre, Philip Rakity, Wolfram Sang
Hello Folks,
Does anybody knows which kernel version will have the SD 4.0 (UHS-II) support?
Thanks,
Sachin.
-----Original Message-----
From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-owner@vger.kernel.org] On Behalf Of Zhangfei Gao
Sent: Wednesday, June 08, 2011 3:12 PM
To: Arnd Bergmann; Nicolas Pitre; Philip Rakity; Wolfram Sang; Chris Ball; linux-mmc@vger.kernel.org; Jun Nie; Raymond Wu; Haojian Zhuang; Qiming Wu; Eric Miao; linux-arm-kernel
Cc: Zhangfei Gao
Subject: [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
1. support brownstone
2. support mmc
3. support basic filesystem and language
4. remove dynamic_debug, since too many log during access sd
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
---
arch/arm/configs/mmp2_defconfig | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 47ad3b1..5a58452 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MMP=y
+CONFIG_MACH_BROWNSTONE=y
CONFIG_MACH_FLINT=y
CONFIG_MACH_MARVELL_JASPER=y
CONFIG_HIGH_RES_TIMERS=y
@@ -63,10 +64,16 @@ CONFIG_BACKLIGHT_MAX8925=y
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MAX8925=y
+CONFIG_MMC=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
@@ -81,7 +88,7 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_DYNAMIC_DEBUG is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
--
1.7.0.4
--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
@ 2011-06-08 12:53 ` Sachin Nikam
0 siblings, 0 replies; 25+ messages in thread
From: Sachin Nikam @ 2011-06-08 12:53 UTC (permalink / raw)
To: linux-arm-kernel
Hello Folks,
Does anybody knows which kernel version will have the SD 4.0 (UHS-II) support?
Thanks,
Sachin.
-----Original Message-----
From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-owner at vger.kernel.org] On Behalf Of Zhangfei Gao
Sent: Wednesday, June 08, 2011 3:12 PM
To: Arnd Bergmann; Nicolas Pitre; Philip Rakity; Wolfram Sang; Chris Ball; linux-mmc at vger.kernel.org; Jun Nie; Raymond Wu; Haojian Zhuang; Qiming Wu; Eric Miao; linux-arm-kernel
Cc: Zhangfei Gao
Subject: [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
1. support brownstone
2. support mmc
3. support basic filesystem and language
4. remove dynamic_debug, since too many log during access sd
Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
---
arch/arm/configs/mmp2_defconfig | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 47ad3b1..5a58452 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MMP=y
+CONFIG_MACH_BROWNSTONE=y
CONFIG_MACH_FLINT=y
CONFIG_MACH_MARVELL_JASPER=y
CONFIG_HIGH_RES_TIMERS=y
@@ -63,10 +64,16 @@ CONFIG_BACKLIGHT_MAX8925=y
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MAX8925=y
+CONFIG_MMC=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
@@ -81,7 +88,7 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_DYNAMIC_DEBUG is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
--
1.7.0.4
--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
the body of a message to majordomo at vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
2011-06-08 12:53 ` Sachin Nikam
@ 2011-06-08 15:00 ` Arnd Bergmann
-1 siblings, 0 replies; 25+ messages in thread
From: Arnd Bergmann @ 2011-06-08 15:00 UTC (permalink / raw)
To: Sachin Nikam
Cc: 'Zhangfei Gao',
Nicolas Pitre, Philip Rakity, Wolfram Sang, Chris Ball,
linux-mmc, Jun Nie, Raymond Wu, Haojian Zhuang, Qiming Wu,
Eric Miao, linux-arm-kernel
On Wednesday 08 June 2011, Sachin Nikam wrote:
>
> Does anybody knows which kernel version will have the SD 4.0 (UHS-II) support?
The SD 4.0 standard is not yet available, so it cannot be implemented.
I would assume that support will be in the kernel version following the
release of the spec, or one release later if the timing is bad.
If you already have access to the spec, feel free to post patches so
we can include it earlier.
Arnd
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
@ 2011-06-08 15:00 ` Arnd Bergmann
0 siblings, 0 replies; 25+ messages in thread
From: Arnd Bergmann @ 2011-06-08 15:00 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 08 June 2011, Sachin Nikam wrote:
>
> Does anybody knows which kernel version will have the SD 4.0 (UHS-II) support?
The SD 4.0 standard is not yet available, so it cannot be implemented.
I would assume that support will be in the kernel version following the
release of the spec, or one release later if the timing is bad.
If you already have access to the spec, feel free to post patches so
we can include it earlier.
Arnd
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
2011-06-08 15:00 ` Arnd Bergmann
@ 2011-06-09 4:36 ` Sachin Nikam
-1 siblings, 0 replies; 25+ messages in thread
From: Sachin Nikam @ 2011-06-09 4:36 UTC (permalink / raw)
To: 'Arnd Bergmann'
Cc: 'Zhangfei Gao',
Nicolas Pitre, Philip Rakity, Wolfram Sang, Chris Ball,
linux-mmc, Jun Nie, Raymond Wu, Haojian Zhuang, Qiming Wu,
Eric Miao, linux-arm-kernel
Thanks for the reply Arnd.
Sure I will start posting the patches.
Regards,
Sachin Nikam.
-----Original Message-----
From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-owner@vger.kernel.org] On Behalf Of Arnd Bergmann
Sent: Wednesday, June 08, 2011 8:31 PM
To: Sachin Nikam
Cc: 'Zhangfei Gao'; Nicolas Pitre; Philip Rakity; Wolfram Sang; Chris Ball; linux-mmc@vger.kernel.org; Jun Nie; Raymond Wu; Haojian Zhuang; Qiming Wu; Eric Miao; linux-arm-kernel
Subject: Re: [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
On Wednesday 08 June 2011, Sachin Nikam wrote:
>
> Does anybody knows which kernel version will have the SD 4.0 (UHS-II) support?
The SD 4.0 standard is not yet available, so it cannot be implemented.
I would assume that support will be in the kernel version following the
release of the spec, or one release later if the timing is bad.
If you already have access to the spec, feel free to post patches so
we can include it earlier.
Arnd
--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
@ 2011-06-09 4:36 ` Sachin Nikam
0 siblings, 0 replies; 25+ messages in thread
From: Sachin Nikam @ 2011-06-09 4:36 UTC (permalink / raw)
To: linux-arm-kernel
Thanks for the reply Arnd.
Sure I will start posting the patches.
Regards,
Sachin Nikam.
-----Original Message-----
From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-owner at vger.kernel.org] On Behalf Of Arnd Bergmann
Sent: Wednesday, June 08, 2011 8:31 PM
To: Sachin Nikam
Cc: 'Zhangfei Gao'; Nicolas Pitre; Philip Rakity; Wolfram Sang; Chris Ball; linux-mmc at vger.kernel.org; Jun Nie; Raymond Wu; Haojian Zhuang; Qiming Wu; Eric Miao; linux-arm-kernel
Subject: Re: [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc
On Wednesday 08 June 2011, Sachin Nikam wrote:
>
> Does anybody knows which kernel version will have the SD 4.0 (UHS-II) support?
The SD 4.0 standard is not yet available, so it cannot be implemented.
I would assume that support will be in the kernel version following the
release of the spec, or one release later if the timing is bad.
If you already have access to the spec, feel free to post patches so
we can include it earlier.
Arnd
--
To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
the body of a message to majordomo at vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 2/5] mmc: support sdhci-pxav2.c
2011-06-08 9:41 ` Zhangfei Gao
@ 2011-06-13 21:35 ` Philip Rakity
-1 siblings, 0 replies; 25+ messages in thread
From: Philip Rakity @ 2011-06-13 21:35 UTC (permalink / raw)
Cc: Arnd Bergmann, Nicolas Pitre, Wolfram Sang, Chris Ball,
linux-mmc, Jun Nie, Raymond Wu, Haojian Zhuang, Qiming Wu,
Eric Miao, linux-arm-kernel, Zhangfei Gao
On Jun 8, 2011, at 2:41 AM, Zhangfei Gao wrote:
> SDHCI driver for PXAV2 SoCs, such as pxa910, the driver based on sdhci-pltfm to handle resource etc.
>
> Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
> Signed-off-by: Jun Nie <njun@marvell.com>
> Signed-off-by: Qiming Wu <wuqm@marvell.com>
> ---
> +++ b/drivers/mmc/host/sdhci-pxav2.c
> +
> +#define SD_FIFO_PARAM 0xe0
> +#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
> +#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
> +#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
> +#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
> + CLK_GATE_ON | CLK_GATE_CTL)
> +
> +#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
> +#define SDCLK_SEL_SHIFT 8
> +#define SDCLK_SEL_MASK 0x3
> +#define SDCLK_DELAY_SHIFT 10
> +#define SDCLK_DELAY_MASK 0x3c
> +
> +#define SD_CE_ATA_2 0xea
> +#define MMC_CARD 0x1000
> +#define MMC_WIDTH 0x0100
> +
> +static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
> +{
> + struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
> + struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
> +
> + if (mask == SDHCI_RESET_ALL) {
> + u16 tmp = 0;
> +
> + /*
> + * tune timing of read data/command when crc error happen
> + * no performance impact
> + */
> + if (pdata->clk_delay_sel == 1) {
> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> +
> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
> + << SDCLK_DELAY_SHIFT;
> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
> + tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
> +
> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> + }
There are 3 possible value for clk_delay_sel.
0 == do not use clk_delay_cycles
1 == use programmed clk_delay_cycles value (the code above)
all other values use the sd_clk which was used to drive the output
The code about only handles 2 of the 3 cases
suggest
(if (pdata->clk_delay_sel) {
> + if (pdata->clk_delay_sel == 1) {
> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> +
> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
> + << SDCLK_DELAY_SHIFT;
> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
> + tmp |= 1 << SDCLK_SEL_SHIFT;
> +
> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> + } else {
> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
> + tmp |= 2 << SDCLK_SEL_SHIFT;
> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
}
}
Philip and Mark
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 2/5] mmc: support sdhci-pxav2.c
@ 2011-06-13 21:35 ` Philip Rakity
0 siblings, 0 replies; 25+ messages in thread
From: Philip Rakity @ 2011-06-13 21:35 UTC (permalink / raw)
To: linux-arm-kernel
On Jun 8, 2011, at 2:41 AM, Zhangfei Gao wrote:
> SDHCI driver for PXAV2 SoCs, such as pxa910, the driver based on sdhci-pltfm to handle resource etc.
>
> Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com>
> Signed-off-by: Jun Nie <njun@marvell.com>
> Signed-off-by: Qiming Wu <wuqm@marvell.com>
> ---
> +++ b/drivers/mmc/host/sdhci-pxav2.c
> +
> +#define SD_FIFO_PARAM 0xe0
> +#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
> +#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
> +#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
> +#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
> + CLK_GATE_ON | CLK_GATE_CTL)
> +
> +#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
> +#define SDCLK_SEL_SHIFT 8
> +#define SDCLK_SEL_MASK 0x3
> +#define SDCLK_DELAY_SHIFT 10
> +#define SDCLK_DELAY_MASK 0x3c
> +
> +#define SD_CE_ATA_2 0xea
> +#define MMC_CARD 0x1000
> +#define MMC_WIDTH 0x0100
> +
> +static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
> +{
> + struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
> + struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
> +
> + if (mask == SDHCI_RESET_ALL) {
> + u16 tmp = 0;
> +
> + /*
> + * tune timing of read data/command when crc error happen
> + * no performance impact
> + */
> + if (pdata->clk_delay_sel == 1) {
> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> +
> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
> + << SDCLK_DELAY_SHIFT;
> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
> + tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
> +
> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> + }
There are 3 possible value for clk_delay_sel.
0 == do not use clk_delay_cycles
1 == use programmed clk_delay_cycles value (the code above)
all other values use the sd_clk which was used to drive the output
The code about only handles 2 of the 3 cases
suggest
(if (pdata->clk_delay_sel) {
> + if (pdata->clk_delay_sel == 1) {
> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> +
> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
> + << SDCLK_DELAY_SHIFT;
> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
> + tmp |= 1 << SDCLK_SEL_SHIFT;
> +
> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> + } else {
> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
> + tmp |= 2 << SDCLK_SEL_SHIFT;
> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
}
}
Philip and Mark
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 2/5] mmc: support sdhci-pxav2.c
2011-06-13 21:35 ` Philip Rakity
@ 2011-06-14 6:07 ` zhangfei gao
-1 siblings, 0 replies; 25+ messages in thread
From: zhangfei gao @ 2011-06-14 6:07 UTC (permalink / raw)
To: Philip Rakity
Cc: Zhangfei Gao, Eric Miao, Arnd Bergmann, Nicolas Pitre, Qiming Wu,
Jun Nie, linux-mmc, Wolfram Sang, Haojian Zhuang, Raymond Wu,
Chris Ball, linux-arm-kernel
>> +static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
>> +{
>> + struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
>> + struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
>> +
>> + if (mask == SDHCI_RESET_ALL) {
>> + u16 tmp = 0;
>> +
>> + /*
>> + * tune timing of read data/command when crc error happen
>> + * no performance impact
>> + */
>> + if (pdata->clk_delay_sel == 1) {
>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> +
>> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
>> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
>> + << SDCLK_DELAY_SHIFT;
>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>> + tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
>> +
>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> + }
>
> There are 3 possible value for clk_delay_sel.
>
> 0 == do not use clk_delay_cycles
> 1 == use programmed clk_delay_cycles value (the code above)
> all other values use the sd_clk which was used to drive the output
>
> The code about only handles 2 of the 3 cases
pxa910/920 only require two cases.
1, clk_delay_sel = 1 with delay value.
2, use default setting and directly use sd_clk. clk_delay_sel = 3.
>
> suggest
>
> (if (pdata->clk_delay_sel) {
>> + if (pdata->clk_delay_sel == 1) {
>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> +
>> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
>> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
>> + << SDCLK_DELAY_SHIFT;
>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>> + tmp |= 1 << SDCLK_SEL_SHIFT;
>> +
>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> + } else {
>
>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>> + tmp |= 2 << SDCLK_SEL_SHIFT;
>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
The else is default setting on pxa910 after reset.
> }
> }
>
> Philip and Mark
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 2/5] mmc: support sdhci-pxav2.c
@ 2011-06-14 6:07 ` zhangfei gao
0 siblings, 0 replies; 25+ messages in thread
From: zhangfei gao @ 2011-06-14 6:07 UTC (permalink / raw)
To: linux-arm-kernel
>> +static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
>> +{
>> + ? ? struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
>> + ? ? struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
>> +
>> + ? ? if (mask == SDHCI_RESET_ALL) {
>> + ? ? ? ? ? ? u16 tmp = 0;
>> +
>> + ? ? ? ? ? ? /*
>> + ? ? ? ? ? ? ?* tune timing of read data/command when crc error happen
>> + ? ? ? ? ? ? ?* no performance impact
>> + ? ? ? ? ? ? ?*/
>> + ? ? ? ? ? ? if (pdata->clk_delay_sel == 1) {
>> + ? ? ? ? ? ? ? ? ? ? tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> +
>> + ? ? ? ? ? ? ? ? ? ? tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
>> + ? ? ? ? ? ? ? ? ? ? tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? << SDCLK_DELAY_SHIFT;
>> + ? ? ? ? ? ? ? ? ? ? tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>> + ? ? ? ? ? ? ? ? ? ? tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
>> +
>> + ? ? ? ? ? ? ? ? ? ? writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> + ? ? ? ? ? ? }
>
> There are 3 possible value for clk_delay_sel.
>
> 0 ?== do not use clk_delay_cycles
> 1 == use programmed clk_delay_cycles value (the code above)
> all other values use the sd_clk which was used to drive the output
>
> The code about only handles 2 of the 3 cases
pxa910/920 only require two cases.
1, clk_delay_sel = 1 with delay value.
2, use default setting and directly use sd_clk. clk_delay_sel = 3.
>
> suggest
>
> ? ? ? ?(if (pdata->clk_delay_sel) {
>> + ? ? ? ? ? ? if (pdata->clk_delay_sel == 1) {
>> + ? ? ? ? ? ? ? ? ? ? tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> +
>> + ? ? ? ? ? ? ? ? ? ? tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
>> + ? ? ? ? ? ? ? ? ? ? tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? << SDCLK_DELAY_SHIFT;
>> + ? ? ? ? ? ? ? ? ? ? tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>> + ? ? ? ? ? ? ? ? ? ? tmp |= 1 << SDCLK_SEL_SHIFT;
>> +
>> + ? ? ? ? ? ? ? ? ? ? writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> + ? ? ? ? ? ? } else {
>
>> + ? ? ? ? ? ? ? ? ? ? tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>> + ? ? ? ? ? ? ? ? ? ? tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>> + ? ? ? ? ? ? ? ? ? ? tmp |= 2 ?<< SDCLK_SEL_SHIFT;
>> + ? ? ? ? ? ? ? ? ? ? writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
The else is default setting on pxa910 after reset.
> ? ? ? ? ? ? ? ? ? }
> ? ? ? ? }
>
> Philip and Mark
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 2/5] mmc: support sdhci-pxav2.c
2011-06-14 6:07 ` zhangfei gao
@ 2011-06-14 15:00 ` Philip Rakity
-1 siblings, 0 replies; 25+ messages in thread
From: Philip Rakity @ 2011-06-14 15:00 UTC (permalink / raw)
To: zhangfei gao
Cc: Zhangfei Gao, Eric Miao, Arnd Bergmann, Nicolas Pitre, Qiming Wu,
Jun Nie, linux-mmc, Wolfram Sang, Haojian Zhuang, Raymond Wu,
Chris Ball, linux-arm-kernel, Mark Brown
On Jun 13, 2011, at 11:07 PM, zhangfei gao wrote:
>>> +static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
>>> +{
>>> + struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
>>> + struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
>>> +
>>> + if (mask == SDHCI_RESET_ALL) {
>>> + u16 tmp = 0;
>>> +
>>> + /*
>>> + * tune timing of read data/command when crc error happen
>>> + * no performance impact
>>> + */
>>> + if (pdata->clk_delay_sel == 1) {
>>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> +
>>> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
>>> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
>>> + << SDCLK_DELAY_SHIFT;
>>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>>> + tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
>>> +
>>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> + }
>>
>> There are 3 possible value for clk_delay_sel.
>>
>> 0 == do not use clk_delay_cycles
>> 1 == use programmed clk_delay_cycles value (the code above)
>> all other values use the sd_clk which was used to drive the output
>>
>> The code about only handles 2 of the 3 cases
>
> pxa910/920 only require two cases.
> 1, clk_delay_sel = 1 with delay value.
> 2, use default setting and directly use sd_clk. clk_delay_sel = 3.
>
>>
>> suggest
>>
>> (if (pdata->clk_delay_sel) {
>>> + if (pdata->clk_delay_sel == 1) {
>>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> +
>>> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
>>> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
>>> + << SDCLK_DELAY_SHIFT;
>>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>>> + tmp |= 1 << SDCLK_SEL_SHIFT;
>>> +
>>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> + } else {
>>
>>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>>> + tmp |= 2 << SDCLK_SEL_SHIFT;
>>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> The else is default setting on pxa910 after reset.
>> }
>> }
>>
>> Philip and Mark
If you are comfortable not support mode 0 then I am okay with this patch set.
Acked-by: Philip Rakity <prakity@marvell.com>
Acked-by: Mark F. Brown <mark.brown314@gmail.com>
>>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 2/5] mmc: support sdhci-pxav2.c
@ 2011-06-14 15:00 ` Philip Rakity
0 siblings, 0 replies; 25+ messages in thread
From: Philip Rakity @ 2011-06-14 15:00 UTC (permalink / raw)
To: linux-arm-kernel
On Jun 13, 2011, at 11:07 PM, zhangfei gao wrote:
>>> +static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
>>> +{
>>> + struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
>>> + struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
>>> +
>>> + if (mask == SDHCI_RESET_ALL) {
>>> + u16 tmp = 0;
>>> +
>>> + /*
>>> + * tune timing of read data/command when crc error happen
>>> + * no performance impact
>>> + */
>>> + if (pdata->clk_delay_sel == 1) {
>>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> +
>>> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
>>> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
>>> + << SDCLK_DELAY_SHIFT;
>>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>>> + tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
>>> +
>>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> + }
>>
>> There are 3 possible value for clk_delay_sel.
>>
>> 0 == do not use clk_delay_cycles
>> 1 == use programmed clk_delay_cycles value (the code above)
>> all other values use the sd_clk which was used to drive the output
>>
>> The code about only handles 2 of the 3 cases
>
> pxa910/920 only require two cases.
> 1, clk_delay_sel = 1 with delay value.
> 2, use default setting and directly use sd_clk. clk_delay_sel = 3.
>
>>
>> suggest
>>
>> (if (pdata->clk_delay_sel) {
>>> + if (pdata->clk_delay_sel == 1) {
>>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> +
>>> + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
>>> + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
>>> + << SDCLK_DELAY_SHIFT;
>>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>>> + tmp |= 1 << SDCLK_SEL_SHIFT;
>>> +
>>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> + } else {
>>
>>> + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>>> + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
>>> + tmp |= 2 << SDCLK_SEL_SHIFT;
>>> + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
> The else is default setting on pxa910 after reset.
>> }
>> }
>>
>> Philip and Mark
If you are comfortable not support mode 0 then I am okay with this patch set.
Acked-by: Philip Rakity <prakity@marvell.com>
Acked-by: Mark F. Brown <mark.brown314@gmail.com>
>>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 0/5] Provide sdhci driver for mmp2 and pxa9xx
2011-06-08 9:41 ` Zhangfei Gao
` (5 preceding siblings ...)
(?)
@ 2011-06-19 3:16 ` Chris Ball
-1 siblings, 0 replies; 25+ messages in thread
From: Chris Ball @ 2011-06-19 3:16 UTC (permalink / raw)
To: Zhangfei Gao
Cc: Arnd Bergmann, Nicolas Pitre, Philip Rakity, Wolfram Sang, linux-mmc
Hi,
On Wed, Jun 08 2011, Zhangfei Gao wrote:
> v3->v4
> Update patch sequence and mmp2_defconfig
> update driver/mmc/host/Kconfig
> Remove get_ro
>
> The patches to provide separate sdhci driver for mmp2 and pxa910
> based on sdhci-platfm.
> Rename to sdhci-pxav3.c and sdhci-pxav2.c
> Remove obsolete sdhci-pxa.c, which is used to share among pxa serious, since
> under this method, platform difference have to be put under arch/arm,
> which is not easy to track.
> As a result, mmp2 mmc resource should be updated accordingly.
Merged to mmc-next for 3.1. Thanks, everyone!
- Chris.
--
Chris Ball <cjb@laptop.org> <http://printf.net/>
One Laptop Per Child
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2011-06-19 3:16 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-06-08 9:41 [PATCH v4 0/5] Provide sdhci driver for mmp2 and pxa9xx Zhangfei Gao
2011-06-08 9:41 ` Zhangfei Gao
2011-06-08 9:41 ` [PATCH v4 1/5] mmc: support sdhci-pxav3.c Zhangfei Gao
2011-06-08 9:41 ` Zhangfei Gao
2011-06-08 9:41 ` [PATCH v4 2/5] mmc: support sdhci-pxav2.c Zhangfei Gao
2011-06-08 9:41 ` Zhangfei Gao
2011-06-13 21:35 ` Philip Rakity
2011-06-13 21:35 ` Philip Rakity
2011-06-14 6:07 ` zhangfei gao
2011-06-14 6:07 ` zhangfei gao
2011-06-14 15:00 ` Philip Rakity
2011-06-14 15:00 ` Philip Rakity
2011-06-08 9:41 ` [PATCH v4 3/5] ARM: mmp2: update mmp2 mmc resource Zhangfei Gao
2011-06-08 9:41 ` Zhangfei Gao
2011-06-08 9:42 ` [PATCH v4 4/5] mmc: delete obsolete sdhci-pxa.c Zhangfei Gao
2011-06-08 9:42 ` Zhangfei Gao
2011-06-08 9:42 ` [PATCH v4 5/5] ARM: mmp2: update mmp2_defconfig to support mmc Zhangfei Gao
2011-06-08 9:42 ` Zhangfei Gao
2011-06-08 12:53 ` Sachin Nikam
2011-06-08 12:53 ` Sachin Nikam
2011-06-08 15:00 ` Arnd Bergmann
2011-06-08 15:00 ` Arnd Bergmann
2011-06-09 4:36 ` Sachin Nikam
2011-06-09 4:36 ` Sachin Nikam
2011-06-19 3:16 ` [PATCH v4 0/5] Provide sdhci driver for mmp2 and pxa9xx Chris Ball
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