[PATCH RFC 00/14] fix some comment spelling errors

[PATCH RFC 00/14] fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/.
I used spellcheck to check the spelling errors and found some errors in the folder.

The checkpatch.pl file in the Linux kernel can check spelling errors in patches.
I'm trying to add this function to the checkpatch.pl in qemu,
so that no similar spelling errors will occur in the feture.
It's not done yet and I will commit the patch when it's done.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>

zhaolichang (14):
  cris/: fix some comment spelling errors
  ppc/: fix some comment spelling errors
  riscv/: fix some comment spelling errors
  rx/: fix some comment spelling errors
  tricore/: fix some comment spelling errors
  mips/: fix some comment spelling errors
  s390x/: fix some comment spelling errors
  m68k/: fix some comment spelling errors
  sh4/: fix some comment spelling errors
  i386/: fix some comment spelling errors
  avr/: fix some comment spelling errors
  arm/: fix some comment spelling errors
  alpha/: fix some comment spelling errors
  target/: fix some comment spelling errors

 target/alpha/cpu.h               |  4 ++--
 target/alpha/translate.c         |  2 +-
 target/arm/cpu.h                 |  2 +-
 target/arm/helper.c              |  4 ++--
 target/arm/m_helper.c            |  2 +-
 target/arm/translate-a64.c       |  4 ++--
 target/arm/translate-sve.c       |  2 +-
 target/avr/helper.c              |  6 +++---
 target/cris/helper.c             |  6 +++---
 target/cris/op_helper.c          |  2 +-
 target/cris/translate.c          | 14 +++++++-------
 target/i386/cpu.c                |  4 ++--
 target/i386/hax-interface.h      |  4 ++--
 target/i386/hax-windows.c        |  2 +-
 target/i386/kvm.c                |  2 +-
 target/i386/machine.c            |  6 +++---
 target/i386/translate.c          |  8 ++++----
 target/i386/whpx-all.c           |  2 +-
 target/m68k/translate.c          | 16 ++++++++--------
 target/mips/internal.h           |  2 +-
 target/mips/translate.c          | 10 +++++-----
 target/mips/translate_init.c.inc |  2 +-
 target/openrisc/cpu.h            |  2 +-
 target/ppc/cpu.h                 |  6 +++---
 target/ppc/excp_helper.c         |  6 +++---
 target/ppc/fpu_helper.c          |  2 +-
 target/ppc/internal.h            |  2 +-
 target/ppc/kvm.c                 |  2 +-
 target/ppc/machine.c             |  2 +-
 target/ppc/mmu-hash64.c          |  2 +-
 target/ppc/mmu_helper.c          |  4 ++--
 target/ppc/translate_init.c.inc  |  2 +-
 target/riscv/cpu.c               |  2 +-
 target/riscv/cpu_bits.h          |  2 +-
 target/riscv/csr.c               |  6 +++---
 target/riscv/vector_helper.c     |  2 +-
 target/rx/op_helper.c            |  2 +-
 target/rx/translate.c            |  2 +-
 target/s390x/cpu_models.h        |  4 ++--
 target/s390x/excp_helper.c       |  2 +-
 target/s390x/fpu_helper.c        |  2 +-
 target/s390x/insn-data.def       |  2 +-
 target/s390x/ioinst.c            |  2 +-
 target/s390x/misc_helper.c       |  2 +-
 target/s390x/translate.c         |  4 ++--
 target/s390x/translate_vx.c.inc  |  2 +-
 target/sh4/cpu.h                 |  2 +-
 target/sh4/op_helper.c           |  2 +-
 target/sh4/translate.c           |  2 +-
 target/sparc/asi.h               |  2 +-
 target/tricore/csfr.def          |  2 +-
 target/tricore/translate.c       |  2 +-
 target/unicore32/translate.c     |  2 +-
 53 files changed, 93 insertions(+), 93 deletions(-)

-- 
2.26.2.windows.1

[PATCH RFC 01/14] cris/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/cris.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/cris/helper.c    |  6 +++---
 target/cris/op_helper.c |  2 +-
 target/cris/translate.c | 14 +++++++-------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/target/cris/helper.c b/target/cris/helper.c
index b5159b8..50419e7 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -141,7 +141,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
     assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
     switch (cs->exception_index) {
     case EXCP_BREAK:
-        /* These exceptions are genereated by the core itself.
+        /* These exceptions are generated by the core itself.
            ERP should point to the insn following the brk.  */
         ex_vec = env->trap_vector;
         env->pregs[PRV10_BRP] = env->pc;
@@ -197,7 +197,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
 
     switch (cs->exception_index) {
     case EXCP_BREAK:
-        /* These exceptions are genereated by the core itself.
+        /* These exceptions are generated by the core itself.
            ERP should point to the insn following the brk.  */
         ex_vec = env->trap_vector;
         env->pregs[PR_ERP] = env->pc;
@@ -256,7 +256,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
        undefined.  */
     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 
-    /* Clear the excption_index to avoid spurios hw_aborts for recursive
+    /* Clear the excption_index to avoid spurious hw_aborts for recursive
        bus faults.  */
     cs->exception_index = -1;
 
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index 6b1e7ae..3c4aacc 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -231,7 +231,7 @@ static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
 {
     unsigned int x, z, mask;
 
-    /* Extended arithmetics, leave the z flag alone.  */
+    /* Extended arithmetic, leave the z flag alone.  */
     x = env->cc_x;
     mask = env->cc_mask | X_FLAG;
     if (x) {
diff --git a/target/cris/translate.c b/target/cris/translate.c
index c312e6f..16b0ef8 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -348,7 +348,7 @@ static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
     tcg_temp_free(t);
 }
 
-/* Extended arithmetics on CRIS.  */
+/* Extended arithmetic on CRIS.  */
 static inline void t_gen_add_flag(TCGv d, int flag)
 {
     TCGv c;
@@ -725,7 +725,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
     switch (op) {
     case CC_OP_ADD:
         tcg_gen_add_tl(dst, a, b);
-        /* Extended arithmetics.  */
+        /* Extended arithmetic.  */
         t_gen_addx_carry(dc, dst);
         break;
     case CC_OP_ADDC:
@@ -738,7 +738,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
         break;
     case CC_OP_SUB:
         tcg_gen_sub_tl(dst, a, b);
-        /* Extended arithmetics.  */
+        /* Extended arithmetic.  */
         t_gen_subx_carry(dc, dst);
         break;
     case CC_OP_MOVE:
@@ -764,7 +764,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
         break;
     case CC_OP_NEG:
         tcg_gen_neg_tl(dst, b);
-        /* Extended arithmetics.  */
+        /* Extended arithmetic.  */
         t_gen_subx_carry(dc, dst);
         break;
     case CC_OP_LZ:
@@ -787,7 +787,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
         break;
     case CC_OP_CMP:
         tcg_gen_sub_tl(dst, a, b);
-        /* Extended arithmetics.  */
+        /* Extended arithmetic.  */
         t_gen_subx_carry(dc, dst);
         break;
     default:
@@ -3053,12 +3053,12 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
  * On QEMU care needs to be taken when a branch+delayslot sequence is broken
  * and the branch and delayslot don't share pages.
  *
- * The TB contaning the branch insn will set up env->btarget and evaluate 
+ * The TB containing the branch insn will set up env->btarget and evaluate 
  * env->btaken. When the translation loop exits we will note that the branch 
  * sequence is broken and let env->dslot be the size of the branch insn (those
  * vary in length).
  *
- * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
+ * The TB containing the delayslot will have the PC of its real insn (i.e no lsb
  * set). It will also expect to have env->dslot setup with the size of the 
  * delay slot so that env->pc - env->dslot point to the branch insn. This TB 
  * will execute the dslot and take the branch, either to btarget or just one 
-- 
2.26.2.windows.1

[PATCH RFC 02/14] ppc/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/ppc.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/ppc/cpu.h                | 6 +++---
 target/ppc/excp_helper.c        | 6 +++---
 target/ppc/fpu_helper.c         | 2 +-
 target/ppc/internal.h           | 2 +-
 target/ppc/kvm.c                | 2 +-
 target/ppc/machine.c            | 2 +-
 target/ppc/mmu-hash64.c         | 2 +-
 target/ppc/mmu_helper.c         | 4 ++--
 target/ppc/translate_init.c.inc | 2 +-
 9 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 766e9c5..ba5ebb1 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -615,7 +615,7 @@ enum {
 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
-#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
+#define FPSCR_UE     5  /* Floating-point underflow exception enable          */
 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
@@ -2331,13 +2331,13 @@ enum {
     /* Internal hardware exception sources */
     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
-    PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
+    PPC_INTERRUPT_PIT,            /* Programmable interval timer interrupt */
     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
-    PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
+    PPC_INTERRUPT_HMI,            /* Hypervisor Maintenance interrupt    */
     PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
     PPC_INTERRUPT_HVIRT,          /* Hypervisor virtualization interrupt  */
 };
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a988ba1..d7411bc 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -231,7 +231,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
     }
 
     /*
-     * Exception targetting modifiers
+     * Exception targeting modifiers
      *
      * LPES0 is supported on POWER7/8/9
      * LPES1 is not supported (old iSeries mode)
@@ -1015,7 +1015,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
          * This means we will incorrectly execute past the power management
          * instruction instead of triggering a reset.
          *
-         * It generally means a discrepancy between the wakup conditions in the
+         * It generally means a discrepancy between the wakeup conditions in the
          * processor has_work implementation and the logic in this function.
          */
         cpu_abort(env_cpu(env),
@@ -1191,7 +1191,7 @@ void helper_rfi(CPUPPCState *env)
 void helper_rfid(CPUPPCState *env)
 {
     /*
-     * The architeture defines a number of rules for which bits can
+     * The architecture defines a number of rules for which bits can
      * change but in practice, we handle this in hreg_store_msr()
      * which will be called by do_rfi(), so there is no need to filter
      * here
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ae43b08..9b8c8b7 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1804,7 +1804,7 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
 
 
 /*
- * VSX_ADD_SUB - VSX floating point add/subract
+ * VSX_ADD_SUB - VSX floating point add/subtract
  *   name  - instruction mnemonic
  *   op    - operation (add or sub)
  *   nels  - number of elements (1, 2 or 4)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 15d655b..b4df127 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -1,5 +1,5 @@
 /*
- *  PowerPC interal definitions for qemu.
+ *  PowerPC internal definitions for qemu.
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index d85ba8f..e85ef2e 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -487,7 +487,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
             /*
              * KVM-HV has transactional memory on POWER8 also without
              * the KVM_CAP_PPC_HTM extension, so enable it here
-             * instead as long as it's availble to userspace on the
+             * instead as long as it's available to userspace on the
              * host.
              */
             if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 109d071..f6a24a9 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -337,7 +337,7 @@ static int cpu_post_load(void *opaque, int version_id)
 
     /*
      * If we're operating in compat mode, we should be ok as long as
-     * the destination supports the same compatiblity mode.
+     * the destination supports the same compatibility mode.
      *
      * Otherwise, however, we require that the destination has exactly
      * the same CPU model as the source.
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index c31d21e..977b2d1 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -883,7 +883,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
     /*
      * Note on LPCR usage: 970 uses HID4, but our special variant of
      * store_spr copies relevant fields into env->spr[SPR_LPCR].
-     * Similarily we filter unimplemented bits when storing into LPCR
+     * Similarly we filter unimplemented bits when storing into LPCR
      * depending on the MMU version. This code can thus just use the
      * LPCR "as-is".
      */
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 8972714..50aa18a 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -179,7 +179,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
             }
             /* Compute access rights */
             access = pp_check(ctx->key, pp, ctx->nx);
-            /* Keep the matching PTE informations */
+            /* Keep the matching PTE information */
             ctx->raddr = pte1;
             ctx->prot = access;
             ret = check_prot(ctx->prot, rw, type);
@@ -2176,7 +2176,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
         env->sr[srnum] = value;
         /*
          * Invalidating 256MB of virtual memory in 4kB pages is way
-         * longer than flusing the whole TLB.
+         * longer than flushing the whole TLB.
          */
 #if !defined(FLUSH_ALL_TLBS) && 0
         {
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index bb66526..3e0810f 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -792,7 +792,7 @@ static void gen_spr_generic(CPUPPCState *env)
                  &spr_read_xer, &spr_write_xer,
                  &spr_read_xer, &spr_write_xer,
                  0x00000000);
-    /* Branch contol */
+    /* Branch control */
     spr_register(env, SPR_LR, "LR",
                  &spr_read_lr, &spr_write_lr,
                  &spr_read_lr, &spr_write_lr,
-- 
2.26.2.windows.1

[PATCH RFC 03/14] riscv/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/riscv.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/riscv/cpu.c           | 2 +-
 target/riscv/cpu_bits.h      | 2 +-
 target/riscv/csr.c           | 6 +++---
 target/riscv/vector_helper.c | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f..f40a0b2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
                     return;
                 }
             } else {
-                qemu_log("vector verison is not specified, "
+                qemu_log("vector version is not specified, "
                         "use the default value v0.7.1\n");
             }
             set_vext_version(env, vext_version);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index bd36062..6e11555 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -536,7 +536,7 @@
 /* Leaf page shift amount */
 #define PGSHIFT             12
 
-/* Default Reset Vector adress */
+/* Default Reset Vector address */
 #define DEFAULT_RSTVEC      0x1000
 
 /* Exception causes */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 26ae347..559db11 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
+/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (env->priv_ver < PRIV_VERSION_1_11_0) {
@@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
     return 0;
 }
 
-/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
+/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 {
     if (env->priv_ver < PRIV_VERSION_1_11_0) {
@@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
         !riscv_cpu_virt_enabled(env)) {
         /*
          * We are in S mode without virtualisation, therefore we are in HS Mode.
-         * Add 1 to the effective privledge level to allow us to access the
+         * Add 1 to the effective privilege level to allow us to access the
          * Hypervisor CSRs.
          */
         effective_priv++;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a156573..fa89a6e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
                                   uint32_t wd, uint32_t idx, CPURISCVState *env,
                                   uintptr_t retaddr);
 
-/* no atomic opreation for vector atomic insructions */
+/* no atomic operation for vector atomic insructions */
 #define DO_SWAP(N, M) (M)
 #define DO_AND(N, M)  (N & M)
 #define DO_XOR(N, M)  (N ^ M)
-- 
2.26.2.windows.1

[PATCH RFC 04/14] rx/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/rx.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/rx/op_helper.c | 2 +-
 target/rx/translate.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index f89d294..59389f4 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
     env->psw_c = (tmp <= env->regs[2]);
 }
 
-/* accumlator operations */
+/* accumulator operations */
 void helper_rmpa(CPURXState *env, uint32_t sz)
 {
     uint64_t result_l, prev;
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 482278e..9ea941c 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_gen_xor_i32(temp, arg1, arg2);
     tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
     tcg_temp_free_i32(temp);
-    /* CMP not requred return */
+    /* CMP not required return */
     if (ret) {
         tcg_gen_mov_i32(ret, cpu_psw_s);
     }
-- 
2.26.2.windows.1

[PATCH RFC 05/14] tricore/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/tricore.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/s390x/ioinst.c      | 2 +-
 target/tricore/csfr.def    | 2 +-
 target/tricore/translate.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c
index a412926..c576d85 100644
--- a/target/s390x/ioinst.c
+++ b/target/s390x/ioinst.c
@@ -279,7 +279,7 @@ void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
         /*
          * As operand exceptions have a lower priority than access exceptions,
          * we check whether the memory area is writeable (injecting the
-         * access execption if it is not) first.
+         * access exception if it is not) first.
          */
         if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) {
             s390_program_interrupt(env, PGM_OPERAND, ra);
diff --git a/target/tricore/csfr.def b/target/tricore/csfr.def
index ff004cb..cdfaf1d 100644
--- a/target/tricore/csfr.def
+++ b/target/tricore/csfr.def
@@ -1,4 +1,4 @@
-/* A(ll) access permited
+/* A(ll) access permitted
    R(ead only) access
    E(nd init protected) access
 
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7752630..c9c420d 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -397,7 +397,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
 #undef E
 
 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
-                                    since no execption occurs */
+                                    since no exception occurs */
 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)                \
     case ADDRESS:                                                        \
         if (has_feature(ctx, FEATURE)) {                             \
-- 
2.26.2.windows.1

[PATCH RFC 06/14] mips/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/mips.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/mips/internal.h           |  2 +-
 target/mips/translate.c          | 10 +++++-----
 target/mips/translate_init.c.inc |  2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9..b811f54 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -188,7 +188,7 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
         /*
          * A MIPS configured with a vectorizing external interrupt controller
          * will feed a vector into the Cause pending lines. The core treats
-         * the status lines as a vector level, not as indiviual masks.
+         * the status lines as a vector level, not as individual masks.
          */
         r = pending > status;
     } else {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf7..b4d0090 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3718,7 +3718,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
 
     t0 = tcg_temp_new();
     addr = tcg_temp_new();
-    /* compare the address against that of the preceeding LL */
+    /* compare the address against that of the preceding LL */
     gen_base_offset_addr(ctx, addr, base, offset);
     tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
     tcg_temp_free(addr);
@@ -25597,7 +25597,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
         }
         /* return resulting half-words to its original position */
         tcg_gen_shri_i32(t0, t0, 16);
-        /* finaly update the destination */
+        /* finally update the destination */
         tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
 
         tcg_temp_free(t1);
@@ -25633,7 +25633,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
         }
         /* return resulting half-words to its original position */
         tcg_gen_shri_i32(t0, t0, 16);
-        /* finaly update the destination */
+        /* finally update the destination */
         tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
 
         tcg_temp_free(t1);
@@ -25702,7 +25702,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
             }
             /* return resulting byte to its original position */
             tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
-            /* finaly update the destination */
+            /* finally update the destination */
             tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
         }
 
@@ -25742,7 +25742,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
             }
             /* return resulting byte to its original position */
             tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
-            /* finaly update the destination */
+            /* finally update the destination */
             tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
         }
 
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 637cacc..c735b2b 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -995,7 +995,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
 
     /* MVPConf1 implemented, TLB sharable, no gating storage support,
        programmable cache partitioning implemented, number of allocatable
-       and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
+       and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
        implemented, 5 TCs implemented. */
     env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
-- 
2.26.2.windows.1

[PATCH RFC 07/14] s390x/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/s390x.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/s390x/cpu_models.h       | 4 ++--
 target/s390x/excp_helper.c      | 2 +-
 target/s390x/fpu_helper.c       | 2 +-
 target/s390x/insn-data.def      | 2 +-
 target/s390x/misc_helper.c      | 2 +-
 target/s390x/translate.c        | 4 ++--
 target/s390x/translate_vx.c.inc | 2 +-
 7 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h
index 74d1f87..15c0f0d 100644
--- a/target/s390x/cpu_models.h
+++ b/target/s390x/cpu_models.h
@@ -24,13 +24,13 @@ struct S390CPUDef {
     uint8_t gen;            /* hw generation identification */
     uint16_t type;          /* cpu type identification */
     uint8_t ec_ga;          /* EC GA version (on which also the BC is based) */
-    uint8_t mha_pow;        /* Maximum Host Adress Power, mha = 2^pow-1 */
+    uint8_t mha_pow;        /* Maximum Host Address Power, mha = 2^pow-1 */
     uint32_t hmfai;         /* hypervisor-managed facilities */
     /* base/min features, must never be changed between QEMU versions */
     S390FeatBitmap base_feat;
     /* used to init base_feat from generated data */
     S390FeatInit base_init;
-    /* deafault features, QEMU version specific */
+    /* default features, QEMU version specific */
     S390FeatBitmap default_feat;
     /* used to init default_feat from generated data */
     S390FeatInit default_init;
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 3b58d10..9644a67 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -538,7 +538,7 @@ try_deliver:
         /* don't trigger a cpu_loop_exit(), use an interrupt instead */
         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HALT);
     } else if (cs->halted) {
-        /* unhalt if we had a WAIT PSW somehwere in our injection chain */
+        /* unhalt if we had a WAIT PSW somewhere in our injection chain */
         s390_cpu_unhalt(cpu);
     }
 }
diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c
index f155bc0..3e609b7 100644
--- a/target/s390x/fpu_helper.c
+++ b/target/s390x/fpu_helper.c
@@ -89,7 +89,7 @@ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr)
     /*
      * invalid/divbyzero cannot coexist with other conditions.
      * overflow/underflow however can coexist with inexact, we have to
-     * handle it separatly.
+     * handle it separately.
      */
     if (s390_exc & ~S390_IEEE_MASK_INEXACT) {
         if (s390_exc & ~S390_IEEE_MASK_INEXACT & env->fpc >> 24) {
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d79ae9e..1631948 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -523,7 +523,7 @@
 /* LOAD LOGICAL HALFWORD RELATIVE LONG */
     C(0xc402, LLHRL,   RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0)
     C(0xc406, LLGHRL,  RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0)
-/* LOAD LOGICAL IMMEDATE */
+/* LOAD LOGICAL IMMEDIATE */
     D(0xc00e, LLIHF,   RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32)
     D(0xc00f, LLILF,   RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0)
     D(0xa50c, LLIHH,   RI_a,  Z,  0, i2_16u_shl, 0, r1, mov2, 0, 48)
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
index 58dbc02..929e509 100644
--- a/target/s390x/misc_helper.c
+++ b/target/s390x/misc_helper.c
@@ -312,7 +312,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1)
             /* same as machine type number in STORE CPU ID, but in EBCDIC */
             snprintf(type, ARRAY_SIZE(type), "%X", cpu->model->def->type);
             ebcdic_put(sysib.sysib_111.type, type, 4);
-            /* model number (not stored in STORE CPU ID for z/Architecure) */
+            /* model number (not stored in STORE CPU ID for z/Architecture) */
             ebcdic_put(sysib.sysib_111.model, "QEMU            ", 16);
             ebcdic_put(sysib.sysib_111.sequence, "QEMU            ", 16);
             ebcdic_put(sysib.sysib_111.plant, "QEMU", 4);
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index a777343..58ad6c8 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -433,7 +433,7 @@ static void gen_program_exception(DisasContext *s, int code)
 {
     TCGv_i32 tmp;
 
-    /* Remember what pgm exeption this was.  */
+    /* Remember what pgm exception this was.  */
     tmp = tcg_const_i32(code);
     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
     tcg_temp_free_i32(tmp);
@@ -489,7 +489,7 @@ static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
 
     /*
      * Note that d2 is limited to 20 bits, signed.  If we crop negative
-     * displacements early we create larger immedate addends.
+     * displacements early we create larger immediate addends.
      */
     if (b2 && x2) {
         tcg_gen_add_i64(tmp, regs[b2], regs[x2]);
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index eb767f5..983da56 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -789,7 +789,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
         }
         break;
     case 0x94:
-        /* If sources and destination dont't overlap -> fast path */
+        /* If sources and destination don't overlap -> fast path */
         if (v1 != v2 && v1 != v3) {
             const uint8_t src_es = get_field(s, m4);
             const uint8_t dst_es = src_es - 1;
-- 
2.26.2.windows.1

[PATCH RFC 08/14] m68k/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/m68k.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/m68k/translate.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 3fc67aa..133a404 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -438,7 +438,7 @@ static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
 }
 
 /*
- * Handle a base + index + displacement effective addresss.
+ * Handle a base + index + displacement effective address.
  * A NULL_QREG base means pc-relative.
  */
 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
@@ -1696,7 +1696,7 @@ static void bcd_add(TCGv dest, TCGv src)
 
     /*
      * t1 = (src + 0x066) + dest + X
-     *    = result with some possible exceding 0x6
+     *    = result with some possible exceeding 0x6
      */
 
     t0 = tcg_const_i32(0x066);
@@ -1706,7 +1706,7 @@ static void bcd_add(TCGv dest, TCGv src)
     tcg_gen_add_i32(t1, t0, dest);
     tcg_gen_add_i32(t1, t1, QREG_CC_X);
 
-    /* we will remove exceding 0x6 where there is no carry */
+    /* we will remove exceeding 0x6 where there is no carry */
 
     /*
      * t0 = (src + 0x0066) ^ dest
@@ -1736,7 +1736,7 @@ static void bcd_add(TCGv dest, TCGv src)
     tcg_temp_free(t0);
 
     /*
-     * remove the exceding 0x6
+     * remove the exceeding 0x6
      * for digits that have not generated a carry
      */
 
@@ -2638,7 +2638,7 @@ DISAS_INSN(negx)
     gen_flush_flags(s); /* compute old Z */
 
     /*
-     * Perform substract with borrow.
+     * Perform subtract with borrow.
      * (X, N) =  -(src + X);
      */
 
@@ -2653,7 +2653,7 @@ DISAS_INSN(negx)
     /*
      * Compute signed-overflow for negation.  The normal formula for
      * subtraction is (res ^ src) & (src ^ dest), but with dest==0
-     * this simplies to res & src.
+     * this simplifies to res & src.
      */
 
     tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
@@ -3159,7 +3159,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
     gen_flush_flags(s); /* compute old Z */
 
     /*
-     * Perform substract with borrow.
+     * Perform subtract with borrow.
      * (X, N) = dest - (src + X);
      */
 
@@ -3169,7 +3169,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
     gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
     tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
 
-    /* Compute signed-overflow for substract.  */
+    /* Compute signed-overflow for subtract.  */
 
     tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
     tcg_gen_xor_i32(tmp, dest, src);
-- 
2.26.2.windows.1

[PATCH RFC 09/14] sh4/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/sh4.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/sh4/cpu.h       | 2 +-
 target/sh4/op_helper.c | 2 +-
 target/sh4/translate.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dbe58c7..91fa949 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -160,7 +160,7 @@ typedef struct CPUSH4State {
     uint32_t pteh;		/* page table entry high register */
     uint32_t ptel;		/* page table entry low register */
     uint32_t ptea;		/* page table entry assistance register */
-    uint32_t ttb;		/* tranlation table base register */
+    uint32_t ttb;		/* translation table base register */
     uint32_t tea;		/* TLB exception address register */
     uint32_t tra;		/* TRAPA exception register */
     uint32_t expevt;		/* exception event register */
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 14c3db0..9de4152 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -400,7 +400,7 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
     t0 = float32_div(float32_one, t0, &env->fp_status);
     /* Since this is supposed to be an approximation, an imprecision
        exception is required.  One supposes this also follows the usual
-       IEEE rule that other exceptions take precidence.  */
+       IEEE rule that other exceptions take precedence.  */
     if (get_float_exception_flags(&env->fp_status) == 0) {
         set_float_exception_flags(float_flag_inexact, &env->fp_status);
     }
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 60c863d..c57218e 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1959,7 +1959,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
     NEXT_INSN;
     switch (ctx->opcode & 0xf00f) {
     case 0x6003: /* mov Rm,Rn */
-        /* Here we want to recognize ld_dst being saved for later consumtion,
+        /* Here we want to recognize ld_dst being saved for later consumption,
            or for another input register being copied so that ld_dst need not
            be clobbered during the operation.  */
         op_dst = B11_8;
-- 
2.26.2.windows.1

[PATCH RFC 10/14] i386/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/i386.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/i386/cpu.c           | 4 ++--
 target/i386/hax-interface.h | 4 ++--
 target/i386/hax-windows.c   | 2 +-
 target/i386/kvm.c           | 2 +-
 target/i386/machine.c       | 6 +++---
 target/i386/translate.c     | 8 ++++----
 target/i386/whpx-all.c      | 2 +-
 7 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3ffd877..23851e5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4677,7 +4677,7 @@ static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
     return name;
 }
 
-/* Compatibily hack to maintain legacy +-feat semantic,
+/* Compatibility hack to maintain legacy +-feat semantic,
  * where +-feat overwrites any feature set by
  * feat=on|feat even if the later is parsed after +-feat
  * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
@@ -6896,7 +6896,7 @@ static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
     GuestPanicInformation *panic_info;
 
     if (!cs->crash_occurred) {
-        error_setg(errp, "No crash occured");
+        error_setg(errp, "No crash occurred");
         return;
     }
 
diff --git a/target/i386/hax-interface.h b/target/i386/hax-interface.h
index 537ae08..edef4fd 100644
--- a/target/i386/hax-interface.h
+++ b/target/i386/hax-interface.h
@@ -238,7 +238,7 @@ enum exit_status {
     HAX_EXIT_UNKNOWN_VMEXIT,
     /* HALT from guest */
     HAX_EXIT_HLT,
-    /* Reboot request, like because of tripple fault in guest */
+    /* Reboot request, like because of triple fault in guest */
     HAX_EXIT_STATECHANGE,
     /* the vcpu is now only paused when destroy, so simply return to hax */
     HAX_EXIT_PAUSED,
@@ -295,7 +295,7 @@ struct hax_qemu_version {
     uint32_t min_version;
 } __attribute__ ((__packed__));
 
-/* The mac specfic interface to qemu, mostly is ioctl related */
+/* The mac specific interface to qemu, mostly is ioctl related */
 struct hax_tunnel_info {
     uint64_t va;
     uint64_t io_va;
diff --git a/target/i386/hax-windows.c b/target/i386/hax-windows.c
index 863c2bc..881089b 100644
--- a/target/i386/hax-windows.c
+++ b/target/i386/hax-windows.c
@@ -174,7 +174,7 @@ int hax_mod_version(struct hax_state *hax, struct hax_module_version *version)
     if (!ret) {
         err = GetLastError();
         if (err == ERROR_INSUFFICIENT_BUFFER || err == ERROR_MORE_DATA) {
-            fprintf(stderr, "hax module verion is too long to hold.\n");
+            fprintf(stderr, "hax module version is too long to hold.\n");
         }
         fprintf(stderr, "Failed to get Hax module version:%lu\n", err);
         return -EFAULT;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 9efb07e..fbdbb49 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1179,7 +1179,7 @@ static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
 /*
  * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
  * case of success, errno < 0 in case of failure and 0 when no Hyper-V
- * extentions are enabled.
+ * extensions are enabled.
  */
 static int hyperv_handle_properties(CPUState *cs,
                                     struct kvm_cpuid_entry2 *cpuid_ent)
diff --git a/target/i386/machine.c b/target/i386/machine.c
index b1acf7d..90e6139 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -264,12 +264,12 @@ static int cpu_pre_save(void *opaque)
      * hypervisor, its exception payload (CR2/DR6 on #PF/#DB)
      * should not be set yet in the respective vCPU register.
      * Thus, in case an exception is pending, it is
-     * important to save the exception payload seperately.
+     * important to save the exception payload separately.
      *
      * Therefore, if an exception is not in a pending state
      * or vCPU is not in guest-mode, it is not important to
      * distinguish between a pending and injected exception
-     * and we don't need to store seperately the exception payload.
+     * and we don't need to store separately the exception payload.
      *
      * In order to preserve better backwards-compatible migration,
      * convert a pending exception to an injected exception in
@@ -1138,7 +1138,7 @@ static int nested_state_post_load(void *opaque, int version_id)
         return -EINVAL;
     }
     if (nested_state->size > max_nested_state_len) {
-        error_report("Recieved unsupported nested state size: "
+        error_report("Received unsupported nested state size: "
                      "nested_state->size=%d, max=%d",
                      nested_state->size, max_nested_state_len);
         return -EINVAL;
diff --git a/target/i386/translate.c b/target/i386/translate.c
index caea6f5..5cdfe0e 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -893,7 +893,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
 }
 
 /* perform a conditional store into register 'reg' according to jump opcode
-   value 'b'. In the fast case, T0 is guaranted not to be used. */
+   value 'b'. In the fast case, T0 is guaranteed not to be used. */
 static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
 {
     int inv, jcc_op, cond;
@@ -1026,7 +1026,7 @@ static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg)
 }
 
 /* generate a conditional jump to label 'l1' according to jump opcode
-   value 'b'. In the fast case, T0 is guaranted not to be used. */
+   value 'b'. In the fast case, T0 is guaranteed not to be used. */
 static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1)
 {
     CCPrepare cc = gen_prepare_cc(s, b, s->T0);
@@ -1043,7 +1043,7 @@ static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1)
 }
 
 /* Generate a conditional jump to label 'l1' according to jump opcode
-   value 'b'. In the fast case, T0 is guaranted not to be used.
+   value 'b'. In the fast case, T0 is guaranteed not to be used.
    A translation block must end soon.  */
 static inline void gen_jcc1(DisasContext *s, int b, TCGLabel *l1)
 {
@@ -6841,7 +6841,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
         if (s->prefix & PREFIX_LOCK) {
             switch (op) {
             case 0: /* bt */
-                /* Needs no atomic ops; we surpressed the normal
+                /* Needs no atomic ops; we suppressed the normal
                    memory load for LOCK above so do it now.  */
                 gen_op_ld_v(s, ot, s->T0, s->A0);
                 break;
diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c
index 5a0f337..661f9c7 100644
--- a/target/i386/whpx-all.c
+++ b/target/i386/whpx-all.c
@@ -1214,7 +1214,7 @@ int whpx_init_vcpu(CPUState *cpu)
     vcpu = g_malloc0(sizeof(struct whpx_vcpu));
 
     if (!vcpu) {
-        error_report("WHPX: Failed to allocte VCPU context.");
+        error_report("WHPX: Failed to allocate VCPU context.");
         return -ENOMEM;
     }
 
-- 
2.26.2.windows.1

[PATCH RFC 11/14] avr/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/avr.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/avr/helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/avr/helper.c b/target/avr/helper.c
index d96d143..9f325bc 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -97,7 +97,7 @@ int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
 
 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
-    return addr; /* I assume 1:1 address correspondance */
+    return addr; /* I assume 1:1 address correspondence */
 }
 
 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@@ -298,7 +298,7 @@ void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
 }
 
 /*
- *  this function implements LD instruction when there is a posibility to read
+ *  this function implements LD instruction when there is a possibility to read
  *  from a CPU register
  */
 target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
@@ -322,7 +322,7 @@ target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
 }
 
 /*
- *  this function implements ST instruction when there is a posibility to write
+ *  this function implements ST instruction when there is a possibility to write
  *  into a CPU register
  */
 void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
-- 
2.26.2.windows.1

[PATCH RFC 12/14] arm/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/arm.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/arm/cpu.h           | 2 +-
 target/arm/helper.c        | 4 ++--
 target/arm/m_helper.c      | 2 +-
 target/arm/translate-a64.c | 4 ++--
 target/arm/translate-sve.c | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6036f61..996308b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2067,7 +2067,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
     return aa64;
 }
 
-/* Function for determing whether guest cp register reads and writes should
+/* Function for determining whether guest cp register reads and writes should
  * access the secure or non-secure bank of a cp register.  When EL3 is
  * operating in AArch32 state, the NS-bit determines whether the secure
  * instance of a cp register should be used. When EL3 is AArch64 (or if
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 88bd9dd..9292e16 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1867,7 +1867,7 @@ static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
      * pmevtyper_rawwrite is called between a pair of pmu_op_start and
      * pmu_op_finish calls when loading saved state for a migration. Because
      * we're potentially updating the type of event here, the value written to
-     * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
+     * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
      * different counter type. Therefore, we need to set this value to the
      * current count for the counter type we're writing so that pmu_op_finish
      * has the correct count for its calculation.
@@ -12214,7 +12214,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
             } else {
                 memattr = 0x44;  /* Normal, NC, No */
             }
-            cacheattrs->shareability = 2; /* outer sharable */
+            cacheattrs->shareability = 2; /* outer shareable */
         } else {
             memattr = 0x00;      /* Device, nGnRnE */
         }
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 0364542..1e8080d 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -158,7 +158,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
      *  R: 0 because unpriv and A flag not set
      *  SRVALID: 0 because NS
      *  MRVALID: 0 because unpriv and A flag not set
-     *  SREGION: 0 becaus SRVALID is 0
+     *  SREGION: 0 because SRVALID is 0
      *  MREGION: 0 because MRVALID is 0
      */
     return 0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7188808..5451f02 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -160,7 +160,7 @@ void gen_a64_set_pc_im(uint64_t val)
  *  + for EL2 and EL3 there is only one TBI bit, and if it is set
  *    then the address is zero-extended, clearing bits [63:56]
  *  + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
- *    and TBI1 controls addressses with bit 55 == 1.
+ *    and TBI1 controls addresses with bit 55 == 1.
  *    If the appropriate TBI bit is set for the address then
  *    the address is sign-extended from bit 55 into bits [63:56]
  *
@@ -1964,7 +1964,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
     }
     if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
         /*
-         * A write to any coprocessor regiser that ends a TB
+         * A write to any coprocessor register that ends a TB
          * must rebuild the hflags for the next TB.
          */
         TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index e4cd6b6..4e8a1c7 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1528,7 +1528,7 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
 
 /* Perform an inline saturating addition of a 32-bit value within
  * a 64-bit register.  The second operand is known to be positive,
- * which halves the comparisions we must perform to bound the result.
+ * which halves the comparisons we must perform to bound the result.
  */
 static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
 {
-- 
2.26.2.windows.1

[PATCH RFC 13/14] alpha/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target/alpha.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/alpha/cpu.h       | 4 ++--
 target/alpha/translate.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index be29bdd..8a6d477 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -190,7 +190,7 @@ enum {
 
    That said, we're only emulating Unix PALcode, and not attempting VMS,
    so we don't need to implement Executive and Supervisor.  QEMU's own
-   PALcode cheats and usees the KSEG mapping for its code+data rather than
+   PALcode cheats and uses the KSEG mapping for its code+data rather than
    physical addresses.  */
 
 #define MMU_KERNEL_IDX   0
@@ -370,7 +370,7 @@ enum {
    The Unix PALcode only uses bit 4.  */
 #define PS_USER_MODE  8u
 
-/* CPUAlphaState->flags constants.  These are layed out so that we
+/* CPUAlphaState->flags constants.  These are laid out so that we
    can set or reset the pieces individually by assigning to the byte,
    or manipulated as a whole.  */
 
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 8870284..6aef9ec 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2939,7 +2939,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
        the first fp insn of the TB.  Alternately we could define a proper
        default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
        to reset the FP_STATUS to that default at the end of any TB that
-       changes the default.  We could even (gasp) dynamiclly figure out
+       changes the default.  We could even (gasp) dynamically figure out
        what default would be most efficient given the running program.  */
     ctx->tb_rm = -1;
     /* Similarly for flush-to-zero.  */
-- 
2.26.2.windows.1

[PATCH RFC 14/14] target/: fix some comment spelling errors

[zhaolichang]

I found that there are many spelling errors in the comments of qemu/target.
I used spellcheck to check the spelling errors and found some errors in the folder.

Signed-off-by: zhaolichang <zhaolichang@huawei.com>
---
 target/openrisc/cpu.h        | 2 +-
 target/sparc/asi.h           | 2 +-
 target/unicore32/translate.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index bd42faf..8ca8605 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState {
     int is_counting;
 
     uint32_t picmr;         /* Interrupt mask register */
-    uint32_t picsr;         /* Interrupt contrl register*/
+    uint32_t picsr;         /* Interrupt control register*/
 #endif
     void *irq[32];          /* Interrupt irq input */
 } CPUOpenRISCState;
diff --git a/target/sparc/asi.h b/target/sparc/asi.h
index bb58735..4e9f1d5 100644
--- a/target/sparc/asi.h
+++ b/target/sparc/asi.h
@@ -231,7 +231,7 @@
 #define ASI_INTR_ID		0x63 /* (CMT) Interrupt ID register	*/
 #define ASI_CORE_ID		0x63 /* (CMT) LP ID register		*/
 #define ASI_CESR_ID		0x63 /* (CMT) CESR ID register		*/
-#define ASI_IC_INSTR		0x66 /* Insn cache instrucion ram diag	*/
+#define ASI_IC_INSTR		0x66 /* Insn cache instruction ram diag	*/
 #define ASI_IC_TAG		0x67 /* Insn cache tag/valid ram diag 	*/
 #define ASI_IC_STAG		0x68 /* (III) Insn cache snoop tag ram	*/
 #define ASI_IC_PRE_DECODE	0x6e /* Insn cache pre-decode ram diag	*/
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index d4b06df..2e91b05 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg)
 {
     if (reg == 31) {
         uint32_t addr;
-        /* normaly, since we updated PC */
+        /* normally, since we updated PC */
         addr = (long)s->pc;
         tcg_gen_movi_i32(var, addr);
     } else {
-- 
2.26.2.windows.1

Re: [PATCH RFC 06/14] mips/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/mips.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
> ---
>  target/mips/internal.h           |  2 +-
>  target/mips/translate.c          | 10 +++++-----
>  target/mips/translate_init.c.inc |  2 +-
>  3 files changed, 7 insertions(+), 7 deletions(-)

Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH RFC 09/14] sh4/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/sh4.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
> ---
>  target/sh4/cpu.h       | 2 +-
>  target/sh4/op_helper.c | 2 +-
>  target/sh4/translate.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH RFC 11/14] avr/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/avr.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
> ---
>  target/avr/helper.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH RFC 14/14] target/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/openrisc/cpu.h        | 2 +-
>  target/sparc/asi.h           | 2 +-
>  target/unicore32/translate.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index bd42faf..8ca8605 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState {
>      int is_counting;
>  
>      uint32_t picmr;         /* Interrupt mask register */
> -    uint32_t picsr;         /* Interrupt contrl register*/
> +    uint32_t picsr;         /* Interrupt control register*/
>  #endif
>      void *irq[32];          /* Interrupt irq input */
>  } CPUOpenRISCState;
> diff --git a/target/sparc/asi.h b/target/sparc/asi.h
> index bb58735..4e9f1d5 100644
> --- a/target/sparc/asi.h
> +++ b/target/sparc/asi.h
> @@ -231,7 +231,7 @@
>  #define ASI_INTR_ID		0x63 /* (CMT) Interrupt ID register	*/
>  #define ASI_CORE_ID		0x63 /* (CMT) LP ID register		*/
>  #define ASI_CESR_ID		0x63 /* (CMT) CESR ID register		*/
> -#define ASI_IC_INSTR		0x66 /* Insn cache instrucion ram diag	*/
> +#define ASI_IC_INSTR		0x66 /* Insn cache instruction ram diag	*/
>  #define ASI_IC_TAG		0x67 /* Insn cache tag/valid ram diag 	*/
>  #define ASI_IC_STAG		0x68 /* (III) Insn cache snoop tag ram	*/
>  #define ASI_IC_PRE_DECODE	0x6e /* Insn cache pre-decode ram diag	*/
> diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
> index d4b06df..2e91b05 100644
> --- a/target/unicore32/translate.c
> +++ b/target/unicore32/translate.c
> @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg)
>  {
>      if (reg == 31) {
>          uint32_t addr;
> -        /* normaly, since we updated PC */
> +        /* normally, since we updated PC */
>          addr = (long)s->pc;
>          tcg_gen_movi_i32(var, addr);
>      } else {
> 

Re: [PATCH RFC 04/14] rx/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/rx.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/rx/op_helper.c | 2 +-
>  target/rx/translate.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
> index f89d294..59389f4 100644
> --- a/target/rx/op_helper.c
> +++ b/target/rx/op_helper.c
> @@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
>      env->psw_c = (tmp <= env->regs[2]);
>  }
>  
> -/* accumlator operations */
> +/* accumulator operations */
>  void helper_rmpa(CPURXState *env, uint32_t sz)
>  {
>      uint64_t result_l, prev;
> diff --git a/target/rx/translate.c b/target/rx/translate.c
> index 482278e..9ea941c 100644
> --- a/target/rx/translate.c
> +++ b/target/rx/translate.c
> @@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
>      tcg_gen_xor_i32(temp, arg1, arg2);
>      tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
>      tcg_temp_free_i32(temp);
> -    /* CMP not requred return */
> +    /* CMP not required return */
>      if (ret) {
>          tcg_gen_mov_i32(ret, cpu_psw_s);
>      }
> 

Re: [PATCH RFC 08/14] m68k/: fix some comment spelling errors

[Laurent Vivier]

Le 30/09/2020 à 11:53, zhaolichang a écrit :
> I found that there are many spelling errors in the comments of qemu/target/m68k.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
> ---
>  target/m68k/translate.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index 3fc67aa..133a404 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -438,7 +438,7 @@ static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
>  }
>  
>  /*
> - * Handle a base + index + displacement effective addresss.
> + * Handle a base + index + displacement effective address.
>   * A NULL_QREG base means pc-relative.
>   */
>  static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
> @@ -1696,7 +1696,7 @@ static void bcd_add(TCGv dest, TCGv src)
>  
>      /*
>       * t1 = (src + 0x066) + dest + X
> -     *    = result with some possible exceding 0x6
> +     *    = result with some possible exceeding 0x6
>       */
>  
>      t0 = tcg_const_i32(0x066);
> @@ -1706,7 +1706,7 @@ static void bcd_add(TCGv dest, TCGv src)
>      tcg_gen_add_i32(t1, t0, dest);
>      tcg_gen_add_i32(t1, t1, QREG_CC_X);
>  
> -    /* we will remove exceding 0x6 where there is no carry */
> +    /* we will remove exceeding 0x6 where there is no carry */
>  
>      /*
>       * t0 = (src + 0x0066) ^ dest
> @@ -1736,7 +1736,7 @@ static void bcd_add(TCGv dest, TCGv src)
>      tcg_temp_free(t0);
>  
>      /*
> -     * remove the exceding 0x6
> +     * remove the exceeding 0x6
>       * for digits that have not generated a carry
>       */
>  
> @@ -2638,7 +2638,7 @@ DISAS_INSN(negx)
>      gen_flush_flags(s); /* compute old Z */
>  
>      /*
> -     * Perform substract with borrow.
> +     * Perform subtract with borrow.
>       * (X, N) =  -(src + X);
>       */
>  
> @@ -2653,7 +2653,7 @@ DISAS_INSN(negx)
>      /*
>       * Compute signed-overflow for negation.  The normal formula for
>       * subtraction is (res ^ src) & (src ^ dest), but with dest==0
> -     * this simplies to res & src.
> +     * this simplifies to res & src.
>       */
>  
>      tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
> @@ -3159,7 +3159,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
>      gen_flush_flags(s); /* compute old Z */
>  
>      /*
> -     * Perform substract with borrow.
> +     * Perform subtract with borrow.
>       * (X, N) = dest - (src + X);
>       */
>  
> @@ -3169,7 +3169,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
>      gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
>      tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
>  
> -    /* Compute signed-overflow for substract.  */
> +    /* Compute signed-overflow for subtract.  */
>  
>      tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
>      tcg_gen_xor_i32(tmp, dest, src);
> 

Reviewed-by: Laurent Vivier <laurent@vivier>

Re: [PATCH RFC 06/14] mips/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On Wed, Sep 30, 2020 at 12:23 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 9/30/20 11:53 AM, zhaolichang wrote:
> > I found that there are many spelling errors in the comments of qemu/target/mips.
> > I used spellcheck to check the spelling errors and found some errors in the folder.
> >
> > Signed-off-by: zhaolichang <zhaolichang@huawei.com>
> > ---
> >  target/mips/internal.h           |  2 +-
> >  target/mips/translate.c          | 10 +++++-----
> >  target/mips/translate_init.c.inc |  2 +-
> >  3 files changed, 7 insertions(+), 7 deletions(-)
>
> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Err:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH RFC 00/14] fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> The checkpatch.pl file in the Linux kernel can check spelling errors in patches.
> I'm trying to add this function to the checkpatch.pl in qemu,
> so that no similar spelling errors will occur in the feture.
> It's not done yet and I will commit the patch when it's done.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

BTW your git-config is still messy, maybe you missed my previous
comment:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg741642.html

Re: [PATCH RFC 01/14] cris/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:08 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/cris.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

With the correction below...

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/cris/helper.c    |  6 +++---
>  target/cris/op_helper.c |  2 +-
>  target/cris/translate.c | 14 +++++++-------
>  3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/target/cris/helper.c b/target/cris/helper.c
> index b5159b8..50419e7 100644
> --- a/target/cris/helper.c
> +++ b/target/cris/helper.c
> @@ -141,7 +141,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
>      assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
>      switch (cs->exception_index) {
>      case EXCP_BREAK:
> -        /* These exceptions are genereated by the core itself.
> +        /* These exceptions are generated by the core itself.
>             ERP should point to the insn following the brk.  */
>          ex_vec = env->trap_vector;
>          env->pregs[PRV10_BRP] = env->pc;
> @@ -197,7 +197,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
>  
>      switch (cs->exception_index) {
>      case EXCP_BREAK:
> -        /* These exceptions are genereated by the core itself.
> +        /* These exceptions are generated by the core itself.
>             ERP should point to the insn following the brk.  */
>          ex_vec = env->trap_vector;
>          env->pregs[PR_ERP] = env->pc;
> @@ -256,7 +256,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
>         undefined.  */
>      env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
>  
> -    /* Clear the excption_index to avoid spurios hw_aborts for recursive
> +    /* Clear the excption_index to avoid spurious hw_aborts for recursive

"exception_index"

>         bus faults.  */
>      cs->exception_index = -1;
>  
> diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
> index 6b1e7ae..3c4aacc 100644
> --- a/target/cris/op_helper.c
> +++ b/target/cris/op_helper.c
> @@ -231,7 +231,7 @@ static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
>  {
>      unsigned int x, z, mask;
>  
> -    /* Extended arithmetics, leave the z flag alone.  */
> +    /* Extended arithmetic, leave the z flag alone.  */
>      x = env->cc_x;
>      mask = env->cc_mask | X_FLAG;
>      if (x) {
> diff --git a/target/cris/translate.c b/target/cris/translate.c
> index c312e6f..16b0ef8 100644
> --- a/target/cris/translate.c
> +++ b/target/cris/translate.c
> @@ -348,7 +348,7 @@ static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
>      tcg_temp_free(t);
>  }
>  
> -/* Extended arithmetics on CRIS.  */
> +/* Extended arithmetic on CRIS.  */
>  static inline void t_gen_add_flag(TCGv d, int flag)
>  {
>      TCGv c;
> @@ -725,7 +725,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
>      switch (op) {
>      case CC_OP_ADD:
>          tcg_gen_add_tl(dst, a, b);
> -        /* Extended arithmetics.  */
> +        /* Extended arithmetic.  */
>          t_gen_addx_carry(dc, dst);
>          break;
>      case CC_OP_ADDC:
> @@ -738,7 +738,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
>          break;
>      case CC_OP_SUB:
>          tcg_gen_sub_tl(dst, a, b);
> -        /* Extended arithmetics.  */
> +        /* Extended arithmetic.  */
>          t_gen_subx_carry(dc, dst);
>          break;
>      case CC_OP_MOVE:
> @@ -764,7 +764,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
>          break;
>      case CC_OP_NEG:
>          tcg_gen_neg_tl(dst, b);
> -        /* Extended arithmetics.  */
> +        /* Extended arithmetic.  */
>          t_gen_subx_carry(dc, dst);
>          break;
>      case CC_OP_LZ:
> @@ -787,7 +787,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op,
>          break;
>      case CC_OP_CMP:
>          tcg_gen_sub_tl(dst, a, b);
> -        /* Extended arithmetics.  */
> +        /* Extended arithmetic.  */
>          t_gen_subx_carry(dc, dst);
>          break;
>      default:
> @@ -3053,12 +3053,12 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
>   * On QEMU care needs to be taken when a branch+delayslot sequence is broken
>   * and the branch and delayslot don't share pages.
>   *
> - * The TB contaning the branch insn will set up env->btarget and evaluate 
> + * The TB containing the branch insn will set up env->btarget and evaluate 
>   * env->btaken. When the translation loop exits we will note that the branch 
>   * sequence is broken and let env->dslot be the size of the branch insn (those
>   * vary in length).
>   *
> - * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
> + * The TB containing the delayslot will have the PC of its real insn (i.e no lsb
>   * set). It will also expect to have env->dslot setup with the size of the 
>   * delay slot so that env->pc - env->dslot point to the branch insn. This TB 
>   * will execute the dslot and take the branch, either to btarget or just one 
> -- 
> 2.26.2.windows.1

dme.
-- 
Driving at 90 down those country lanes, singing to "Tiny Dancer".

Re: [PATCH RFC 02/14] ppc/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:09 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/ppc.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/ppc/cpu.h                | 6 +++---
>  target/ppc/excp_helper.c        | 6 +++---
>  target/ppc/fpu_helper.c         | 2 +-
>  target/ppc/internal.h           | 2 +-
>  target/ppc/kvm.c                | 2 +-
>  target/ppc/machine.c            | 2 +-
>  target/ppc/mmu-hash64.c         | 2 +-
>  target/ppc/mmu_helper.c         | 4 ++--
>  target/ppc/translate_init.c.inc | 2 +-
>  9 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 766e9c5..ba5ebb1 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -615,7 +615,7 @@ enum {
>  #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
>  #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
>  #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
> -#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
> +#define FPSCR_UE     5  /* Floating-point underflow exception enable          */
>  #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
>  #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
>  #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
> @@ -2331,13 +2331,13 @@ enum {
>      /* Internal hardware exception sources */
>      PPC_INTERRUPT_DECR,           /* Decrementer exception                */
>      PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
> -    PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
> +    PPC_INTERRUPT_PIT,            /* Programmable interval timer interrupt */
>      PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
>      PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
>      PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
>      PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
>      PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
> -    PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
> +    PPC_INTERRUPT_HMI,            /* Hypervisor Maintenance interrupt    */
>      PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
>      PPC_INTERRUPT_HVIRT,          /* Hypervisor virtualization interrupt  */
>  };
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index a988ba1..d7411bc 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -231,7 +231,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
>      }
>  
>      /*
> -     * Exception targetting modifiers
> +     * Exception targeting modifiers
>       *
>       * LPES0 is supported on POWER7/8/9
>       * LPES1 is not supported (old iSeries mode)
> @@ -1015,7 +1015,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
>           * This means we will incorrectly execute past the power management
>           * instruction instead of triggering a reset.
>           *
> -         * It generally means a discrepancy between the wakup conditions in the
> +         * It generally means a discrepancy between the wakeup conditions in the
>           * processor has_work implementation and the logic in this function.
>           */
>          cpu_abort(env_cpu(env),
> @@ -1191,7 +1191,7 @@ void helper_rfi(CPUPPCState *env)
>  void helper_rfid(CPUPPCState *env)
>  {
>      /*
> -     * The architeture defines a number of rules for which bits can
> +     * The architecture defines a number of rules for which bits can
>       * change but in practice, we handle this in hreg_store_msr()
>       * which will be called by do_rfi(), so there is no need to filter
>       * here
> diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
> index ae43b08..9b8c8b7 100644
> --- a/target/ppc/fpu_helper.c
> +++ b/target/ppc/fpu_helper.c
> @@ -1804,7 +1804,7 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
>  
>  
>  /*
> - * VSX_ADD_SUB - VSX floating point add/subract
> + * VSX_ADD_SUB - VSX floating point add/subtract
>   *   name  - instruction mnemonic
>   *   op    - operation (add or sub)
>   *   nels  - number of elements (1, 2 or 4)
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index 15d655b..b4df127 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -1,5 +1,5 @@
>  /*
> - *  PowerPC interal definitions for qemu.
> + *  PowerPC internal definitions for qemu.
>   *
>   * This library is free software; you can redistribute it and/or
>   * modify it under the terms of the GNU Lesser General Public
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index d85ba8f..e85ef2e 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -487,7 +487,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
>              /*
>               * KVM-HV has transactional memory on POWER8 also without
>               * the KVM_CAP_PPC_HTM extension, so enable it here
> -             * instead as long as it's availble to userspace on the
> +             * instead as long as it's available to userspace on the
>               * host.
>               */
>              if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index 109d071..f6a24a9 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -337,7 +337,7 @@ static int cpu_post_load(void *opaque, int version_id)
>  
>      /*
>       * If we're operating in compat mode, we should be ok as long as
> -     * the destination supports the same compatiblity mode.
> +     * the destination supports the same compatibility mode.
>       *
>       * Otherwise, however, we require that the destination has exactly
>       * the same CPU model as the source.
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index c31d21e..977b2d1 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -883,7 +883,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
>      /*
>       * Note on LPCR usage: 970 uses HID4, but our special variant of
>       * store_spr copies relevant fields into env->spr[SPR_LPCR].
> -     * Similarily we filter unimplemented bits when storing into LPCR
> +     * Similarly we filter unimplemented bits when storing into LPCR
>       * depending on the MMU version. This code can thus just use the
>       * LPCR "as-is".
>       */
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 8972714..50aa18a 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -179,7 +179,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
>              }
>              /* Compute access rights */
>              access = pp_check(ctx->key, pp, ctx->nx);
> -            /* Keep the matching PTE informations */
> +            /* Keep the matching PTE information */
>              ctx->raddr = pte1;
>              ctx->prot = access;
>              ret = check_prot(ctx->prot, rw, type);
> @@ -2176,7 +2176,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
>          env->sr[srnum] = value;
>          /*
>           * Invalidating 256MB of virtual memory in 4kB pages is way
> -         * longer than flusing the whole TLB.
> +         * longer than flushing the whole TLB.
>           */
>  #if !defined(FLUSH_ALL_TLBS) && 0
>          {
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index bb66526..3e0810f 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -792,7 +792,7 @@ static void gen_spr_generic(CPUPPCState *env)
>                   &spr_read_xer, &spr_write_xer,
>                   &spr_read_xer, &spr_write_xer,
>                   0x00000000);
> -    /* Branch contol */
> +    /* Branch control */
>      spr_register(env, SPR_LR, "LR",
>                   &spr_read_lr, &spr_write_lr,
>                   &spr_read_lr, &spr_write_lr,
> -- 
> 2.26.2.windows.1

dme.
-- 
You took the words right out of my mouth.

Re: [PATCH RFC 03/14] riscv/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:10 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/riscv.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/riscv/cpu.c           | 2 +-
>  target/riscv/cpu_bits.h      | 2 +-
>  target/riscv/csr.c           | 6 +++---
>  target/riscv/vector_helper.c | 2 +-
>  4 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f..f40a0b2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>                      return;
>                  }
>              } else {
> -                qemu_log("vector verison is not specified, "
> +                qemu_log("vector version is not specified, "
>                          "use the default value v0.7.1\n");
>              }
>              set_vext_version(env, vext_version);
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index bd36062..6e11555 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -536,7 +536,7 @@
>  /* Leaf page shift amount */
>  #define PGSHIFT             12
>  
> -/* Default Reset Vector adress */
> +/* Default Reset Vector address */
>  #define DEFAULT_RSTVEC      0x1000
>  
>  /* Exception causes */
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 26ae347..559db11 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
>      return 0;
>  }
>  
> -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
> +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>      if (env->priv_ver < PRIV_VERSION_1_11_0) {
> @@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
>      return 0;
>  }
>  
> -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
> +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
>  {
>      if (env->priv_ver < PRIV_VERSION_1_11_0) {
> @@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>          !riscv_cpu_virt_enabled(env)) {
>          /*
>           * We are in S mode without virtualisation, therefore we are in HS Mode.
> -         * Add 1 to the effective privledge level to allow us to access the
> +         * Add 1 to the effective privilege level to allow us to access the
>           * Hypervisor CSRs.
>           */
>          effective_priv++;
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index a156573..fa89a6e 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
>                                    uint32_t wd, uint32_t idx, CPURISCVState *env,
>                                    uintptr_t retaddr);
>  
> -/* no atomic opreation for vector atomic insructions */
> +/* no atomic operation for vector atomic insructions */
>  #define DO_SWAP(N, M) (M)
>  #define DO_AND(N, M)  (N & M)
>  #define DO_XOR(N, M)  (N ^ M)
> -- 
> 2.26.2.windows.1

dme.
-- 
But are you safe Miss Gradenko?

Re: [PATCH RFC 04/14] rx/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:11 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/rx.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/rx/op_helper.c | 2 +-
>  target/rx/translate.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
> index f89d294..59389f4 100644
> --- a/target/rx/op_helper.c
> +++ b/target/rx/op_helper.c
> @@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
>      env->psw_c = (tmp <= env->regs[2]);
>  }
>  
> -/* accumlator operations */
> +/* accumulator operations */
>  void helper_rmpa(CPURXState *env, uint32_t sz)
>  {
>      uint64_t result_l, prev;
> diff --git a/target/rx/translate.c b/target/rx/translate.c
> index 482278e..9ea941c 100644
> --- a/target/rx/translate.c
> +++ b/target/rx/translate.c
> @@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
>      tcg_gen_xor_i32(temp, arg1, arg2);
>      tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
>      tcg_temp_free_i32(temp);
> -    /* CMP not requred return */
> +    /* CMP not required return */
>      if (ret) {
>          tcg_gen_mov_i32(ret, cpu_psw_s);
>      }
> -- 
> 2.26.2.windows.1

dme.
-- 
I'd rather be with you than flying through space.

Re: [PATCH RFC 05/14] tricore/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:12 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/tricore.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/s390x/ioinst.c      | 2 +-
>  target/tricore/csfr.def    | 2 +-
>  target/tricore/translate.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c
> index a412926..c576d85 100644
> --- a/target/s390x/ioinst.c
> +++ b/target/s390x/ioinst.c
> @@ -279,7 +279,7 @@ void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
>          /*
>           * As operand exceptions have a lower priority than access exceptions,
>           * we check whether the memory area is writeable (injecting the
> -         * access execption if it is not) first.
> +         * access exception if it is not) first.
>           */
>          if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) {
>              s390_program_interrupt(env, PGM_OPERAND, ra);
> diff --git a/target/tricore/csfr.def b/target/tricore/csfr.def
> index ff004cb..cdfaf1d 100644
> --- a/target/tricore/csfr.def
> +++ b/target/tricore/csfr.def
> @@ -1,4 +1,4 @@
> -/* A(ll) access permited
> +/* A(ll) access permitted
>     R(ead only) access
>     E(nd init protected) access
>  
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index 7752630..c9c420d 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -397,7 +397,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
>  #undef E
>  
>  #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
> -                                    since no execption occurs */
> +                                    since no exception occurs */
>  #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)                \
>      case ADDRESS:                                                        \
>          if (has_feature(ctx, FEATURE)) {                             \
> -- 
> 2.26.2.windows.1

dme.
-- 
If I could buy my reasoning, I'd pay to lose.

Re: [PATCH RFC 06/14] mips/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:13 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/mips.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/mips/internal.h           |  2 +-
>  target/mips/translate.c          | 10 +++++-----
>  target/mips/translate_init.c.inc |  2 +-
>  3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target/mips/internal.h b/target/mips/internal.h
> index 7f159a9..b811f54 100644
> --- a/target/mips/internal.h
> +++ b/target/mips/internal.h
> @@ -188,7 +188,7 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
>          /*
>           * A MIPS configured with a vectorizing external interrupt controller
>           * will feed a vector into the Cause pending lines. The core treats
> -         * the status lines as a vector level, not as indiviual masks.
> +         * the status lines as a vector level, not as individual masks.
>           */
>          r = pending > status;
>      } else {
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 398edf7..b4d0090 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -3718,7 +3718,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
>  
>      t0 = tcg_temp_new();
>      addr = tcg_temp_new();
> -    /* compare the address against that of the preceeding LL */
> +    /* compare the address against that of the preceding LL */
>      gen_base_offset_addr(ctx, addr, base, offset);
>      tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
>      tcg_temp_free(addr);
> @@ -25597,7 +25597,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
>          }
>          /* return resulting half-words to its original position */
>          tcg_gen_shri_i32(t0, t0, 16);
> -        /* finaly update the destination */
> +        /* finally update the destination */
>          tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
>  
>          tcg_temp_free(t1);
> @@ -25633,7 +25633,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
>          }
>          /* return resulting half-words to its original position */
>          tcg_gen_shri_i32(t0, t0, 16);
> -        /* finaly update the destination */
> +        /* finally update the destination */
>          tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
>  
>          tcg_temp_free(t1);
> @@ -25702,7 +25702,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
>              }
>              /* return resulting byte to its original position */
>              tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
> -            /* finaly update the destination */
> +            /* finally update the destination */
>              tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
>          }
>  
> @@ -25742,7 +25742,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
>              }
>              /* return resulting byte to its original position */
>              tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
> -            /* finaly update the destination */
> +            /* finally update the destination */
>              tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
>          }
>  
> diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
> index 637cacc..c735b2b 100644
> --- a/target/mips/translate_init.c.inc
> +++ b/target/mips/translate_init.c.inc
> @@ -995,7 +995,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
>  
>      /* MVPConf1 implemented, TLB sharable, no gating storage support,
>         programmable cache partitioning implemented, number of allocatable
> -       and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
> +       and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
>         implemented, 5 TCs implemented. */
>      env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
>                               (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
> -- 
> 2.26.2.windows.1

dme.
-- 
There in the midst of it so alive and alone, words support like bone.

Re: [PATCH RFC 07/14] s390x/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:14 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/s390x.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/s390x/cpu_models.h       | 4 ++--
>  target/s390x/excp_helper.c      | 2 +-
>  target/s390x/fpu_helper.c       | 2 +-
>  target/s390x/insn-data.def      | 2 +-
>  target/s390x/misc_helper.c      | 2 +-
>  target/s390x/translate.c        | 4 ++--
>  target/s390x/translate_vx.c.inc | 2 +-
>  7 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h
> index 74d1f87..15c0f0d 100644
> --- a/target/s390x/cpu_models.h
> +++ b/target/s390x/cpu_models.h
> @@ -24,13 +24,13 @@ struct S390CPUDef {
>      uint8_t gen;            /* hw generation identification */
>      uint16_t type;          /* cpu type identification */
>      uint8_t ec_ga;          /* EC GA version (on which also the BC is based) */
> -    uint8_t mha_pow;        /* Maximum Host Adress Power, mha = 2^pow-1 */
> +    uint8_t mha_pow;        /* Maximum Host Address Power, mha = 2^pow-1 */
>      uint32_t hmfai;         /* hypervisor-managed facilities */
>      /* base/min features, must never be changed between QEMU versions */
>      S390FeatBitmap base_feat;
>      /* used to init base_feat from generated data */
>      S390FeatInit base_init;
> -    /* deafault features, QEMU version specific */
> +    /* default features, QEMU version specific */
>      S390FeatBitmap default_feat;
>      /* used to init default_feat from generated data */
>      S390FeatInit default_init;
> diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
> index 3b58d10..9644a67 100644
> --- a/target/s390x/excp_helper.c
> +++ b/target/s390x/excp_helper.c
> @@ -538,7 +538,7 @@ try_deliver:
>          /* don't trigger a cpu_loop_exit(), use an interrupt instead */
>          cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HALT);
>      } else if (cs->halted) {
> -        /* unhalt if we had a WAIT PSW somehwere in our injection chain */
> +        /* unhalt if we had a WAIT PSW somewhere in our injection chain */
>          s390_cpu_unhalt(cpu);
>      }
>  }
> diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c
> index f155bc0..3e609b7 100644
> --- a/target/s390x/fpu_helper.c
> +++ b/target/s390x/fpu_helper.c
> @@ -89,7 +89,7 @@ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr)
>      /*
>       * invalid/divbyzero cannot coexist with other conditions.
>       * overflow/underflow however can coexist with inexact, we have to
> -     * handle it separatly.
> +     * handle it separately.
>       */
>      if (s390_exc & ~S390_IEEE_MASK_INEXACT) {
>          if (s390_exc & ~S390_IEEE_MASK_INEXACT & env->fpc >> 24) {
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index d79ae9e..1631948 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -523,7 +523,7 @@
>  /* LOAD LOGICAL HALFWORD RELATIVE LONG */
>      C(0xc402, LLHRL,   RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0)
>      C(0xc406, LLGHRL,  RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0)
> -/* LOAD LOGICAL IMMEDATE */
> +/* LOAD LOGICAL IMMEDIATE */
>      D(0xc00e, LLIHF,   RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32)
>      D(0xc00f, LLILF,   RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0)
>      D(0xa50c, LLIHH,   RI_a,  Z,  0, i2_16u_shl, 0, r1, mov2, 0, 48)
> diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
> index 58dbc02..929e509 100644
> --- a/target/s390x/misc_helper.c
> +++ b/target/s390x/misc_helper.c
> @@ -312,7 +312,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1)
>              /* same as machine type number in STORE CPU ID, but in EBCDIC */
>              snprintf(type, ARRAY_SIZE(type), "%X", cpu->model->def->type);
>              ebcdic_put(sysib.sysib_111.type, type, 4);
> -            /* model number (not stored in STORE CPU ID for z/Architecure) */
> +            /* model number (not stored in STORE CPU ID for z/Architecture) */
>              ebcdic_put(sysib.sysib_111.model, "QEMU            ", 16);
>              ebcdic_put(sysib.sysib_111.sequence, "QEMU            ", 16);
>              ebcdic_put(sysib.sysib_111.plant, "QEMU", 4);
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index a777343..58ad6c8 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -433,7 +433,7 @@ static void gen_program_exception(DisasContext *s, int code)
>  {
>      TCGv_i32 tmp;
>  
> -    /* Remember what pgm exeption this was.  */
> +    /* Remember what pgm exception this was.  */
>      tmp = tcg_const_i32(code);
>      tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
>      tcg_temp_free_i32(tmp);
> @@ -489,7 +489,7 @@ static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
>  
>      /*
>       * Note that d2 is limited to 20 bits, signed.  If we crop negative
> -     * displacements early we create larger immedate addends.
> +     * displacements early we create larger immediate addends.
>       */
>      if (b2 && x2) {
>          tcg_gen_add_i64(tmp, regs[b2], regs[x2]);
> diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
> index eb767f5..983da56 100644
> --- a/target/s390x/translate_vx.c.inc
> +++ b/target/s390x/translate_vx.c.inc
> @@ -789,7 +789,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
>          }
>          break;
>      case 0x94:
> -        /* If sources and destination dont't overlap -> fast path */
> +        /* If sources and destination don't overlap -> fast path */
>          if (v1 != v2 && v1 != v3) {
>              const uint8_t src_es = get_field(s, m4);
>              const uint8_t dst_es = src_es - 1;
> -- 
> 2.26.2.windows.1

dme.
-- 
Do I have to tell the story, of a thousand rainy days since we first met?

Re: [PATCH RFC 08/14] m68k/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:15 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/m68k.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/m68k/translate.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index 3fc67aa..133a404 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -438,7 +438,7 @@ static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
>  }
>  
>  /*
> - * Handle a base + index + displacement effective addresss.
> + * Handle a base + index + displacement effective address.
>   * A NULL_QREG base means pc-relative.
>   */
>  static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
> @@ -1696,7 +1696,7 @@ static void bcd_add(TCGv dest, TCGv src)
>  
>      /*
>       * t1 = (src + 0x066) + dest + X
> -     *    = result with some possible exceding 0x6
> +     *    = result with some possible exceeding 0x6
>       */
>  
>      t0 = tcg_const_i32(0x066);
> @@ -1706,7 +1706,7 @@ static void bcd_add(TCGv dest, TCGv src)
>      tcg_gen_add_i32(t1, t0, dest);
>      tcg_gen_add_i32(t1, t1, QREG_CC_X);
>  
> -    /* we will remove exceding 0x6 where there is no carry */
> +    /* we will remove exceeding 0x6 where there is no carry */
>  
>      /*
>       * t0 = (src + 0x0066) ^ dest
> @@ -1736,7 +1736,7 @@ static void bcd_add(TCGv dest, TCGv src)
>      tcg_temp_free(t0);
>  
>      /*
> -     * remove the exceding 0x6
> +     * remove the exceeding 0x6
>       * for digits that have not generated a carry
>       */
>  
> @@ -2638,7 +2638,7 @@ DISAS_INSN(negx)
>      gen_flush_flags(s); /* compute old Z */
>  
>      /*
> -     * Perform substract with borrow.
> +     * Perform subtract with borrow.
>       * (X, N) =  -(src + X);
>       */
>  
> @@ -2653,7 +2653,7 @@ DISAS_INSN(negx)
>      /*
>       * Compute signed-overflow for negation.  The normal formula for
>       * subtraction is (res ^ src) & (src ^ dest), but with dest==0
> -     * this simplies to res & src.
> +     * this simplifies to res & src.
>       */
>  
>      tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
> @@ -3159,7 +3159,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
>      gen_flush_flags(s); /* compute old Z */
>  
>      /*
> -     * Perform substract with borrow.
> +     * Perform subtract with borrow.
>       * (X, N) = dest - (src + X);
>       */
>  
> @@ -3169,7 +3169,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
>      gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
>      tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
>  
> -    /* Compute signed-overflow for substract.  */
> +    /* Compute signed-overflow for subtract.  */
>  
>      tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
>      tcg_gen_xor_i32(tmp, dest, src);
> -- 
> 2.26.2.windows.1

dme.
-- 
Don't you know you're never going to get to France.

Re: [PATCH RFC 09/14] sh4/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:16 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/sh4.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/sh4/cpu.h       | 2 +-
>  target/sh4/op_helper.c | 2 +-
>  target/sh4/translate.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index dbe58c7..91fa949 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -160,7 +160,7 @@ typedef struct CPUSH4State {
>      uint32_t pteh;		/* page table entry high register */
>      uint32_t ptel;		/* page table entry low register */
>      uint32_t ptea;		/* page table entry assistance register */
> -    uint32_t ttb;		/* tranlation table base register */
> +    uint32_t ttb;		/* translation table base register */
>      uint32_t tea;		/* TLB exception address register */
>      uint32_t tra;		/* TRAPA exception register */
>      uint32_t expevt;		/* exception event register */
> diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
> index 14c3db0..9de4152 100644
> --- a/target/sh4/op_helper.c
> +++ b/target/sh4/op_helper.c
> @@ -400,7 +400,7 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
>      t0 = float32_div(float32_one, t0, &env->fp_status);
>      /* Since this is supposed to be an approximation, an imprecision
>         exception is required.  One supposes this also follows the usual
> -       IEEE rule that other exceptions take precidence.  */
> +       IEEE rule that other exceptions take precedence.  */
>      if (get_float_exception_flags(&env->fp_status) == 0) {
>          set_float_exception_flags(float_flag_inexact, &env->fp_status);
>      }
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index 60c863d..c57218e 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -1959,7 +1959,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
>      NEXT_INSN;
>      switch (ctx->opcode & 0xf00f) {
>      case 0x6003: /* mov Rm,Rn */
> -        /* Here we want to recognize ld_dst being saved for later consumtion,
> +        /* Here we want to recognize ld_dst being saved for later consumption,
>             or for another input register being copied so that ld_dst need not
>             be clobbered during the operation.  */
>          op_dst = B11_8;
> -- 
> 2.26.2.windows.1

dme.
-- 
Music has magic, it's good clear syncopation.

Re: [PATCH RFC 10/14] i386/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:17 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/i386.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/i386/cpu.c           | 4 ++--
>  target/i386/hax-interface.h | 4 ++--
>  target/i386/hax-windows.c   | 2 +-
>  target/i386/kvm.c           | 2 +-
>  target/i386/machine.c       | 6 +++---
>  target/i386/translate.c     | 8 ++++----
>  target/i386/whpx-all.c      | 2 +-
>  7 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 3ffd877..23851e5 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -4677,7 +4677,7 @@ static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
>      return name;
>  }
>  
> -/* Compatibily hack to maintain legacy +-feat semantic,
> +/* Compatibility hack to maintain legacy +-feat semantic,
>   * where +-feat overwrites any feature set by
>   * feat=on|feat even if the later is parsed after +-feat
>   * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
> @@ -6896,7 +6896,7 @@ static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
>      GuestPanicInformation *panic_info;
>  
>      if (!cs->crash_occurred) {
> -        error_setg(errp, "No crash occured");
> +        error_setg(errp, "No crash occurred");
>          return;
>      }
>  
> diff --git a/target/i386/hax-interface.h b/target/i386/hax-interface.h
> index 537ae08..edef4fd 100644
> --- a/target/i386/hax-interface.h
> +++ b/target/i386/hax-interface.h
> @@ -238,7 +238,7 @@ enum exit_status {
>      HAX_EXIT_UNKNOWN_VMEXIT,
>      /* HALT from guest */
>      HAX_EXIT_HLT,
> -    /* Reboot request, like because of tripple fault in guest */
> +    /* Reboot request, like because of triple fault in guest */
>      HAX_EXIT_STATECHANGE,
>      /* the vcpu is now only paused when destroy, so simply return to hax */
>      HAX_EXIT_PAUSED,
> @@ -295,7 +295,7 @@ struct hax_qemu_version {
>      uint32_t min_version;
>  } __attribute__ ((__packed__));
>  
> -/* The mac specfic interface to qemu, mostly is ioctl related */
> +/* The mac specific interface to qemu, mostly is ioctl related */
>  struct hax_tunnel_info {
>      uint64_t va;
>      uint64_t io_va;
> diff --git a/target/i386/hax-windows.c b/target/i386/hax-windows.c
> index 863c2bc..881089b 100644
> --- a/target/i386/hax-windows.c
> +++ b/target/i386/hax-windows.c
> @@ -174,7 +174,7 @@ int hax_mod_version(struct hax_state *hax, struct hax_module_version *version)
>      if (!ret) {
>          err = GetLastError();
>          if (err == ERROR_INSUFFICIENT_BUFFER || err == ERROR_MORE_DATA) {
> -            fprintf(stderr, "hax module verion is too long to hold.\n");
> +            fprintf(stderr, "hax module version is too long to hold.\n");
>          }
>          fprintf(stderr, "Failed to get Hax module version:%lu\n", err);
>          return -EFAULT;
> diff --git a/target/i386/kvm.c b/target/i386/kvm.c
> index 9efb07e..fbdbb49 100644
> --- a/target/i386/kvm.c
> +++ b/target/i386/kvm.c
> @@ -1179,7 +1179,7 @@ static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
>  /*
>   * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
>   * case of success, errno < 0 in case of failure and 0 when no Hyper-V
> - * extentions are enabled.
> + * extensions are enabled.
>   */
>  static int hyperv_handle_properties(CPUState *cs,
>                                      struct kvm_cpuid_entry2 *cpuid_ent)
> diff --git a/target/i386/machine.c b/target/i386/machine.c
> index b1acf7d..90e6139 100644
> --- a/target/i386/machine.c
> +++ b/target/i386/machine.c
> @@ -264,12 +264,12 @@ static int cpu_pre_save(void *opaque)
>       * hypervisor, its exception payload (CR2/DR6 on #PF/#DB)
>       * should not be set yet in the respective vCPU register.
>       * Thus, in case an exception is pending, it is
> -     * important to save the exception payload seperately.
> +     * important to save the exception payload separately.
>       *
>       * Therefore, if an exception is not in a pending state
>       * or vCPU is not in guest-mode, it is not important to
>       * distinguish between a pending and injected exception
> -     * and we don't need to store seperately the exception payload.
> +     * and we don't need to store separately the exception payload.
>       *
>       * In order to preserve better backwards-compatible migration,
>       * convert a pending exception to an injected exception in
> @@ -1138,7 +1138,7 @@ static int nested_state_post_load(void *opaque, int version_id)
>          return -EINVAL;
>      }
>      if (nested_state->size > max_nested_state_len) {
> -        error_report("Recieved unsupported nested state size: "
> +        error_report("Received unsupported nested state size: "
>                       "nested_state->size=%d, max=%d",
>                       nested_state->size, max_nested_state_len);
>          return -EINVAL;
> diff --git a/target/i386/translate.c b/target/i386/translate.c
> index caea6f5..5cdfe0e 100644
> --- a/target/i386/translate.c
> +++ b/target/i386/translate.c
> @@ -893,7 +893,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
>  }
>  
>  /* perform a conditional store into register 'reg' according to jump opcode
> -   value 'b'. In the fast case, T0 is guaranted not to be used. */
> +   value 'b'. In the fast case, T0 is guaranteed not to be used. */
>  static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
>  {
>      int inv, jcc_op, cond;
> @@ -1026,7 +1026,7 @@ static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg)
>  }
>  
>  /* generate a conditional jump to label 'l1' according to jump opcode
> -   value 'b'. In the fast case, T0 is guaranted not to be used. */
> +   value 'b'. In the fast case, T0 is guaranteed not to be used. */
>  static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1)
>  {
>      CCPrepare cc = gen_prepare_cc(s, b, s->T0);
> @@ -1043,7 +1043,7 @@ static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1)
>  }
>  
>  /* Generate a conditional jump to label 'l1' according to jump opcode
> -   value 'b'. In the fast case, T0 is guaranted not to be used.
> +   value 'b'. In the fast case, T0 is guaranteed not to be used.
>     A translation block must end soon.  */
>  static inline void gen_jcc1(DisasContext *s, int b, TCGLabel *l1)
>  {
> @@ -6841,7 +6841,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
>          if (s->prefix & PREFIX_LOCK) {
>              switch (op) {
>              case 0: /* bt */
> -                /* Needs no atomic ops; we surpressed the normal
> +                /* Needs no atomic ops; we suppressed the normal
>                     memory load for LOCK above so do it now.  */
>                  gen_op_ld_v(s, ot, s->T0, s->A0);
>                  break;
> diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c
> index 5a0f337..661f9c7 100644
> --- a/target/i386/whpx-all.c
> +++ b/target/i386/whpx-all.c
> @@ -1214,7 +1214,7 @@ int whpx_init_vcpu(CPUState *cpu)
>      vcpu = g_malloc0(sizeof(struct whpx_vcpu));
>  
>      if (!vcpu) {
> -        error_report("WHPX: Failed to allocte VCPU context.");
> +        error_report("WHPX: Failed to allocate VCPU context.");
>          return -ENOMEM;
>      }
>  
> -- 
> 2.26.2.windows.1

dme.
-- 
Tell me sweet little lies.

Re: [PATCH RFC 11/14] avr/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:18 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/avr.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/avr/helper.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/avr/helper.c b/target/avr/helper.c
> index d96d143..9f325bc 100644
> --- a/target/avr/helper.c
> +++ b/target/avr/helper.c
> @@ -97,7 +97,7 @@ int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
>  
>  hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>  {
> -    return addr; /* I assume 1:1 address correspondance */
> +    return addr; /* I assume 1:1 address correspondence */
>  }
>  
>  bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> @@ -298,7 +298,7 @@ void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
>  }
>  
>  /*
> - *  this function implements LD instruction when there is a posibility to read
> + *  this function implements LD instruction when there is a possibility to read
>   *  from a CPU register
>   */
>  target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
> @@ -322,7 +322,7 @@ target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
>  }
>  
>  /*
> - *  this function implements ST instruction when there is a posibility to write
> + *  this function implements ST instruction when there is a possibility to write
>   *  into a CPU register
>   */
>  void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
> -- 
> 2.26.2.windows.1

dme.
-- 
I'm in California dreaming about who we used to be.

Re: [PATCH RFC 12/14] arm/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:19 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/arm.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/arm/cpu.h           | 2 +-
>  target/arm/helper.c        | 4 ++--
>  target/arm/m_helper.c      | 2 +-
>  target/arm/translate-a64.c | 4 ++--
>  target/arm/translate-sve.c | 2 +-
>  5 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 6036f61..996308b 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2067,7 +2067,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
>      return aa64;
>  }
>  
> -/* Function for determing whether guest cp register reads and writes should
> +/* Function for determining whether guest cp register reads and writes should
>   * access the secure or non-secure bank of a cp register.  When EL3 is
>   * operating in AArch32 state, the NS-bit determines whether the secure
>   * instance of a cp register should be used. When EL3 is AArch64 (or if
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 88bd9dd..9292e16 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1867,7 +1867,7 @@ static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
>       * pmevtyper_rawwrite is called between a pair of pmu_op_start and
>       * pmu_op_finish calls when loading saved state for a migration. Because
>       * we're potentially updating the type of event here, the value written to
> -     * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
> +     * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
>       * different counter type. Therefore, we need to set this value to the
>       * current count for the counter type we're writing so that pmu_op_finish
>       * has the correct count for its calculation.
> @@ -12214,7 +12214,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
>              } else {
>                  memattr = 0x44;  /* Normal, NC, No */
>              }
> -            cacheattrs->shareability = 2; /* outer sharable */
> +            cacheattrs->shareability = 2; /* outer shareable */
>          } else {
>              memattr = 0x00;      /* Device, nGnRnE */
>          }
> diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
> index 0364542..1e8080d 100644
> --- a/target/arm/m_helper.c
> +++ b/target/arm/m_helper.c
> @@ -158,7 +158,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
>       *  R: 0 because unpriv and A flag not set
>       *  SRVALID: 0 because NS
>       *  MRVALID: 0 because unpriv and A flag not set
> -     *  SREGION: 0 becaus SRVALID is 0
> +     *  SREGION: 0 because SRVALID is 0
>       *  MREGION: 0 because MRVALID is 0
>       */
>      return 0;
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 7188808..5451f02 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -160,7 +160,7 @@ void gen_a64_set_pc_im(uint64_t val)
>   *  + for EL2 and EL3 there is only one TBI bit, and if it is set
>   *    then the address is zero-extended, clearing bits [63:56]
>   *  + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
> - *    and TBI1 controls addressses with bit 55 == 1.
> + *    and TBI1 controls addresses with bit 55 == 1.
>   *    If the appropriate TBI bit is set for the address then
>   *    the address is sign-extended from bit 55 into bits [63:56]
>   *
> @@ -1964,7 +1964,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
>      }
>      if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
>          /*
> -         * A write to any coprocessor regiser that ends a TB
> +         * A write to any coprocessor register that ends a TB
>           * must rebuild the hflags for the next TB.
>           */
>          TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index e4cd6b6..4e8a1c7 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -1528,7 +1528,7 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
>  
>  /* Perform an inline saturating addition of a 32-bit value within
>   * a 64-bit register.  The second operand is known to be positive,
> - * which halves the comparisions we must perform to bound the result.
> + * which halves the comparisons we must perform to bound the result.
>   */
>  static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
>  {
> -- 
> 2.26.2.windows.1

dme.
-- 
Tell me sweet little lies.

Re: [PATCH RFC 13/14] alpha/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:20 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target/alpha.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/alpha/cpu.h       | 4 ++--
>  target/alpha/translate.c | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index be29bdd..8a6d477 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -190,7 +190,7 @@ enum {
>  
>     That said, we're only emulating Unix PALcode, and not attempting VMS,
>     so we don't need to implement Executive and Supervisor.  QEMU's own
> -   PALcode cheats and usees the KSEG mapping for its code+data rather than
> +   PALcode cheats and uses the KSEG mapping for its code+data rather than
>     physical addresses.  */
>  
>  #define MMU_KERNEL_IDX   0
> @@ -370,7 +370,7 @@ enum {
>     The Unix PALcode only uses bit 4.  */
>  #define PS_USER_MODE  8u
>  
> -/* CPUAlphaState->flags constants.  These are layed out so that we
> +/* CPUAlphaState->flags constants.  These are laid out so that we
>     can set or reset the pieces individually by assigning to the byte,
>     or manipulated as a whole.  */
>  
> diff --git a/target/alpha/translate.c b/target/alpha/translate.c
> index 8870284..6aef9ec 100644
> --- a/target/alpha/translate.c
> +++ b/target/alpha/translate.c
> @@ -2939,7 +2939,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
>         the first fp insn of the TB.  Alternately we could define a proper
>         default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
>         to reset the FP_STATUS to that default at the end of any TB that
> -       changes the default.  We could even (gasp) dynamiclly figure out
> +       changes the default.  We could even (gasp) dynamically figure out
>         what default would be most efficient given the running program.  */
>      ctx->tb_rm = -1;
>      /* Similarly for flush-to-zero.  */
> -- 
> 2.26.2.windows.1

dme.
-- 
They like the smell of it in Hollywood.

Re: [PATCH RFC 14/14] target/: fix some comment spelling errors

[David Edmondson]

On Wednesday, 2020-09-30 at 17:53:21 +08, zhaolichang wrote:

> I found that there are many spelling errors in the comments of qemu/target.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

> ---
>  target/openrisc/cpu.h        | 2 +-
>  target/sparc/asi.h           | 2 +-
>  target/unicore32/translate.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index bd42faf..8ca8605 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState {
>      int is_counting;
>  
>      uint32_t picmr;         /* Interrupt mask register */
> -    uint32_t picsr;         /* Interrupt contrl register*/
> +    uint32_t picsr;         /* Interrupt control register*/
>  #endif
>      void *irq[32];          /* Interrupt irq input */
>  } CPUOpenRISCState;
> diff --git a/target/sparc/asi.h b/target/sparc/asi.h
> index bb58735..4e9f1d5 100644
> --- a/target/sparc/asi.h
> +++ b/target/sparc/asi.h
> @@ -231,7 +231,7 @@
>  #define ASI_INTR_ID		0x63 /* (CMT) Interrupt ID register	*/
>  #define ASI_CORE_ID		0x63 /* (CMT) LP ID register		*/
>  #define ASI_CESR_ID		0x63 /* (CMT) CESR ID register		*/
> -#define ASI_IC_INSTR		0x66 /* Insn cache instrucion ram diag	*/
> +#define ASI_IC_INSTR		0x66 /* Insn cache instruction ram diag	*/
>  #define ASI_IC_TAG		0x67 /* Insn cache tag/valid ram diag 	*/
>  #define ASI_IC_STAG		0x68 /* (III) Insn cache snoop tag ram	*/
>  #define ASI_IC_PRE_DECODE	0x6e /* Insn cache pre-decode ram diag	*/
> diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
> index d4b06df..2e91b05 100644
> --- a/target/unicore32/translate.c
> +++ b/target/unicore32/translate.c
> @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg)
>  {
>      if (reg == 31) {
>          uint32_t addr;
> -        /* normaly, since we updated PC */
> +        /* normally, since we updated PC */
>          addr = (long)s->pc;
>          tcg_gen_movi_i32(var, addr);
>      } else {
> -- 
> 2.26.2.windows.1

dme.
-- 
Tell her I'll be waiting, in the usual place.

Re: [PATCH RFC 03/14] riscv/: fix some comment spelling errors

[Alistair Francis]

On Wed, Sep 30, 2020 at 2:56 AM zhaolichang <zhaolichang@huawei.com> wrote:
>
> I found that there are many spelling errors in the comments of qemu/target/riscv.
> I used spellcheck to check the spelling errors and found some errors in the folder.
>
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c           | 2 +-
>  target/riscv/cpu_bits.h      | 2 +-
>  target/riscv/csr.c           | 6 +++---
>  target/riscv/vector_helper.c | 2 +-
>  4 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f..f40a0b2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>                      return;
>                  }
>              } else {
> -                qemu_log("vector verison is not specified, "
> +                qemu_log("vector version is not specified, "
>                          "use the default value v0.7.1\n");
>              }
>              set_vext_version(env, vext_version);
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index bd36062..6e11555 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -536,7 +536,7 @@
>  /* Leaf page shift amount */
>  #define PGSHIFT             12
>
> -/* Default Reset Vector adress */
> +/* Default Reset Vector address */
>  #define DEFAULT_RSTVEC      0x1000
>
>  /* Exception causes */
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 26ae347..559db11 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
>      return 0;
>  }
>
> -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
> +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
>  {
>      if (env->priv_ver < PRIV_VERSION_1_11_0) {
> @@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
>      return 0;
>  }
>
> -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
> +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
>  static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
>  {
>      if (env->priv_ver < PRIV_VERSION_1_11_0) {
> @@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>          !riscv_cpu_virt_enabled(env)) {
>          /*
>           * We are in S mode without virtualisation, therefore we are in HS Mode.
> -         * Add 1 to the effective privledge level to allow us to access the
> +         * Add 1 to the effective privilege level to allow us to access the
>           * Hypervisor CSRs.
>           */
>          effective_priv++;
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index a156573..fa89a6e 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
>                                    uint32_t wd, uint32_t idx, CPURISCVState *env,
>                                    uintptr_t retaddr);
>
> -/* no atomic opreation for vector atomic insructions */
> +/* no atomic operation for vector atomic insructions */
>  #define DO_SWAP(N, M) (M)
>  #define DO_AND(N, M)  (N & M)
>  #define DO_XOR(N, M)  (N ^ M)
> --
> 2.26.2.windows.1
>
>

Re: [PATCH RFC 13/14] alpha/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/alpha.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
> ---
>  target/alpha/cpu.h       | 4 ++--
>  target/alpha/translate.c | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH RFC 08/14] m68k/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 12:26 PM, Laurent Vivier wrote:
> Le 30/09/2020 à 11:53, zhaolichang a écrit :
>> I found that there are many spelling errors in the comments of qemu/target/m68k.
>> I used spellcheck to check the spelling errors and found some errors in the folder.
>>
>> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
>> ---
>>  target/m68k/translate.c | 16 ++++++++--------
>>  1 file changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
>> index 3fc67aa..133a404 100644
>> --- a/target/m68k/translate.c
>> +++ b/target/m68k/translate.c
>> @@ -438,7 +438,7 @@ static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
>>  }
>>  
>>  /*
>> - * Handle a base + index + displacement effective addresss.
>> + * Handle a base + index + displacement effective address.
>>   * A NULL_QREG base means pc-relative.
>>   */
>>  static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
>> @@ -1696,7 +1696,7 @@ static void bcd_add(TCGv dest, TCGv src)
>>  
>>      /*
>>       * t1 = (src + 0x066) + dest + X
>> -     *    = result with some possible exceding 0x6
>> +     *    = result with some possible exceeding 0x6
>>       */
>>  
>>      t0 = tcg_const_i32(0x066);
>> @@ -1706,7 +1706,7 @@ static void bcd_add(TCGv dest, TCGv src)
>>      tcg_gen_add_i32(t1, t0, dest);
>>      tcg_gen_add_i32(t1, t1, QREG_CC_X);
>>  
>> -    /* we will remove exceding 0x6 where there is no carry */
>> +    /* we will remove exceeding 0x6 where there is no carry */
>>  
>>      /*
>>       * t0 = (src + 0x0066) ^ dest
>> @@ -1736,7 +1736,7 @@ static void bcd_add(TCGv dest, TCGv src)
>>      tcg_temp_free(t0);
>>  
>>      /*
>> -     * remove the exceding 0x6
>> +     * remove the exceeding 0x6
>>       * for digits that have not generated a carry
>>       */
>>  
>> @@ -2638,7 +2638,7 @@ DISAS_INSN(negx)
>>      gen_flush_flags(s); /* compute old Z */
>>  
>>      /*
>> -     * Perform substract with borrow.
>> +     * Perform subtract with borrow.
>>       * (X, N) =  -(src + X);
>>       */
>>  
>> @@ -2653,7 +2653,7 @@ DISAS_INSN(negx)
>>      /*
>>       * Compute signed-overflow for negation.  The normal formula for
>>       * subtraction is (res ^ src) & (src ^ dest), but with dest==0
>> -     * this simplies to res & src.
>> +     * this simplifies to res & src.
>>       */
>>  
>>      tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
>> @@ -3159,7 +3159,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
>>      gen_flush_flags(s); /* compute old Z */
>>  
>>      /*
>> -     * Perform substract with borrow.
>> +     * Perform subtract with borrow.
>>       * (X, N) = dest - (src + X);
>>       */
>>  
>> @@ -3169,7 +3169,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
>>      gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
>>      tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
>>  
>> -    /* Compute signed-overflow for substract.  */
>> +    /* Compute signed-overflow for subtract.  */
>>  
>>      tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
>>      tcg_gen_xor_i32(tmp, dest, src);
>>
> 
> Reviewed-by: Laurent Vivier <laurent@vivier>

Reviewed-by: Laurent Vivier <laurent@vivier.eu>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH RFC 12/14] arm/: fix some comment spelling errors

[Philippe Mathieu-Daudé]

On 9/30/20 11:53 AM, zhaolichang wrote:
> I found that there are many spelling errors in the comments of qemu/target/arm.
> I used spellcheck to check the spelling errors and found some errors in the folder.
> 
> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
> ---
>  target/arm/cpu.h           | 2 +-
>  target/arm/helper.c        | 4 ++--
>  target/arm/m_helper.c      | 2 +-
>  target/arm/translate-a64.c | 4 ++--
>  target/arm/translate-sve.c | 2 +-
>  5 files changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH RFC 08/14] m68k/: fix some comment spelling errors

[Laurent Vivier]

Le 30/09/2020 à 18:03, Philippe Mathieu-Daudé a écrit :
> On 9/30/20 12:26 PM, Laurent Vivier wrote:
>> Le 30/09/2020 à 11:53, zhaolichang a écrit :
>>> I found that there are many spelling errors in the comments of qemu/target/m68k.
>>> I used spellcheck to check the spelling errors and found some errors in the folder.
>>>
>>> Signed-off-by: zhaolichang <zhaolichang@huawei.com>
>>> ---
>>>  target/m68k/translate.c | 16 ++++++++--------
>>>  1 file changed, 8 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
>>> index 3fc67aa..133a404 100644
>>> --- a/target/m68k/translate.c
>>> +++ b/target/m68k/translate.c
>>> @@ -438,7 +438,7 @@ static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
>>>  }
>>>  
>>>  /*
>>> - * Handle a base + index + displacement effective addresss.
>>> + * Handle a base + index + displacement effective address.
>>>   * A NULL_QREG base means pc-relative.
>>>   */
>>>  static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
>>> @@ -1696,7 +1696,7 @@ static void bcd_add(TCGv dest, TCGv src)
>>>  
>>>      /*
>>>       * t1 = (src + 0x066) + dest + X
>>> -     *    = result with some possible exceding 0x6
>>> +     *    = result with some possible exceeding 0x6
>>>       */
>>>  
>>>      t0 = tcg_const_i32(0x066);
>>> @@ -1706,7 +1706,7 @@ static void bcd_add(TCGv dest, TCGv src)
>>>      tcg_gen_add_i32(t1, t0, dest);
>>>      tcg_gen_add_i32(t1, t1, QREG_CC_X);
>>>  
>>> -    /* we will remove exceding 0x6 where there is no carry */
>>> +    /* we will remove exceeding 0x6 where there is no carry */
>>>  
>>>      /*
>>>       * t0 = (src + 0x0066) ^ dest
>>> @@ -1736,7 +1736,7 @@ static void bcd_add(TCGv dest, TCGv src)
>>>      tcg_temp_free(t0);
>>>  
>>>      /*
>>> -     * remove the exceding 0x6
>>> +     * remove the exceeding 0x6
>>>       * for digits that have not generated a carry
>>>       */
>>>  
>>> @@ -2638,7 +2638,7 @@ DISAS_INSN(negx)
>>>      gen_flush_flags(s); /* compute old Z */
>>>  
>>>      /*
>>> -     * Perform substract with borrow.
>>> +     * Perform subtract with borrow.
>>>       * (X, N) =  -(src + X);
>>>       */
>>>  
>>> @@ -2653,7 +2653,7 @@ DISAS_INSN(negx)
>>>      /*
>>>       * Compute signed-overflow for negation.  The normal formula for
>>>       * subtraction is (res ^ src) & (src ^ dest), but with dest==0
>>> -     * this simplies to res & src.
>>> +     * this simplifies to res & src.
>>>       */
>>>  
>>>      tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
>>> @@ -3159,7 +3159,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
>>>      gen_flush_flags(s); /* compute old Z */
>>>  
>>>      /*
>>> -     * Perform substract with borrow.
>>> +     * Perform subtract with borrow.
>>>       * (X, N) = dest - (src + X);
>>>       */
>>>  
>>> @@ -3169,7 +3169,7 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
>>>      gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
>>>      tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
>>>  
>>> -    /* Compute signed-overflow for substract.  */
>>> +    /* Compute signed-overflow for subtract.  */
>>>  
>>>      tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
>>>      tcg_gen_xor_i32(tmp, dest, src);
>>>
>>
>> Reviewed-by: Laurent Vivier <laurent@vivier>
> 
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>

Yes, thanks.

> 
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 

Laurent