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[<bogus@does.not.exist.com>]

8bit ECC correction. So I am not sure this constrain might due to older
version controller. Wonder you have any insight on this?


> 
> Denali's document says
> For 512B ECC sector size,
>    ecc.bytes = Ceiling to next word (13 * ecc.strength)
> For 1024B ECC sector size,
>    ecc.bytes = Ceiling to next word (14 * ecc.strength)
> 
> 
> 
> And denali_setup_dma_sequence() function
> (Why did you rename this function?)
> did not work either.
> I needed to fix it locally.
> 
> 
> So bad news is this version itself does not work for me.
> Good news is I could adjust it locally and confirmed some features
> worked. (But I think I need more test.)
> 
> So, how will this situation work?
> It turned out there are some differences between
> two Denali hardwares and this driver works only for yours.
> 
> You merge it first, and (if you don't mind) shall I modify it
> in a more generic way to run on both hardwares?
> 


Anyway will work for me. I can take your comments and change the driver
accordingly too.


> > If you want to run under SPL, there are some patches for that. Let me
> > know if you need that. While for U-Boot, they are working fine. Probably
> 
> Thanks for your offering help.
> But I am not sure if SOCFPGA and UniPhier can share a SPL nand driver.
> (Actually I have locally our own Denali driver for SPL.
> And I have Denali driver for main U-Boot, which is adjusted for
> our SoCs, too.
> But I don't mind to switch onto your driver if it works for me.)
> 


Oh for SPL, I can use the same driver too. Just that I would need to
update the nand_spl_simple.c. The main changes is to use the HW ECC
feature instead of getting software calculate and fix the ECC. FYI, the
patch I made for SPL is located at
http://rocketboards.org/gitweb/?p=u-boot-socfpga.git;a=commit;h=461a61b8f03d3b690de1f4ff007cd23fb80018a5

> > +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> > +#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NAND_REGS_ADDRESS
> > +#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NAND_DATA_ADDRESS
> > +#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND_REGS_BASE
> 
> Maybe
> #define CONFIG_SYS_NAND_BASE	(SOCFPGA_NAND_DATA_ADDRESS + 0x10)
> ?
> 


For SOCFPGA, the register and data base address have large address space
in between them. End of day, it seems its tightly to hardware guys
implementation.


> 
> BTW, you changed all  denali->foo  to denali.foo.
> It looks unnecessay to me.
> 


Hmmm.. I suspect this changed when we declare denali as static global.

Thanks
Chin Liang

> 
> Best Regards
> Masahiro Yamada
> 
>