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From: Palmer Dabbelt <palmer@dabbelt.com>
To: vincent.chen@sifive.com
Cc: daniel.thompson@linaro.org, kgdb-bugreport@lists.sourceforge.net,
	jason.wessel@windriver.com, dianders@chromium.org,
	vincent.chen@sifive.com, Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 4/5] riscv: Use the XML target descriptions to report 3 system registers
Date: Thu, 16 Apr 2020 12:12:11 -0700 (PDT)	[thread overview]
Message-ID: <mhng-062ce9f5-ddff-43e4-8fc9-1ebaeead969c@palmerdabbelt-glaptop1> (raw)
In-Reply-To: <1585668191-16287-5-git-send-email-vincent.chen@sifive.com>

On Tue, 31 Mar 2020 08:23:10 PDT (-0700), vincent.chen@sifive.com wrote:
> The $sstatus, $badaddr, and $scause registers belong to the thread context,
> so KGDB can obtain their contents from pt_regs in each trap. However, the
> sequential number of these registers in the gdb register list is far from
> the general-purpose registers. If riscv port uses the existing method to
> report these three registers, many trivial registers with sequence numbers
> in the middle of them will also be packaged to the reply packets. To solve
> this problem, the riscv port wants to introduce the GDB target description
> mechanism to customize the reported register list. By the list, the KGDB
> can ignore the intermediate registers and just reports the general-purpose
> registers and these three system registers.
>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> ---
>  arch/riscv/Kconfig               |   1 +
>  arch/riscv/include/asm/gdb_xml.h | 117 +++++++++++++++++++++++++++++++++++++++
>  arch/riscv/include/asm/kgdb.h    |   8 ++-
>  arch/riscv/kernel/kgdb.c         |  14 +++++
>  4 files changed, 139 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/include/asm/gdb_xml.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 108794f4aa45..94b6f301007c 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -67,6 +67,7 @@ config RISCV
>  	select HAVE_COPY_THREAD_TLS
>  	select HAVE_ARCH_KASAN if MMU && 64BIT
>  	select HAVE_ARCH_KGDB
> +	select ARCH_SUPPORTS_GDB_XML
>
>  config ARCH_MMAP_RND_BITS_MIN
>  	default 18 if 64BIT
> diff --git a/arch/riscv/include/asm/gdb_xml.h b/arch/riscv/include/asm/gdb_xml.h
> new file mode 100644
> index 000000000000..1d1459d06a1b
> --- /dev/null
> +++ b/arch/riscv/include/asm/gdb_xml.h
> @@ -0,0 +1,117 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __ASM_GDB_XML_H_
> +#define __ASM_GDB_XML_H_
> +
> +#define arch_gdb_stub_feature riscv_gdb_stub_feature
> +static const char riscv_gdb_stub_feature[64] =
> +			"PacketSize=800;qXfer:features:read+;";
> +
> +static const char gdb_xfer_read_target[31] = "qXfer:features:read:target.xml:";
> +
> +#ifdef CONFIG_64BIT
> +static const char gdb_xfer_read_cpuxml[39] =
> +			"qXfer:features:read:riscv-64bit-cpu.xml";
> +
> +static const char riscv_gdb_stub_target_desc[256] =
> +"l<?xml version=\"1.0\"?>"
> +"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
> +"<target>"
> +"<xi:include href=\"riscv-64bit-cpu.xml\"/>"
> +"</target>";
> +
> +static const char riscv_gdb_stub_cpuxml[2048] =
> +"l<?xml version=\"1.0\"?>"
> +"<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"
> +"<feature name=\"org.gnu.gdb.riscv.cpu\">"
> +"<reg name=\""DBG_REG_ZERO"\" bitsize=\"64\" type=\"int\" regnum=\"0\"/>"
> +"<reg name=\""DBG_REG_RA"\" bitsize=\"64\" type=\"code_ptr\"/>"
> +"<reg name=\""DBG_REG_SP"\" bitsize=\"64\" type=\"data_ptr\"/>"
> +"<reg name=\""DBG_REG_GP"\" bitsize=\"64\" type=\"data_ptr\"/>"
> +"<reg name=\""DBG_REG_TP"\" bitsize=\"64\" type=\"data_ptr\"/>"
> +"<reg name=\""DBG_REG_T0"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T1"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T2"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_FP"\" bitsize=\"64\" type=\"data_ptr\"/>"
> +"<reg name=\""DBG_REG_S1"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A0"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A1"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A2"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A3"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A4"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A5"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A6"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A7"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S2"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S3"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S4"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S5"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S6"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S7"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S8"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S9"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S10"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S11"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T3"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T4"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T5"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T6"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_EPC"\" bitsize=\"64\" type=\"code_ptr\"/>"
> +"<reg name=\""DBG_REG_STATUS"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_BADADDR"\" bitsize=\"64\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_CAUSE"\" bitsize=\"64\" type=\"int\"/>"
> +"</feature>";
> +#else
> +static const char gdb_xfer_read_cpuxml[39] =
> +			"qXfer:features:read:riscv-32bit-cpu.xml";
> +
> +static const char riscv_gdb_stub_target_desc[256] =
> +"l<?xml version=\"1.0\"?>"
> +"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
> +"<target>"
> +"<xi:include href=\"riscv-32bit-cpu.xml\"/>"
> +"</target>";
> +
> +static const char riscv_gdb_stub_cpuxml[2048] =
> +"l<?xml version=\"1.0\"?>"
> +"<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"
> +"<feature name=\"org.gnu.gdb.riscv.cpu\">"
> +"<reg name=\""DBG_REG_ZERO"\" bitsize=\"32\" type=\"int\" regnum=\"0\"/>"
> +"<reg name=\""DBG_REG_RA"\" bitsize=\"32\" type=\"code_ptr\"/>"
> +"<reg name=\""DBG_REG_SP"\" bitsize=\"32\" type=\"data_ptr\"/>"
> +"<reg name=\""DBG_REG_GP"\" bitsize=\"32\" type=\"data_ptr\"/>"
> +"<reg name=\""DBG_REG_TP"\" bitsize=\"32\" type=\"data_ptr\"/>"
> +"<reg name=\""DBG_REG_T0"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T1"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T2"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_FP"\" bitsize=\"32\" type=\"data_ptr\"/>"
> +"<reg name=\""DBG_REG_S1"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A0"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A1"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A2"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A3"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A4"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A5"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A6"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_A7"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S2"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S3"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S4"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S5"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S6"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S7"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S8"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S9"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S10"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_S11"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T3"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T4"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T5"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_T6"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_EPC"\" bitsize=\"32\" type=\"code_ptr\"/>"
> +"<reg name=\""DBG_REG_STATUS"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_BADADDR"\" bitsize=\"32\" type=\"int\"/>"
> +"<reg name=\""DBG_REG_CAUSE"\" bitsize=\"32\" type=\"int\"/>"
> +"</feature>";
> +#endif
> +#endif
> diff --git a/arch/riscv/include/asm/kgdb.h b/arch/riscv/include/asm/kgdb.h
> index 69bc6a03081d..6c35a853940d 100644
> --- a/arch/riscv/include/asm/kgdb.h
> +++ b/arch/riscv/include/asm/kgdb.h
> @@ -7,7 +7,7 @@
>
>  #define GDB_SIZEOF_REG sizeof(unsigned long)
>
> -#define DBG_MAX_REG_NUM (33)
> +#define DBG_MAX_REG_NUM (36)
>  #define NUMREGBYTES ((DBG_MAX_REG_NUM) * GDB_SIZEOF_REG)
>  #define CACHE_FLUSH_IS_SAFE     1
>  #define BUFMAX                  2048
> @@ -66,6 +66,9 @@ static inline void arch_kgdb_breakpoint(void)
>  #define DBG_REG_T5 "t5"
>  #define DBG_REG_T6 "t6"
>  #define DBG_REG_EPC "pc"
> +#define DBG_REG_STATUS "sstatus"
> +#define DBG_REG_BADADDR "stval"
> +#define DBG_REG_CAUSE "scause"
>
>  #define DBG_REG_ZERO_OFF 0
>  #define DBG_REG_RA_OFF 1
> @@ -103,5 +106,8 @@ static inline void arch_kgdb_breakpoint(void)
>  #define DBG_REG_STATUS_OFF 33
>  #define DBG_REG_BADADDR_OFF 34
>  #define DBG_REG_CAUSE_OFF 35
> +
> +#include <asm/gdb_xml.h>
> +
>  #endif
>  #endif
> diff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c
> index e3b1075c3935..86d891b7ea2c 100644
> --- a/arch/riscv/kernel/kgdb.c
> +++ b/arch/riscv/kernel/kgdb.c
> @@ -7,6 +7,7 @@
>  #include <linux/irqflags.h>
>  #include <linux/string.h>
>  #include <asm/cacheflush.h>
> +#include <asm/gdb_xml.h>
>
>  enum {
>  	NOT_KGDB_BREAK = 0,
> @@ -48,6 +49,9 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
>  	{DBG_REG_T5, GDB_SIZEOF_REG, offsetof(struct pt_regs, t5)},
>  	{DBG_REG_T6, GDB_SIZEOF_REG, offsetof(struct pt_regs, t6)},
>  	{DBG_REG_EPC, GDB_SIZEOF_REG, offsetof(struct pt_regs, epc)},
> +	{DBG_REG_STATUS, GDB_SIZEOF_REG, offsetof(struct pt_regs, status)},
> +	{DBG_REG_BADADDR, GDB_SIZEOF_REG, offsetof(struct pt_regs, badaddr)},
> +	{DBG_REG_CAUSE, GDB_SIZEOF_REG, offsetof(struct pt_regs, cause)},
>  };
>
>  char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
> @@ -100,6 +104,16 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
>  	regs->epc = pc;
>  }
>
> +void arch_handle_qxfer_pkt(char *remcom_in_buffer, char *remcom_out_buffer)
> +{
> +	if (!strncmp(remcom_in_buffer, gdb_xfer_read_target,
> +		     sizeof(gdb_xfer_read_target)))
> +		strcpy(remcom_out_buffer, riscv_gdb_stub_target_desc);
> +	else if (!strncmp(remcom_in_buffer, gdb_xfer_read_cpuxml,
> +			  sizeof(gdb_xfer_read_cpuxml)))
> +		strcpy(remcom_out_buffer, riscv_gdb_stub_cpuxml);
> +}
> +
>  static inline void kgdb_arch_update_addr(struct pt_regs *regs,
>  					 char *remcom_in_buffer)
>  {

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>


  reply	other threads:[~2020-04-16 19:12 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-31 15:23 [PATCH v2 0/5] riscv: Add KGDB and KDB support Vincent Chen
2020-03-31 15:23 ` [PATCH v2 1/5] kgdb: Add kgdb_has_hit_break function Vincent Chen
2020-04-03 10:22   ` Daniel Thompson
2020-03-31 15:23 ` [PATCH v2 2/5] riscv: Add KGDB support Vincent Chen
2020-03-31 15:23 ` [PATCH v2 3/5] kgdb: enable arch to support XML packet support Vincent Chen
2020-04-03 10:03   ` Daniel Thompson
2020-04-06  0:42     ` Vincent Chen
2020-03-31 15:23 ` [PATCH v2 4/5] riscv: Use the XML target descriptions to report 3 system registers Vincent Chen
2020-04-16 19:12   ` Palmer Dabbelt [this message]
2020-03-31 15:23 ` [PATCH v2 5/5] riscv: Add SW single-step support for KDB Vincent Chen
2020-04-16 19:13   ` Palmer Dabbelt
2020-04-03 10:12 ` [PATCH v2 0/5] riscv: Add KGDB and KDB support Daniel Thompson
2020-04-06  2:35   ` Vincent Chen
2020-04-06  4:14     ` Anup Patel
2020-04-16 19:13 ` Palmer Dabbelt

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