* [Qemu-devel] [PATCH v2] riscv: sifive_test: Add reset functionality
@ 2019-09-05 15:55 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2019-09-05 15:55 UTC (permalink / raw)
To: Palmer Dabbelt, qemu-devel, qemu-riscv
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
Changes in v2:
- fix build error in the "for-master" branch of Palmer's RISC-V repo
that was rebased on QEMU master
hw/riscv/sifive_test.c | 4 ++++
include/hw/riscv/sifive_test.h | 3 ++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index afbb3aa..3557e16 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -22,6 +22,7 @@
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
+#include "sysemu/runstate.h"
#include "target/riscv/cpu.h"
#include "hw/hw.h"
#include "hw/riscv/sifive_test.h"
@@ -42,6 +43,9 @@ static void sifive_test_write(void *opaque, hwaddr addr,
exit(code);
case FINISHER_PASS:
exit(0);
+ case FINISHER_RESET:
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
default:
break;
}
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h
index 3a603a6..1ec416a 100644
--- a/include/hw/riscv/sifive_test.h
+++ b/include/hw/riscv/sifive_test.h
@@ -36,7 +36,8 @@ typedef struct SiFiveTestState {
enum {
FINISHER_FAIL = 0x3333,
- FINISHER_PASS = 0x5555
+ FINISHER_PASS = 0x5555,
+ FINISHER_RESET = 0x7777
};
DeviceState *sifive_test_create(hwaddr addr);
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-riscv] [PATCH v2] riscv: sifive_test: Add reset functionality
@ 2019-09-05 15:55 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2019-09-05 15:55 UTC (permalink / raw)
To: Palmer Dabbelt, qemu-devel, qemu-riscv
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
Changes in v2:
- fix build error in the "for-master" branch of Palmer's RISC-V repo
that was rebased on QEMU master
hw/riscv/sifive_test.c | 4 ++++
include/hw/riscv/sifive_test.h | 3 ++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index afbb3aa..3557e16 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -22,6 +22,7 @@
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
+#include "sysemu/runstate.h"
#include "target/riscv/cpu.h"
#include "hw/hw.h"
#include "hw/riscv/sifive_test.h"
@@ -42,6 +43,9 @@ static void sifive_test_write(void *opaque, hwaddr addr,
exit(code);
case FINISHER_PASS:
exit(0);
+ case FINISHER_RESET:
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
default:
break;
}
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h
index 3a603a6..1ec416a 100644
--- a/include/hw/riscv/sifive_test.h
+++ b/include/hw/riscv/sifive_test.h
@@ -36,7 +36,8 @@ typedef struct SiFiveTestState {
enum {
FINISHER_FAIL = 0x3333,
- FINISHER_PASS = 0x5555
+ FINISHER_PASS = 0x5555,
+ FINISHER_RESET = 0x7777
};
DeviceState *sifive_test_create(hwaddr addr);
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2] riscv: sifive_test: Add reset functionality
2019-09-05 15:55 ` [Qemu-riscv] " Bin Meng
@ 2019-09-05 15:57 ` Bin Meng
-1 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2019-09-05 15:57 UTC (permalink / raw)
To: Palmer Dabbelt, qemu-devel@nongnu.org Developers, open list:RISC-V
Hi Palmer,
On Thu, Sep 5, 2019 at 11:55 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> This adds a reset opcode for sifive_test device to trigger a system
> reset for testing purpose.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>
> ---
>
> Changes in v2:
> - fix build error in the "for-master" branch of Palmer's RISC-V repo
> that was rebased on QEMU master
>
> hw/riscv/sifive_test.c | 4 ++++
> include/hw/riscv/sifive_test.h | 3 ++-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
Please drop the already applied v1 patch in your "for-master" branch
and apply this v2.
After you rebased the "for-master' branch, this patch no longer build
any more due to changes in QEMU master.
Regards,
Bin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-riscv] [PATCH v2] riscv: sifive_test: Add reset functionality
@ 2019-09-05 15:57 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2019-09-05 15:57 UTC (permalink / raw)
To: Palmer Dabbelt, qemu-devel@nongnu.org Developers, open list:RISC-V
Hi Palmer,
On Thu, Sep 5, 2019 at 11:55 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> This adds a reset opcode for sifive_test device to trigger a system
> reset for testing purpose.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>
> ---
>
> Changes in v2:
> - fix build error in the "for-master" branch of Palmer's RISC-V repo
> that was rebased on QEMU master
>
> hw/riscv/sifive_test.c | 4 ++++
> include/hw/riscv/sifive_test.h | 3 ++-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
Please drop the already applied v1 patch in your "for-master" branch
and apply this v2.
After you rebased the "for-master' branch, this patch no longer build
any more due to changes in QEMU master.
Regards,
Bin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2] riscv: sifive_test: Add reset functionality
2019-09-05 15:57 ` [Qemu-riscv] " Bin Meng
@ 2019-09-05 19:16 ` Palmer Dabbelt
-1 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2019-09-05 19:16 UTC (permalink / raw)
To: bmeng.cn; +Cc: qemu-riscv, qemu-devel
On Thu, 05 Sep 2019 08:57:44 PDT (-0700), bmeng.cn@gmail.com wrote:
> Hi Palmer,
>
> On Thu, Sep 5, 2019 at 11:55 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> This adds a reset opcode for sifive_test device to trigger a system
>> reset for testing purpose.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>>
>> ---
>>
>> Changes in v2:
>> - fix build error in the "for-master" branch of Palmer's RISC-V repo
>> that was rebased on QEMU master
>>
>> hw/riscv/sifive_test.c | 4 ++++
>> include/hw/riscv/sifive_test.h | 3 ++-
>> 2 files changed, 6 insertions(+), 1 deletion(-)
>>
>
> Please drop the already applied v1 patch in your "for-master" branch
> and apply this v2.
>
> After you rebased the "for-master' branch, this patch no longer build
> any more due to changes in QEMU master.
>
> Regards,
> Bin
Thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-riscv] [PATCH v2] riscv: sifive_test: Add reset functionality
@ 2019-09-05 19:16 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2019-09-05 19:16 UTC (permalink / raw)
To: bmeng.cn; +Cc: qemu-devel, qemu-riscv
On Thu, 05 Sep 2019 08:57:44 PDT (-0700), bmeng.cn@gmail.com wrote:
> Hi Palmer,
>
> On Thu, Sep 5, 2019 at 11:55 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> This adds a reset opcode for sifive_test device to trigger a system
>> reset for testing purpose.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>>
>> ---
>>
>> Changes in v2:
>> - fix build error in the "for-master" branch of Palmer's RISC-V repo
>> that was rebased on QEMU master
>>
>> hw/riscv/sifive_test.c | 4 ++++
>> include/hw/riscv/sifive_test.h | 3 ++-
>> 2 files changed, 6 insertions(+), 1 deletion(-)
>>
>
> Please drop the already applied v1 patch in your "for-master" branch
> and apply this v2.
>
> After you rebased the "for-master' branch, this patch no longer build
> any more due to changes in QEMU master.
>
> Regards,
> Bin
Thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-09-05 19:17 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-05 15:55 [Qemu-devel] [PATCH v2] riscv: sifive_test: Add reset functionality Bin Meng
2019-09-05 15:55 ` [Qemu-riscv] " Bin Meng
2019-09-05 15:57 ` [Qemu-devel] " Bin Meng
2019-09-05 15:57 ` [Qemu-riscv] " Bin Meng
2019-09-05 19:16 ` [Qemu-devel] " Palmer Dabbelt
2019-09-05 19:16 ` [Qemu-riscv] " Palmer Dabbelt
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