From: Palmer Dabbelt <palmer@dabbelt.com> To: atishp@atishpatra.org Cc: anup@brainfault.org, xypron.glpk@gmx.de, Paul Walmsley <paul.walmsley@sifive.com>, aou@eecs.berkeley.edu, Atish Patra <Atish.Patra@wdc.com>, Anup Patel <Anup.Patel@wdc.com>, wangkefeng.wang@huawei.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, seanga2@gmail.com Subject: Re: [PATCH 1/1] RISC-V: correct enum sbi_ext_rfence_fid Date: Tue, 09 Mar 2021 19:23:34 -0800 (PST) [thread overview] Message-ID: <mhng-559b7914-90be-4626-9f00-487e35289eac@penguin> (raw) In-Reply-To: <CAOnJCULZFHPPXhL5ZyH9qNfb5BgUHos1PU2q6Khb7uT=N-7a3w@mail.gmail.com> On Tue, 09 Mar 2021 11:28:39 PST (-0800), atishp@atishpatra.org wrote: > On Mon, Mar 8, 2021 at 2:55 AM Anup Patel <anup@brainfault.org> wrote: >> >> On Mon, Mar 8, 2021 at 1:19 PM Atish Patra <atishp@atishpatra.org> wrote: >> > >> > On Sat, Mar 6, 2021 at 4:12 AM Anup Patel <anup@brainfault.org> wrote: >> > > >> > > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote: >> > > > >> > > > The constants in enum sbi_ext_rfence_fid should match the SBI >> > > > specification. See >> > > > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing >> > > > >> > > > | Function Name | FID | EID >> > > > | sbi_remote_fence_i | 0 | 0x52464E43 >> > > > | sbi_remote_sfence_vma | 1 | 0x52464E43 >> > > > | sbi_remote_sfence_vma_asid | 2 | 0x52464E43 >> > > > | sbi_remote_hfence_gvma_vmid | 3 | 0x52464E43 >> > > > | sbi_remote_hfence_gvma | 4 | 0x52464E43 >> > > > | sbi_remote_hfence_vvma_asid | 5 | 0x52464E43 >> > > > | sbi_remote_hfence_vvma | 6 | 0x52464E43 >> > > > >> > > > Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions") >> > > > Reported-by: Sean Anderson <seanga2@gmail.com> >> > > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> >> > > > > Reviewed-by: Atish Patra <atish.patra@wdc.com> > >> > > Good catch. >> > > >> > > I guess we never saw any issues because these calls are only used by >> > > KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE >> > > instruction is emulated as flush everything on FPGA, QEMU, and Spike so >> > > we did not notice any issue with KVM RISC-V too. >> > > >> > >> > OpenSBI & Xvisor also define the same order as Linux kernel. The >> > existing order(in Linux kernel) >> > makes more sense w.r.to Lexicographic order as well. >> > >> > Should we just fix the spec instead ? >> >> I would not recommend that because RFENCE is part of the released SBI v0.2 spec. >> > > Fair enough. Yes, agreed. It's very important that we don't change the specs we said are frozen, that would be a huge mess. This is on fixes. Thanks! > >> We have to be more careful in software to follow the spec correctly. >> > > Agreed. Apologies for the slip up. > >> Regards, >> Anup >> >> > >> > > Looks good to me. >> > > >> > > Reviewed-by: Anup Patel <anup@brainfault.org> >> > > >> > > Regards, >> > > Anup >> > > >> > > > --- >> > > > arch/riscv/include/asm/sbi.h | 4 ++-- >> > > > 1 file changed, 2 insertions(+), 2 deletions(-) >> > > > >> > > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h >> > > > index 99895d9c3bdd..d7027411dde8 100644 >> > > > --- a/arch/riscv/include/asm/sbi.h >> > > > +++ b/arch/riscv/include/asm/sbi.h >> > > > @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid { >> > > > SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, >> > > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, >> > > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, >> > > > - SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, >> > > > SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, >> > > > - SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, >> > > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, >> > > > SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, >> > > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, >> > > > }; >> > > > >> > > > enum sbi_ext_hsm_fid { >> > > > -- >> > > > 2.30.1 >> > > > >> > > > >> > > > _______________________________________________ >> > > > linux-riscv mailing list >> > > > linux-riscv@lists.infradead.org >> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv >> > > >> > > _______________________________________________ >> > > linux-riscv mailing list >> > > linux-riscv@lists.infradead.org >> > > http://lists.infradead.org/mailman/listinfo/linux-riscv >> > >> > >> > >> > -- >> > Regards, >> > Atish
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@dabbelt.com> To: atishp@atishpatra.org Cc: anup@brainfault.org, xypron.glpk@gmx.de, Paul Walmsley <paul.walmsley@sifive.com>, aou@eecs.berkeley.edu, Atish Patra <Atish.Patra@wdc.com>, Anup Patel <Anup.Patel@wdc.com>, wangkefeng.wang@huawei.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, seanga2@gmail.com Subject: Re: [PATCH 1/1] RISC-V: correct enum sbi_ext_rfence_fid Date: Tue, 09 Mar 2021 19:23:34 -0800 (PST) [thread overview] Message-ID: <mhng-559b7914-90be-4626-9f00-487e35289eac@penguin> (raw) In-Reply-To: <CAOnJCULZFHPPXhL5ZyH9qNfb5BgUHos1PU2q6Khb7uT=N-7a3w@mail.gmail.com> On Tue, 09 Mar 2021 11:28:39 PST (-0800), atishp@atishpatra.org wrote: > On Mon, Mar 8, 2021 at 2:55 AM Anup Patel <anup@brainfault.org> wrote: >> >> On Mon, Mar 8, 2021 at 1:19 PM Atish Patra <atishp@atishpatra.org> wrote: >> > >> > On Sat, Mar 6, 2021 at 4:12 AM Anup Patel <anup@brainfault.org> wrote: >> > > >> > > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote: >> > > > >> > > > The constants in enum sbi_ext_rfence_fid should match the SBI >> > > > specification. See >> > > > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing >> > > > >> > > > | Function Name | FID | EID >> > > > | sbi_remote_fence_i | 0 | 0x52464E43 >> > > > | sbi_remote_sfence_vma | 1 | 0x52464E43 >> > > > | sbi_remote_sfence_vma_asid | 2 | 0x52464E43 >> > > > | sbi_remote_hfence_gvma_vmid | 3 | 0x52464E43 >> > > > | sbi_remote_hfence_gvma | 4 | 0x52464E43 >> > > > | sbi_remote_hfence_vvma_asid | 5 | 0x52464E43 >> > > > | sbi_remote_hfence_vvma | 6 | 0x52464E43 >> > > > >> > > > Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions") >> > > > Reported-by: Sean Anderson <seanga2@gmail.com> >> > > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> >> > > > > Reviewed-by: Atish Patra <atish.patra@wdc.com> > >> > > Good catch. >> > > >> > > I guess we never saw any issues because these calls are only used by >> > > KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE >> > > instruction is emulated as flush everything on FPGA, QEMU, and Spike so >> > > we did not notice any issue with KVM RISC-V too. >> > > >> > >> > OpenSBI & Xvisor also define the same order as Linux kernel. The >> > existing order(in Linux kernel) >> > makes more sense w.r.to Lexicographic order as well. >> > >> > Should we just fix the spec instead ? >> >> I would not recommend that because RFENCE is part of the released SBI v0.2 spec. >> > > Fair enough. Yes, agreed. It's very important that we don't change the specs we said are frozen, that would be a huge mess. This is on fixes. Thanks! > >> We have to be more careful in software to follow the spec correctly. >> > > Agreed. Apologies for the slip up. > >> Regards, >> Anup >> >> > >> > > Looks good to me. >> > > >> > > Reviewed-by: Anup Patel <anup@brainfault.org> >> > > >> > > Regards, >> > > Anup >> > > >> > > > --- >> > > > arch/riscv/include/asm/sbi.h | 4 ++-- >> > > > 1 file changed, 2 insertions(+), 2 deletions(-) >> > > > >> > > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h >> > > > index 99895d9c3bdd..d7027411dde8 100644 >> > > > --- a/arch/riscv/include/asm/sbi.h >> > > > +++ b/arch/riscv/include/asm/sbi.h >> > > > @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid { >> > > > SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, >> > > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, >> > > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, >> > > > - SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, >> > > > SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, >> > > > - SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, >> > > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, >> > > > SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, >> > > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, >> > > > }; >> > > > >> > > > enum sbi_ext_hsm_fid { >> > > > -- >> > > > 2.30.1 >> > > > >> > > > >> > > > _______________________________________________ >> > > > linux-riscv mailing list >> > > > linux-riscv@lists.infradead.org >> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv >> > > >> > > _______________________________________________ >> > > linux-riscv mailing list >> > > linux-riscv@lists.infradead.org >> > > http://lists.infradead.org/mailman/listinfo/linux-riscv >> > >> > >> > >> > -- >> > Regards, >> > Atish _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-03-10 3:24 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-06 5:48 [PATCH 1/1] RISC-V: correct enum sbi_ext_rfence_fid Heinrich Schuchardt 2021-03-06 5:48 ` Heinrich Schuchardt 2021-03-06 12:12 ` Anup Patel 2021-03-06 12:12 ` Anup Patel 2021-03-08 7:49 ` Atish Patra 2021-03-08 7:49 ` Atish Patra 2021-03-08 8:03 ` Atish Patra 2021-03-08 8:03 ` Atish Patra 2021-03-08 10:55 ` Anup Patel 2021-03-08 10:55 ` Anup Patel 2021-03-09 11:33 ` Heinrich Schuchardt 2021-03-09 11:33 ` Heinrich Schuchardt 2021-03-09 19:28 ` Atish Patra 2021-03-09 19:28 ` Atish Patra 2021-03-10 3:23 ` Palmer Dabbelt [this message] 2021-03-10 3:23 ` Palmer Dabbelt
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