From: Palmer Dabbelt <palmer@dabbelt.com> To: robh@kernel.org Cc: Christoph Hellwig <hch@lst.de>, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, mark.rutland@arm.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, shorne@gmail.com Subject: Re: [PATCH 6/6] dt-bindings: interrupt-controller: RISC-V PLIC documentation Date: Fri, 03 Aug 2018 18:48:43 -0700 (PDT) [thread overview] Message-ID: <mhng-6ecc7259-6cd2-4649-a0b5-be7c79176657@palmer-si-x1c4> (raw) In-Reply-To: <CAL_JsqJWOXX7-_sb4W63wPRqFjHuU-DM-LNYgczieWjAE5ABfQ@mail.gmail.com> On Wed, 01 Aug 2018 11:26:31 PDT (-0700), robh@kernel.org wrote: > On Wed, Aug 1, 2018 at 1:12 AM Christoph Hellwig <hch@lst.de> wrote: >> >> On Tue, Jul 31, 2018 at 04:46:30PM -0600, Rob Herring wrote: >> > Perhaps this should be 'sifive,plic0' >> >> Excepet for the fact this the old name has already been in shipping >> hardware and release of qemu and other emulators it should. > > Not really my problem that they didn't follow the process and upstream > their binding first. But this alone is just a string identifier, so I > don't really care that much. If things are really a mess, then the > next implementations will have to have better compatible strings. More > likely, I'll just see folks trying to add various properties to deal > with all the differences. > > You could always define a better compatible and leave 'riscv,plic0' as > a fallback to avoid breaking things. Ya, sorry about that. FWIW, we don't consider any of the bindings stable until they're actually accepted upstream, so it's on us to fix our bootloaders to match what actually lands upstream. Luckily there's not that much hardware out there and none of it is in production, so I'm OK forcing people to upgrade bootloaders to make this all work. I think it's probably best to leave the extra compat string out of the kernel proper, as then it'll never be enshrined as a RISC-V standard. >> > Normally this would have an SoC specific compatible too. Sometimes we >> > can get away without, but it doesn't seem like the PLIC is very tightly >> > specified nor has common implementations. >> >> It is a giant f***cking mess to be honest. Adding a highlevel spec >> to the ISA but not a register layout is completely idotic, but if you >> look at the current riscv-sw list this decision is still defended by >> SiFive / the RISC-V foundation. The whole stale of the RISC-V platform >> Ecosystem is rather pathetic unfortunately, and people don't seem to >> be willing to learn from past good practice nor mistakes in ARM land. > > Interrupt controllers are where the differentiation is. ;) Again, sorry about that :). The RISC-V platform specification really should have started a year ago, but I'm afraid there's just a bit too much going on on my end. If it helps any, we just submitted a plumbers dev room with one topic being the RISC-V platform spec, so I guess I'm in official trouble now it there isn't at least something to talk about by November...
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From: palmer@dabbelt.com (Palmer Dabbelt) To: linux-riscv@lists.infradead.org Subject: [PATCH 6/6] dt-bindings: interrupt-controller: RISC-V PLIC documentation Date: Fri, 03 Aug 2018 18:48:43 -0700 (PDT) [thread overview] Message-ID: <mhng-6ecc7259-6cd2-4649-a0b5-be7c79176657@palmer-si-x1c4> (raw) In-Reply-To: <CAL_JsqJWOXX7-_sb4W63wPRqFjHuU-DM-LNYgczieWjAE5ABfQ@mail.gmail.com> On Wed, 01 Aug 2018 11:26:31 PDT (-0700), robh at kernel.org wrote: > On Wed, Aug 1, 2018 at 1:12 AM Christoph Hellwig <hch@lst.de> wrote: >> >> On Tue, Jul 31, 2018 at 04:46:30PM -0600, Rob Herring wrote: >> > Perhaps this should be 'sifive,plic0' >> >> Excepet for the fact this the old name has already been in shipping >> hardware and release of qemu and other emulators it should. > > Not really my problem that they didn't follow the process and upstream > their binding first. But this alone is just a string identifier, so I > don't really care that much. If things are really a mess, then the > next implementations will have to have better compatible strings. More > likely, I'll just see folks trying to add various properties to deal > with all the differences. > > You could always define a better compatible and leave 'riscv,plic0' as > a fallback to avoid breaking things. Ya, sorry about that. FWIW, we don't consider any of the bindings stable until they're actually accepted upstream, so it's on us to fix our bootloaders to match what actually lands upstream. Luckily there's not that much hardware out there and none of it is in production, so I'm OK forcing people to upgrade bootloaders to make this all work. I think it's probably best to leave the extra compat string out of the kernel proper, as then it'll never be enshrined as a RISC-V standard. >> > Normally this would have an SoC specific compatible too. Sometimes we >> > can get away without, but it doesn't seem like the PLIC is very tightly >> > specified nor has common implementations. >> >> It is a giant f***cking mess to be honest. Adding a highlevel spec >> to the ISA but not a register layout is completely idotic, but if you >> look at the current riscv-sw list this decision is still defended by >> SiFive / the RISC-V foundation. The whole stale of the RISC-V platform >> Ecosystem is rather pathetic unfortunately, and people don't seem to >> be willing to learn from past good practice nor mistakes in ARM land. > > Interrupt controllers are where the differentiation is. ;) Again, sorry about that :). The RISC-V platform specification really should have started a year ago, but I'm afraid there's just a bit too much going on on my end. If it helps any, we just submitted a plumbers dev room with one topic being the RISC-V platform spec, so I guess I'm in official trouble now it there isn't at least something to talk about by November...
next prev parent reply other threads:[~2018-08-04 1:48 UTC|newest] Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-07-25 9:36 RISC-V irqchip drivers Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` [PATCH 1/6] RISC-V: simplify software interrupt / IPI code Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 21:44 ` Palmer Dabbelt 2018-07-25 21:44 ` Palmer Dabbelt 2018-07-26 8:10 ` Christoph Hellwig 2018-07-26 8:10 ` Christoph Hellwig 2018-07-25 9:36 ` [PATCH 2/6] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 21:44 ` Palmer Dabbelt 2018-07-25 21:44 ` Palmer Dabbelt 2018-07-25 9:36 ` [PATCH 3/6] irqchip: RISC-V Local Interrupt Controller Driver Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 11:18 ` Marc Zyngier 2018-07-25 11:18 ` Marc Zyngier 2018-07-25 11:24 ` Christoph Hellwig 2018-07-25 11:24 ` Christoph Hellwig 2018-07-25 11:37 ` Marc Zyngier 2018-07-25 11:37 ` Marc Zyngier 2018-07-25 17:54 ` Atish Patra 2018-07-25 17:54 ` Atish Patra 2018-07-26 3:38 ` Anup Patel 2018-07-26 3:38 ` Anup Patel 2018-07-26 8:27 ` Christoph Hellwig 2018-07-26 8:27 ` Christoph Hellwig 2018-07-26 13:39 ` Anup Patel 2018-07-26 13:39 ` Anup Patel 2018-08-01 18:55 ` Thomas Gleixner 2018-08-01 18:55 ` Thomas Gleixner 2018-08-02 7:34 ` Christoph Hellwig 2018-08-02 7:34 ` Christoph Hellwig 2018-08-02 9:35 ` Thomas Gleixner 2018-08-02 9:35 ` Thomas Gleixner 2018-08-02 9:43 ` Christoph Hellwig 2018-08-02 9:43 ` Christoph Hellwig 2018-08-02 9:44 ` Thomas Gleixner 2018-08-02 9:44 ` Thomas Gleixner 2018-08-04 4:03 ` Palmer Dabbelt 2018-08-04 4:03 ` Palmer Dabbelt 2018-08-04 16:40 ` Thomas Gleixner 2018-08-04 16:40 ` Thomas Gleixner 2018-07-25 9:36 ` [PATCH 4/6] dt-bindings: interrupt-controller: RISC-V local interrupt controller docs Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-31 22:37 ` Rob Herring 2018-07-31 22:37 ` Rob Herring 2018-08-01 7:13 ` Christoph Hellwig 2018-08-01 7:13 ` Christoph Hellwig 2018-08-01 18:14 ` Rob Herring 2018-08-01 18:14 ` Rob Herring 2018-07-25 9:36 ` [PATCH 5/6] irqchip: New RISC-V PLIC Driver Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` [PATCH 6/6] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-25 9:36 ` Christoph Hellwig 2018-07-31 22:46 ` Rob Herring 2018-07-31 22:46 ` Rob Herring 2018-08-01 7:16 ` Christoph Hellwig 2018-08-01 7:16 ` Christoph Hellwig 2018-08-01 18:26 ` Rob Herring 2018-08-01 18:26 ` Rob Herring 2018-08-02 9:55 ` Christoph Hellwig 2018-08-02 9:55 ` Christoph Hellwig 2018-08-02 14:43 ` Rob Herring 2018-08-02 14:43 ` Rob Herring 2018-08-04 1:48 ` Palmer Dabbelt [this message] 2018-08-04 1:48 ` Palmer Dabbelt 2018-07-25 21:26 ` RISC-V irqchip drivers Palmer Dabbelt 2018-07-25 21:26 ` Palmer Dabbelt
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