From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Alistair Francis <Alistair.Francis@wdc.com>,
alistair23@gmail.com
Subject: Re: [PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR
Date: Mon, 17 Feb 2020 11:04:02 -0800 (PST) [thread overview]
Message-ID: <mhng-87b5e850-a81a-499e-888f-24e1331b0ba2@palmerdabbelt-glaptop1> (raw)
In-Reply-To: <b1650e8b542ebea1cf949dc2a66a4cfb46a2f49d.1580518859.git.alistair.francis@wdc.com>
On Fri, 31 Jan 2020 17:03:05 PST (-0800), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 3 +++
> target/riscv/cpu.h | 10 ++++++++++
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 17 +++++++++++++++++
> target/riscv/csr.c | 25 +++++++++++++++++++++++++
> target/riscv/op_helper.c | 4 ++++
> 6 files changed, 62 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 44ad768a84..b27066f6a7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -237,6 +237,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> #ifndef CONFIG_USER_ONLY
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
> +#ifdef TARGET_RISCV32
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
> +#endif
> if (riscv_has_ext(env, RVH)) {
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index a8534fdf2b..6f9c29322a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -127,6 +127,10 @@ struct CPURISCVState {
>
> target_ulong mip;
>
> +#ifdef TARGET_RISCV32
> + target_ulong mstatush;
> +#endif
> +
> uint32_t miclaim;
>
> target_ulong mie;
> @@ -164,6 +168,9 @@ struct CPURISCVState {
> target_ulong vscause;
> target_ulong vstval;
> target_ulong vsatp;
> +#ifdef TARGET_RISCV32
> + target_ulong vsstatush;
> +#endif
>
> target_ulong mtval2;
> target_ulong mtinst;
> @@ -176,6 +183,9 @@ struct CPURISCVState {
> target_ulong stval_hs;
> target_ulong satp_hs;
> target_ulong mstatus_hs;
> +#ifdef TARGET_RISCV32
> + target_ulong mstatush_hs;
> +#endif
>
> target_ulong scounteren;
> target_ulong mcounteren;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index a24654d137..049032f2ae 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -135,6 +135,9 @@
> #define CSR_MTVEC 0x305
> #define CSR_MCOUNTEREN 0x306
>
> +/* 32-bit only */
> +#define CSR_MSTATUSH 0x310
> +
> /* Legacy Counter Setup (priv v1.9.1) */
> /* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
> #define CSR_MUCOUNTEREN 0x320
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 10786a077b..e04545adf7 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -126,6 +126,11 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
> env->mstatus &= ~mstatus_mask;
> env->mstatus |= env->mstatus_hs;
>
> +#if defined(TARGET_RISCV32)
> + env->vsstatush = env->mstatush;
> + env->mstatush |= env->mstatush_hs;
> +#endif
> +
> env->vstvec = env->stvec;
> env->stvec = env->stvec_hs;
>
> @@ -149,6 +154,11 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
> env->mstatus &= ~mstatus_mask;
> env->mstatus |= env->vsstatus;
>
> +#if defined(TARGET_RISCV32)
> + env->mstatush_hs = env->mstatush;
> + env->mstatush |= env->vsstatush;
> +#endif
> +
> env->stvec_hs = env->stvec;
> env->stvec = env->vstvec;
>
> @@ -937,10 +947,17 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> if (riscv_cpu_virt_enabled(env)) {
> riscv_cpu_swap_hypervisor_regs(env);
> }
> +#ifdef TARGET_RISCV32
> + env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
> + riscv_cpu_virt_enabled(env));
> + env->mstatush = set_field(env->mstatush, MSTATUS_MTL,
> + riscv_cpu_force_hs_excep_enabled(env));
> +#else
> env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
> riscv_cpu_virt_enabled(env));
> env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
> riscv_cpu_force_hs_excep_enabled(env));
> +#endif
>
> mtval2 = env->guest_phys_fault_addr;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 2e6700bbeb..572a478e8c 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -371,6 +371,27 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
> return 0;
> }
>
> +#ifdef TARGET_RISCV32
> +static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->mstatush;
> + return 0;
> +}
> +
> +static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if ((val ^ env->mstatush) & (MSTATUS_MPV)) {
> + tlb_flush(env_cpu(env));
> + }
> +
> + val &= MSTATUS_MPV | MSTATUS_MTL;
> +
> + env->mstatush = val;
> +
> + return 0;
> +}
> +#endif
> +
> static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
> {
> *val = env->misa;
> @@ -1214,6 +1235,10 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTVEC] = { any, read_mtvec, write_mtvec },
> [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
>
> +#if defined(TARGET_RISCV32)
> + [CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
> +#endif
> +
> /* Legacy Counter Setup (priv v1.9.1) */
> [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren },
> [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 804936e9d5..dca68fa96e 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -153,7 +153,11 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> get_field(mstatus, MSTATUS_MPIE));
> mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> +#ifdef TARGET_RISCV32
> + env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0);
> +#else
> mstatus = set_field(mstatus, MSTATUS_MPV, 0);
> +#endif
> env->mstatus = mstatus;
> riscv_cpu_set_mode(env, prev_priv);
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
next prev parent reply other threads:[~2020-02-17 19:05 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-01 1:01 [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5 Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 01/35] target/riscv: Convert MIP CSR to target_ulong Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 02/35] target/riscv: Add the Hypervisor extension Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 04/35] target/riscv: Add support for the new execption numbers Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 06/35] target/riscv: Add the virtulisation mode Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 07/35] target/riscv: Add the force HS exception mode Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-10 21:46 ` Palmer Dabbelt
2020-02-01 1:01 ` [PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 09/35] target/riscv: Print priv and virt in disas log Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 13/35] target/riscv: Add Hypervisor machine " Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 14/35] target/riscv: Add virtual register swapping function Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 17/35] target/riscv: Extend the SIP " Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 21/35] target/riscv: Add hypvervisor trap support Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-12 20:03 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 22/35] target/riscv: Add Hypervisor trap return support Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 23/35] target/riscv: Add hfence instructions Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 24/35] target/riscv: Remove the hret instruction Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-13 18:31 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-13 18:39 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-13 18:44 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 28/35] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 29/35] target/riscv: Allow specifying MMU stage Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 30/35] target/riscv: Implement second stage MMU Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 31/35] target/riscv: Raise the new execptions when 2nd stage translation fails Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:03 ` [PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions Alistair Francis
2020-02-01 1:03 ` Alistair Francis
2020-02-01 1:03 ` [PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2020-02-01 1:03 ` Alistair Francis
2020-02-17 19:04 ` Palmer Dabbelt [this message]
2020-02-01 1:03 ` [PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2020-02-01 1:03 ` Alistair Francis
2020-02-01 1:03 ` [PATCH v2 35/35] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2020-02-01 1:03 ` Alistair Francis
2020-02-10 18:50 ` [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5 Palmer Dabbelt
2020-02-10 19:52 ` Alistair Francis
2020-02-10 19:52 ` Alistair Francis
2020-02-17 19:11 ` Palmer Dabbelt
2020-02-18 18:11 ` Alistair Francis
2020-02-18 18:11 ` Alistair Francis
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