From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Date: Fri, 31 Jan 2020 17:03:08 -0800 [thread overview]
Message-ID: <cf7a5eeb1933140143ef236ccd086eff12bcab44.1580518859.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1580518859.git.alistair.francis@wdc.com>
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
target/riscv/cpu_bits.h | 11 +++++++++++
target/riscv/cpu_helper.c | 4 ++--
target/riscv/op_helper.c | 2 +-
target/riscv/translate.c | 2 +-
4 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 049032f2ae..7f64ee1174 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -363,8 +363,19 @@
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
+#if defined(TARGET_RISCV64)
#define MSTATUS_MTL 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
+#elif defined(TARGET_RISCV32)
+#define MSTATUS_MTL 0x00000040
+#define MSTATUS_MPV 0x00000080
+#endif
+
+#ifdef TARGET_RISCV32
+# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV)
+#else
+# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV)
+#endif
#define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e04545adf7..b9e90dfd9a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -322,7 +322,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
mode = get_field(env->mstatus, MSTATUS_MPP);
if (riscv_has_ext(env, RVH) &&
- get_field(env->mstatus, MSTATUS_MPV)) {
+ MSTATUS_MPV_ISSET(env)) {
use_background = true;
}
}
@@ -720,7 +720,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
m_mode_two_stage = env->priv == PRV_M &&
access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV) &&
- get_field(env->mstatus, MSTATUS_MPV);
+ MSTATUS_MPV_ISSET(env);
hs_mode_two_stage = env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index dca68fa96e..8736f689c2 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
- target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV);
+ target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 240fd7c971..ae8818efb3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -752,7 +752,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
if (env->priv_ver == PRV_M &&
get_field(env->mstatus, MSTATUS_MPRV) &&
- get_field(env->mstatus, MSTATUS_MPV)) {
+ MSTATUS_MPV_ISSET(env)) {
ctx->virt_enabled = true;
} else if (env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
--
2.25.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Date: Fri, 31 Jan 2020 17:03:08 -0800 [thread overview]
Message-ID: <cf7a5eeb1933140143ef236ccd086eff12bcab44.1580518859.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1580518859.git.alistair.francis@wdc.com>
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
target/riscv/cpu_bits.h | 11 +++++++++++
target/riscv/cpu_helper.c | 4 ++--
target/riscv/op_helper.c | 2 +-
target/riscv/translate.c | 2 +-
4 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 049032f2ae..7f64ee1174 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -363,8 +363,19 @@
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
+#if defined(TARGET_RISCV64)
#define MSTATUS_MTL 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
+#elif defined(TARGET_RISCV32)
+#define MSTATUS_MTL 0x00000040
+#define MSTATUS_MPV 0x00000080
+#endif
+
+#ifdef TARGET_RISCV32
+# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV)
+#else
+# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV)
+#endif
#define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e04545adf7..b9e90dfd9a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -322,7 +322,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
mode = get_field(env->mstatus, MSTATUS_MPP);
if (riscv_has_ext(env, RVH) &&
- get_field(env->mstatus, MSTATUS_MPV)) {
+ MSTATUS_MPV_ISSET(env)) {
use_background = true;
}
}
@@ -720,7 +720,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
m_mode_two_stage = env->priv == PRV_M &&
access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV) &&
- get_field(env->mstatus, MSTATUS_MPV);
+ MSTATUS_MPV_ISSET(env);
hs_mode_two_stage = env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index dca68fa96e..8736f689c2 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
- target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV);
+ target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 240fd7c971..ae8818efb3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -752,7 +752,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
if (env->priv_ver == PRV_M &&
get_field(env->mstatus, MSTATUS_MPRV) &&
- get_field(env->mstatus, MSTATUS_MPV)) {
+ MSTATUS_MPV_ISSET(env)) {
ctx->virt_enabled = true;
} else if (env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
--
2.25.0
next prev parent reply other threads:[~2020-02-01 1:21 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-01 1:01 [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5 Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 01/35] target/riscv: Convert MIP CSR to target_ulong Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 02/35] target/riscv: Add the Hypervisor extension Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 04/35] target/riscv: Add support for the new execption numbers Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 06/35] target/riscv: Add the virtulisation mode Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 07/35] target/riscv: Add the force HS exception mode Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-10 21:46 ` Palmer Dabbelt
2020-02-01 1:01 ` [PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:01 ` [PATCH v2 09/35] target/riscv: Print priv and virt in disas log Alistair Francis
2020-02-01 1:01 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 13/35] target/riscv: Add Hypervisor machine " Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 14/35] target/riscv: Add virtual register swapping function Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 17/35] target/riscv: Extend the SIP " Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 21/35] target/riscv: Add hypvervisor trap support Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-12 20:03 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 22/35] target/riscv: Add Hypervisor trap return support Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 23/35] target/riscv: Add hfence instructions Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 24/35] target/riscv: Remove the hret instruction Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-13 18:31 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-13 18:39 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-13 18:44 ` Palmer Dabbelt
2020-02-01 1:02 ` [PATCH v2 28/35] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 29/35] target/riscv: Allow specifying MMU stage Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 30/35] target/riscv: Implement second stage MMU Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:02 ` [PATCH v2 31/35] target/riscv: Raise the new execptions when 2nd stage translation fails Alistair Francis
2020-02-01 1:02 ` Alistair Francis
2020-02-01 1:03 ` [PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions Alistair Francis
2020-02-01 1:03 ` Alistair Francis
2020-02-01 1:03 ` [PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2020-02-01 1:03 ` Alistair Francis
2020-02-17 19:04 ` Palmer Dabbelt
2020-02-01 1:03 ` Alistair Francis [this message]
2020-02-01 1:03 ` [PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2020-02-01 1:03 ` [PATCH v2 35/35] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2020-02-01 1:03 ` Alistair Francis
2020-02-10 18:50 ` [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5 Palmer Dabbelt
2020-02-10 19:52 ` Alistair Francis
2020-02-10 19:52 ` Alistair Francis
2020-02-17 19:11 ` Palmer Dabbelt
2020-02-18 18:11 ` Alistair Francis
2020-02-18 18:11 ` Alistair Francis
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