* [PATCH v1 1/2] riscv: sifive_e: Manually define the machine
@ 2020-05-14 20:47 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-14 20:47 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 41 +++++++++++++++++++++++++++----------
include/hw/riscv/sifive_e.h | 4 ++++
2 files changed, 34 insertions(+), 11 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index b53109521e..472a98970b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -79,7 +79,7 @@ static void riscv_sifive_e_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
- SiFiveEState *s = g_new0(SiFiveEState, 1);
+ SiFiveEState *s = RISCV_E_MACHINE(machine);
MemoryRegion *sys_mem = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
int i;
@@ -115,6 +115,35 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static void sifive_e_machine_instance_init(Object *obj)
+{
+}
+
+static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V Board compatible with SiFive E SDK";
+ mc->init = riscv_sifive_e_init;
+ mc->max_cpus = 1;
+ mc->default_cpu_type = SIFIVE_E_CPU;
+}
+
+static const TypeInfo sifive_e_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("sifive_e"),
+ .parent = TYPE_MACHINE,
+ .class_init = sifive_e_machine_class_init,
+ .instance_init = sifive_e_machine_instance_init,
+ .instance_size = sizeof(SiFiveEState),
+};
+
+static void sifive_e_machine_init_register_types(void)
+{
+ type_register_static(&sifive_e_machine_typeinfo);
+}
+
+type_init(sifive_e_machine_init_register_types)
+
static void riscv_sifive_e_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -214,16 +243,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
&s->xip_mem);
}
-static void riscv_sifive_e_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Board compatible with SiFive E SDK";
- mc->init = riscv_sifive_e_init;
- mc->max_cpus = 1;
- mc->default_cpu_type = SIFIVE_E_CPU;
-}
-
-DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
-
static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 25ce7aa9d5..414992119e 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -47,6 +47,10 @@ typedef struct SiFiveEState {
SiFiveESoCState soc;
} SiFiveEState;
+#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
+#define RISCV_E_MACHINE(obj) \
+ OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
+
enum {
SIFIVE_E_DEBUG,
SIFIVE_E_MROM,
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 1/2] riscv: sifive_e: Manually define the machine
@ 2020-05-14 20:47 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-14 20:47 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 41 +++++++++++++++++++++++++++----------
include/hw/riscv/sifive_e.h | 4 ++++
2 files changed, 34 insertions(+), 11 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index b53109521e..472a98970b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -79,7 +79,7 @@ static void riscv_sifive_e_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
- SiFiveEState *s = g_new0(SiFiveEState, 1);
+ SiFiveEState *s = RISCV_E_MACHINE(machine);
MemoryRegion *sys_mem = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
int i;
@@ -115,6 +115,35 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static void sifive_e_machine_instance_init(Object *obj)
+{
+}
+
+static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V Board compatible with SiFive E SDK";
+ mc->init = riscv_sifive_e_init;
+ mc->max_cpus = 1;
+ mc->default_cpu_type = SIFIVE_E_CPU;
+}
+
+static const TypeInfo sifive_e_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("sifive_e"),
+ .parent = TYPE_MACHINE,
+ .class_init = sifive_e_machine_class_init,
+ .instance_init = sifive_e_machine_instance_init,
+ .instance_size = sizeof(SiFiveEState),
+};
+
+static void sifive_e_machine_init_register_types(void)
+{
+ type_register_static(&sifive_e_machine_typeinfo);
+}
+
+type_init(sifive_e_machine_init_register_types)
+
static void riscv_sifive_e_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -214,16 +243,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
&s->xip_mem);
}
-static void riscv_sifive_e_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Board compatible with SiFive E SDK";
- mc->init = riscv_sifive_e_init;
- mc->max_cpus = 1;
- mc->default_cpu_type = SIFIVE_E_CPU;
-}
-
-DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
-
static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 25ce7aa9d5..414992119e 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -47,6 +47,10 @@ typedef struct SiFiveEState {
SiFiveESoCState soc;
} SiFiveEState;
+#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
+#define RISCV_E_MACHINE(obj) \
+ OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
+
enum {
SIFIVE_E_DEBUG,
SIFIVE_E_MROM,
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 2/2] sifive_e: Support the revB machine
2020-05-14 20:47 ` Alistair Francis
@ 2020-05-14 20:47 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-14 20:47 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
include/hw/riscv/sifive_e.h | 1 +
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 472a98970b..cb7818341b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM reset vector */
- uint32_t reset_vec[2] = {
- 0x204002b7, /* 0x1000: lui t0,0x20400 */
- 0x00028067, /* 0x1004: jr t0 */
- };
+ uint32_t reset_vec[2];
+
+ if (s->revb) {
+ reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
+ } else {
+ reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
+ }
+ reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
@@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ return s->revb;
+}
+
+static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = value;
+}
+
static void sifive_e_machine_instance_init(Object *obj)
{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = false;
+ object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
+ sifive_e_machine_set_revb, NULL);
+ object_property_set_description(obj, "revb",
+ "Set on to tell QEMU that it should model "
+ "the revB HiFive1 board",
+ NULL);
}
static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 414992119e..0d3cd07fcc 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -45,6 +45,7 @@ typedef struct SiFiveEState {
/*< public >*/
SiFiveESoCState soc;
+ bool revb;
} SiFiveEState;
#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 2/2] sifive_e: Support the revB machine
@ 2020-05-14 20:47 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-14 20:47 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
include/hw/riscv/sifive_e.h | 1 +
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 472a98970b..cb7818341b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM reset vector */
- uint32_t reset_vec[2] = {
- 0x204002b7, /* 0x1000: lui t0,0x20400 */
- 0x00028067, /* 0x1004: jr t0 */
- };
+ uint32_t reset_vec[2];
+
+ if (s->revb) {
+ reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
+ } else {
+ reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
+ }
+ reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
@@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ return s->revb;
+}
+
+static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = value;
+}
+
static void sifive_e_machine_instance_init(Object *obj)
{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = false;
+ object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
+ sifive_e_machine_set_revb, NULL);
+ object_property_set_description(obj, "revb",
+ "Set on to tell QEMU that it should model "
+ "the revB HiFive1 board",
+ NULL);
}
static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 414992119e..0d3cd07fcc 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -45,6 +45,7 @@ typedef struct SiFiveEState {
/*< public >*/
SiFiveESoCState soc;
+ bool revb;
} SiFiveEState;
#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v1 1/2] riscv: sifive_e: Manually define the machine
2020-05-14 20:47 ` Alistair Francis
@ 2020-05-20 23:08 ` Palmer Dabbelt
-1 siblings, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2020-05-20 23:08 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, qemu-riscv, qemu-devel, alistair23
On Thu, 14 May 2020 13:47:07 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_e.c | 41 +++++++++++++++++++++++++++----------
> include/hw/riscv/sifive_e.h | 4 ++++
> 2 files changed, 34 insertions(+), 11 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index b53109521e..472a98970b 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -79,7 +79,7 @@ static void riscv_sifive_e_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
>
> - SiFiveEState *s = g_new0(SiFiveEState, 1);
> + SiFiveEState *s = RISCV_E_MACHINE(machine);
> MemoryRegion *sys_mem = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> int i;
> @@ -115,6 +115,35 @@ static void riscv_sifive_e_init(MachineState *machine)
> }
> }
>
> +static void sifive_e_machine_instance_init(Object *obj)
> +{
> +}
> +
> +static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> + mc->desc = "RISC-V Board compatible with SiFive E SDK";
> + mc->init = riscv_sifive_e_init;
> + mc->max_cpus = 1;
> + mc->default_cpu_type = SIFIVE_E_CPU;
> +}
> +
> +static const TypeInfo sifive_e_machine_typeinfo = {
> + .name = MACHINE_TYPE_NAME("sifive_e"),
> + .parent = TYPE_MACHINE,
> + .class_init = sifive_e_machine_class_init,
> + .instance_init = sifive_e_machine_instance_init,
> + .instance_size = sizeof(SiFiveEState),
> +};
> +
> +static void sifive_e_machine_init_register_types(void)
> +{
> + type_register_static(&sifive_e_machine_typeinfo);
> +}
> +
> +type_init(sifive_e_machine_init_register_types)
> +
> static void riscv_sifive_e_soc_init(Object *obj)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> @@ -214,16 +243,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> &s->xip_mem);
> }
>
> -static void riscv_sifive_e_machine_init(MachineClass *mc)
> -{
> - mc->desc = "RISC-V Board compatible with SiFive E SDK";
> - mc->init = riscv_sifive_e_init;
> - mc->max_cpus = 1;
> - mc->default_cpu_type = SIFIVE_E_CPU;
> -}
> -
> -DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
> -
> static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 25ce7aa9d5..414992119e 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -47,6 +47,10 @@ typedef struct SiFiveEState {
> SiFiveESoCState soc;
> } SiFiveEState;
>
> +#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
> +#define RISCV_E_MACHINE(obj) \
> + OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
> +
> enum {
> SIFIVE_E_DEBUG,
> SIFIVE_E_MROM,
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 1/2] riscv: sifive_e: Manually define the machine
@ 2020-05-20 23:08 ` Palmer Dabbelt
0 siblings, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2020-05-20 23:08 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, qemu-riscv, Alistair Francis, alistair23
On Thu, 14 May 2020 13:47:07 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_e.c | 41 +++++++++++++++++++++++++++----------
> include/hw/riscv/sifive_e.h | 4 ++++
> 2 files changed, 34 insertions(+), 11 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index b53109521e..472a98970b 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -79,7 +79,7 @@ static void riscv_sifive_e_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
>
> - SiFiveEState *s = g_new0(SiFiveEState, 1);
> + SiFiveEState *s = RISCV_E_MACHINE(machine);
> MemoryRegion *sys_mem = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> int i;
> @@ -115,6 +115,35 @@ static void riscv_sifive_e_init(MachineState *machine)
> }
> }
>
> +static void sifive_e_machine_instance_init(Object *obj)
> +{
> +}
> +
> +static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> + mc->desc = "RISC-V Board compatible with SiFive E SDK";
> + mc->init = riscv_sifive_e_init;
> + mc->max_cpus = 1;
> + mc->default_cpu_type = SIFIVE_E_CPU;
> +}
> +
> +static const TypeInfo sifive_e_machine_typeinfo = {
> + .name = MACHINE_TYPE_NAME("sifive_e"),
> + .parent = TYPE_MACHINE,
> + .class_init = sifive_e_machine_class_init,
> + .instance_init = sifive_e_machine_instance_init,
> + .instance_size = sizeof(SiFiveEState),
> +};
> +
> +static void sifive_e_machine_init_register_types(void)
> +{
> + type_register_static(&sifive_e_machine_typeinfo);
> +}
> +
> +type_init(sifive_e_machine_init_register_types)
> +
> static void riscv_sifive_e_soc_init(Object *obj)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> @@ -214,16 +243,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> &s->xip_mem);
> }
>
> -static void riscv_sifive_e_machine_init(MachineClass *mc)
> -{
> - mc->desc = "RISC-V Board compatible with SiFive E SDK";
> - mc->init = riscv_sifive_e_init;
> - mc->max_cpus = 1;
> - mc->default_cpu_type = SIFIVE_E_CPU;
> -}
> -
> -DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
> -
> static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 25ce7aa9d5..414992119e 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -47,6 +47,10 @@ typedef struct SiFiveEState {
> SiFiveESoCState soc;
> } SiFiveEState;
>
> +#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
> +#define RISCV_E_MACHINE(obj) \
> + OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
> +
> enum {
> SIFIVE_E_DEBUG,
> SIFIVE_E_MROM,
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
2020-05-14 20:47 ` Alistair Francis
@ 2020-05-20 23:08 ` Palmer Dabbelt
-1 siblings, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2020-05-20 23:08 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, qemu-riscv, qemu-devel, alistair23
On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> include/hw/riscv/sifive_e.h | 1 +
> 2 files changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 472a98970b..cb7818341b 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> memmap[SIFIVE_E_DTIM].base, main_mem);
>
> /* Mask ROM reset vector */
> - uint32_t reset_vec[2] = {
> - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> - 0x00028067, /* 0x1004: jr t0 */
> - };
> + uint32_t reset_vec[2];
> +
> + if (s->revb) {
> + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> + } else {
> + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> + }
> + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
>
> /* copy in the reset vector in little_endian byte order */
> for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> }
> }
>
> +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> +{
> + SiFiveEState *s = RISCV_E_MACHINE(obj);
> +
> + return s->revb;
> +}
> +
> +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> +{
> + SiFiveEState *s = RISCV_E_MACHINE(obj);
> +
> + s->revb = value;
> +}
> +
> static void sifive_e_machine_instance_init(Object *obj)
> {
> + SiFiveEState *s = RISCV_E_MACHINE(obj);
> +
> + s->revb = false;
> + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> + sifive_e_machine_set_revb, NULL);
> + object_property_set_description(obj, "revb",
> + "Set on to tell QEMU that it should model "
> + "the revB HiFive1 board",
> + NULL);
> }
>
> static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 414992119e..0d3cd07fcc 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
>
> /*< public >*/
> SiFiveESoCState soc;
> + bool revb;
> } SiFiveEState;
>
> #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
IIRC there are way more differences between the un-suffixed FE310 and the Rev
B, specifically the interrupt map is all different.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
@ 2020-05-20 23:08 ` Palmer Dabbelt
0 siblings, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2020-05-20 23:08 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, qemu-riscv, Alistair Francis, alistair23
On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> include/hw/riscv/sifive_e.h | 1 +
> 2 files changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 472a98970b..cb7818341b 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> memmap[SIFIVE_E_DTIM].base, main_mem);
>
> /* Mask ROM reset vector */
> - uint32_t reset_vec[2] = {
> - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> - 0x00028067, /* 0x1004: jr t0 */
> - };
> + uint32_t reset_vec[2];
> +
> + if (s->revb) {
> + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> + } else {
> + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> + }
> + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
>
> /* copy in the reset vector in little_endian byte order */
> for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> }
> }
>
> +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> +{
> + SiFiveEState *s = RISCV_E_MACHINE(obj);
> +
> + return s->revb;
> +}
> +
> +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> +{
> + SiFiveEState *s = RISCV_E_MACHINE(obj);
> +
> + s->revb = value;
> +}
> +
> static void sifive_e_machine_instance_init(Object *obj)
> {
> + SiFiveEState *s = RISCV_E_MACHINE(obj);
> +
> + s->revb = false;
> + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> + sifive_e_machine_set_revb, NULL);
> + object_property_set_description(obj, "revb",
> + "Set on to tell QEMU that it should model "
> + "the revB HiFive1 board",
> + NULL);
> }
>
> static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 414992119e..0d3cd07fcc 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
>
> /*< public >*/
> SiFiveESoCState soc;
> + bool revb;
> } SiFiveEState;
>
> #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
IIRC there are way more differences between the un-suffixed FE310 and the Rev
B, specifically the interrupt map is all different.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
2020-05-20 23:08 ` Palmer Dabbelt
@ 2020-05-21 15:57 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-21 15:57 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers
On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> > include/hw/riscv/sifive_e.h | 1 +
> > 2 files changed, 32 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > index 472a98970b..cb7818341b 100644
> > --- a/hw/riscv/sifive_e.c
> > +++ b/hw/riscv/sifive_e.c
> > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> > memmap[SIFIVE_E_DTIM].base, main_mem);
> >
> > /* Mask ROM reset vector */
> > - uint32_t reset_vec[2] = {
> > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> > - 0x00028067, /* 0x1004: jr t0 */
> > - };
> > + uint32_t reset_vec[2];
> > +
> > + if (s->revb) {
> > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> > + } else {
> > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> > + }
> > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
> >
> > /* copy in the reset vector in little_endian byte order */
> > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> > }
> > }
> >
> > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> > +{
> > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > +
> > + return s->revb;
> > +}
> > +
> > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> > +{
> > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > +
> > + s->revb = value;
> > +}
> > +
> > static void sifive_e_machine_instance_init(Object *obj)
> > {
> > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > +
> > + s->revb = false;
> > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> > + sifive_e_machine_set_revb, NULL);
> > + object_property_set_description(obj, "revb",
> > + "Set on to tell QEMU that it should model "
> > + "the revB HiFive1 board",
> > + NULL);
> > }
> >
> > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> > index 414992119e..0d3cd07fcc 100644
> > --- a/include/hw/riscv/sifive_e.h
> > +++ b/include/hw/riscv/sifive_e.h
> > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
> >
> > /*< public >*/
> > SiFiveESoCState soc;
> > + bool revb;
> > } SiFiveEState;
> >
> > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
>
> IIRC there are way more differences between the un-suffixed FE310 and the Rev
> B, specifically the interrupt map is all different.
The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
all seem to be the same.
Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
@ 2020-05-21 15:57 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-21 15:57 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V
On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> > include/hw/riscv/sifive_e.h | 1 +
> > 2 files changed, 32 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > index 472a98970b..cb7818341b 100644
> > --- a/hw/riscv/sifive_e.c
> > +++ b/hw/riscv/sifive_e.c
> > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> > memmap[SIFIVE_E_DTIM].base, main_mem);
> >
> > /* Mask ROM reset vector */
> > - uint32_t reset_vec[2] = {
> > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> > - 0x00028067, /* 0x1004: jr t0 */
> > - };
> > + uint32_t reset_vec[2];
> > +
> > + if (s->revb) {
> > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> > + } else {
> > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> > + }
> > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
> >
> > /* copy in the reset vector in little_endian byte order */
> > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> > }
> > }
> >
> > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> > +{
> > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > +
> > + return s->revb;
> > +}
> > +
> > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> > +{
> > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > +
> > + s->revb = value;
> > +}
> > +
> > static void sifive_e_machine_instance_init(Object *obj)
> > {
> > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > +
> > + s->revb = false;
> > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> > + sifive_e_machine_set_revb, NULL);
> > + object_property_set_description(obj, "revb",
> > + "Set on to tell QEMU that it should model "
> > + "the revB HiFive1 board",
> > + NULL);
> > }
> >
> > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> > index 414992119e..0d3cd07fcc 100644
> > --- a/include/hw/riscv/sifive_e.h
> > +++ b/include/hw/riscv/sifive_e.h
> > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
> >
> > /*< public >*/
> > SiFiveESoCState soc;
> > + bool revb;
> > } SiFiveEState;
> >
> > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
>
> IIRC there are way more differences between the un-suffixed FE310 and the Rev
> B, specifically the interrupt map is all different.
The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
all seem to be the same.
Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
2020-05-21 15:57 ` Alistair Francis
@ 2020-05-28 18:13 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 18:13 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers
On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> >
> > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > ---
> > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> > > include/hw/riscv/sifive_e.h | 1 +
> > > 2 files changed, 32 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > > index 472a98970b..cb7818341b 100644
> > > --- a/hw/riscv/sifive_e.c
> > > +++ b/hw/riscv/sifive_e.c
> > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> > > memmap[SIFIVE_E_DTIM].base, main_mem);
> > >
> > > /* Mask ROM reset vector */
> > > - uint32_t reset_vec[2] = {
> > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> > > - 0x00028067, /* 0x1004: jr t0 */
> > > - };
> > > + uint32_t reset_vec[2];
> > > +
> > > + if (s->revb) {
> > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> > > + } else {
> > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> > > + }
> > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
> > >
> > > /* copy in the reset vector in little_endian byte order */
> > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> > > }
> > > }
> > >
> > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> > > +{
> > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > +
> > > + return s->revb;
> > > +}
> > > +
> > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> > > +{
> > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > +
> > > + s->revb = value;
> > > +}
> > > +
> > > static void sifive_e_machine_instance_init(Object *obj)
> > > {
> > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > +
> > > + s->revb = false;
> > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> > > + sifive_e_machine_set_revb, NULL);
> > > + object_property_set_description(obj, "revb",
> > > + "Set on to tell QEMU that it should model "
> > > + "the revB HiFive1 board",
> > > + NULL);
> > > }
> > >
> > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> > > index 414992119e..0d3cd07fcc 100644
> > > --- a/include/hw/riscv/sifive_e.h
> > > +++ b/include/hw/riscv/sifive_e.h
> > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
> > >
> > > /*< public >*/
> > > SiFiveESoCState soc;
> > > + bool revb;
> > > } SiFiveEState;
> > >
> > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
> >
> > IIRC there are way more differences between the un-suffixed FE310 and the Rev
> > B, specifically the interrupt map is all different.
>
> The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
> all seem to be the same.
Ping!
>
> Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
@ 2020-05-28 18:13 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 18:13 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V
On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> >
> > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > ---
> > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> > > include/hw/riscv/sifive_e.h | 1 +
> > > 2 files changed, 32 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > > index 472a98970b..cb7818341b 100644
> > > --- a/hw/riscv/sifive_e.c
> > > +++ b/hw/riscv/sifive_e.c
> > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> > > memmap[SIFIVE_E_DTIM].base, main_mem);
> > >
> > > /* Mask ROM reset vector */
> > > - uint32_t reset_vec[2] = {
> > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> > > - 0x00028067, /* 0x1004: jr t0 */
> > > - };
> > > + uint32_t reset_vec[2];
> > > +
> > > + if (s->revb) {
> > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> > > + } else {
> > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> > > + }
> > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
> > >
> > > /* copy in the reset vector in little_endian byte order */
> > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> > > }
> > > }
> > >
> > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> > > +{
> > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > +
> > > + return s->revb;
> > > +}
> > > +
> > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> > > +{
> > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > +
> > > + s->revb = value;
> > > +}
> > > +
> > > static void sifive_e_machine_instance_init(Object *obj)
> > > {
> > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > +
> > > + s->revb = false;
> > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> > > + sifive_e_machine_set_revb, NULL);
> > > + object_property_set_description(obj, "revb",
> > > + "Set on to tell QEMU that it should model "
> > > + "the revB HiFive1 board",
> > > + NULL);
> > > }
> > >
> > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> > > index 414992119e..0d3cd07fcc 100644
> > > --- a/include/hw/riscv/sifive_e.h
> > > +++ b/include/hw/riscv/sifive_e.h
> > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
> > >
> > > /*< public >*/
> > > SiFiveESoCState soc;
> > > + bool revb;
> > > } SiFiveEState;
> > >
> > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
> >
> > IIRC there are way more differences between the un-suffixed FE310 and the Rev
> > B, specifically the interrupt map is all different.
>
> The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
> all seem to be the same.
Ping!
>
> Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
2020-05-28 18:13 ` Alistair Francis
@ 2020-06-10 22:13 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-06-10 22:13 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers
On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> > >
> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > > ---
> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> > > > include/hw/riscv/sifive_e.h | 1 +
> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > > > index 472a98970b..cb7818341b 100644
> > > > --- a/hw/riscv/sifive_e.c
> > > > +++ b/hw/riscv/sifive_e.c
> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
> > > >
> > > > /* Mask ROM reset vector */
> > > > - uint32_t reset_vec[2] = {
> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> > > > - 0x00028067, /* 0x1004: jr t0 */
> > > > - };
> > > > + uint32_t reset_vec[2];
> > > > +
> > > > + if (s->revb) {
> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> > > > + } else {
> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> > > > + }
> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
> > > >
> > > > /* copy in the reset vector in little_endian byte order */
> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> > > > }
> > > > }
> > > >
> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> > > > +{
> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > > +
> > > > + return s->revb;
> > > > +}
> > > > +
> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> > > > +{
> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > > +
> > > > + s->revb = value;
> > > > +}
> > > > +
> > > > static void sifive_e_machine_instance_init(Object *obj)
> > > > {
> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > > +
> > > > + s->revb = false;
> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> > > > + sifive_e_machine_set_revb, NULL);
> > > > + object_property_set_description(obj, "revb",
> > > > + "Set on to tell QEMU that it should model "
> > > > + "the revB HiFive1 board",
> > > > + NULL);
> > > > }
> > > >
> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> > > > index 414992119e..0d3cd07fcc 100644
> > > > --- a/include/hw/riscv/sifive_e.h
> > > > +++ b/include/hw/riscv/sifive_e.h
> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
> > > >
> > > > /*< public >*/
> > > > SiFiveESoCState soc;
> > > > + bool revb;
> > > > } SiFiveEState;
> > > >
> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
> > >
> > > IIRC there are way more differences between the un-suffixed FE310 and the Rev
> > > B, specifically the interrupt map is all different.
> >
> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
> > all seem to be the same.
>
> Ping!
Ping^2
Applying to RISC-V tree.
Alistair
>
> >
> > Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
@ 2020-06-10 22:13 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-06-10 22:13 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V
On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> > >
> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > > ---
> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> > > > include/hw/riscv/sifive_e.h | 1 +
> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > > > index 472a98970b..cb7818341b 100644
> > > > --- a/hw/riscv/sifive_e.c
> > > > +++ b/hw/riscv/sifive_e.c
> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
> > > >
> > > > /* Mask ROM reset vector */
> > > > - uint32_t reset_vec[2] = {
> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> > > > - 0x00028067, /* 0x1004: jr t0 */
> > > > - };
> > > > + uint32_t reset_vec[2];
> > > > +
> > > > + if (s->revb) {
> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> > > > + } else {
> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> > > > + }
> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
> > > >
> > > > /* copy in the reset vector in little_endian byte order */
> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> > > > }
> > > > }
> > > >
> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> > > > +{
> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > > +
> > > > + return s->revb;
> > > > +}
> > > > +
> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> > > > +{
> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > > +
> > > > + s->revb = value;
> > > > +}
> > > > +
> > > > static void sifive_e_machine_instance_init(Object *obj)
> > > > {
> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> > > > +
> > > > + s->revb = false;
> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> > > > + sifive_e_machine_set_revb, NULL);
> > > > + object_property_set_description(obj, "revb",
> > > > + "Set on to tell QEMU that it should model "
> > > > + "the revB HiFive1 board",
> > > > + NULL);
> > > > }
> > > >
> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> > > > index 414992119e..0d3cd07fcc 100644
> > > > --- a/include/hw/riscv/sifive_e.h
> > > > +++ b/include/hw/riscv/sifive_e.h
> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
> > > >
> > > > /*< public >*/
> > > > SiFiveESoCState soc;
> > > > + bool revb;
> > > > } SiFiveEState;
> > > >
> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
> > >
> > > IIRC there are way more differences between the un-suffixed FE310 and the Rev
> > > B, specifically the interrupt map is all different.
> >
> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
> > all seem to be the same.
>
> Ping!
Ping^2
Applying to RISC-V tree.
Alistair
>
> >
> > Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
2020-06-10 22:13 ` Alistair Francis
@ 2020-06-18 22:42 ` Palmer Dabbelt
-1 siblings, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2020-06-18 22:42 UTC (permalink / raw)
To: alistair23; +Cc: qemu-riscv, Alistair Francis, qemu-devel
On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistair23@gmail.com wrote:
> On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
>> >
>> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> > >
>> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
>> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> > > > ---
>> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
>> > > > include/hw/riscv/sifive_e.h | 1 +
>> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
>> > > >
>> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
>> > > > index 472a98970b..cb7818341b 100644
>> > > > --- a/hw/riscv/sifive_e.c
>> > > > +++ b/hw/riscv/sifive_e.c
>> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
>> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
>> > > >
>> > > > /* Mask ROM reset vector */
>> > > > - uint32_t reset_vec[2] = {
>> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
>> > > > - 0x00028067, /* 0x1004: jr t0 */
>> > > > - };
>> > > > + uint32_t reset_vec[2];
>> > > > +
>> > > > + if (s->revb) {
>> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
>> > > > + } else {
>> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
>> > > > + }
>> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
>> > > >
>> > > > /* copy in the reset vector in little_endian byte order */
>> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
>> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
>> > > > }
>> > > > }
>> > > >
>> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
>> > > > +{
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + return s->revb;
>> > > > +}
>> > > > +
>> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
>> > > > +{
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + s->revb = value;
>> > > > +}
>> > > > +
>> > > > static void sifive_e_machine_instance_init(Object *obj)
>> > > > {
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + s->revb = false;
>> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
>> > > > + sifive_e_machine_set_revb, NULL);
>> > > > + object_property_set_description(obj, "revb",
>> > > > + "Set on to tell QEMU that it should model "
>> > > > + "the revB HiFive1 board",
>> > > > + NULL);
>> > > > }
>> > > >
>> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
>> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
>> > > > index 414992119e..0d3cd07fcc 100644
>> > > > --- a/include/hw/riscv/sifive_e.h
>> > > > +++ b/include/hw/riscv/sifive_e.h
>> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
>> > > >
>> > > > /*< public >*/
>> > > > SiFiveESoCState soc;
>> > > > + bool revb;
>> > > > } SiFiveEState;
>> > > >
>> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
>> > >
>> > > IIRC there are way more differences between the un-suffixed FE310 and the Rev
>> > > B, specifically the interrupt map is all different.
>> >
>> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
>> > all seem to be the same.
>>
>> Ping!
>
> Ping^2
>
> Applying to RISC-V tree.
They're not: uart0 is interrupt 3 on the rev b but 5 on the non-rev b (which
they don't call rev a but I'm going to :)). There's isn't even a uart1 in the
DTS on the rev a, and the GPIO interrupts are different as well.
The DTS files are in SiFive's SDK:
https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1-revb/core.dts
https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1/core.dts
which should also generate some test programs. When I was there we tested on
QEMU for the platforms that were supported, so there should be some support for
doing so still.
>
> Alistair
>
>>
>> >
>> > Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
@ 2020-06-18 22:42 ` Palmer Dabbelt
0 siblings, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2020-06-18 22:42 UTC (permalink / raw)
To: alistair23; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistair23@gmail.com wrote:
> On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
>> >
>> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> > >
>> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
>> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> > > > ---
>> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
>> > > > include/hw/riscv/sifive_e.h | 1 +
>> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
>> > > >
>> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
>> > > > index 472a98970b..cb7818341b 100644
>> > > > --- a/hw/riscv/sifive_e.c
>> > > > +++ b/hw/riscv/sifive_e.c
>> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
>> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
>> > > >
>> > > > /* Mask ROM reset vector */
>> > > > - uint32_t reset_vec[2] = {
>> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
>> > > > - 0x00028067, /* 0x1004: jr t0 */
>> > > > - };
>> > > > + uint32_t reset_vec[2];
>> > > > +
>> > > > + if (s->revb) {
>> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
>> > > > + } else {
>> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
>> > > > + }
>> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
>> > > >
>> > > > /* copy in the reset vector in little_endian byte order */
>> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
>> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
>> > > > }
>> > > > }
>> > > >
>> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
>> > > > +{
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + return s->revb;
>> > > > +}
>> > > > +
>> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
>> > > > +{
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + s->revb = value;
>> > > > +}
>> > > > +
>> > > > static void sifive_e_machine_instance_init(Object *obj)
>> > > > {
>> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> > > > +
>> > > > + s->revb = false;
>> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
>> > > > + sifive_e_machine_set_revb, NULL);
>> > > > + object_property_set_description(obj, "revb",
>> > > > + "Set on to tell QEMU that it should model "
>> > > > + "the revB HiFive1 board",
>> > > > + NULL);
>> > > > }
>> > > >
>> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
>> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
>> > > > index 414992119e..0d3cd07fcc 100644
>> > > > --- a/include/hw/riscv/sifive_e.h
>> > > > +++ b/include/hw/riscv/sifive_e.h
>> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
>> > > >
>> > > > /*< public >*/
>> > > > SiFiveESoCState soc;
>> > > > + bool revb;
>> > > > } SiFiveEState;
>> > > >
>> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
>> > >
>> > > IIRC there are way more differences between the un-suffixed FE310 and the Rev
>> > > B, specifically the interrupt map is all different.
>> >
>> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
>> > all seem to be the same.
>>
>> Ping!
>
> Ping^2
>
> Applying to RISC-V tree.
They're not: uart0 is interrupt 3 on the rev b but 5 on the non-rev b (which
they don't call rev a but I'm going to :)). There's isn't even a uart1 in the
DTS on the rev a, and the GPIO interrupts are different as well.
The DTS files are in SiFive's SDK:
https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1-revb/core.dts
https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1/core.dts
which should also generate some test programs. When I was there we tested on
QEMU for the platforms that were supported, so there should be some support for
doing so still.
>
> Alistair
>
>>
>> >
>> > Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
2020-06-18 22:42 ` Palmer Dabbelt
@ 2020-06-18 23:18 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-06-18 23:18 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers
On Thu, Jun 18, 2020 at 3:42 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistair23@gmail.com wrote:
> > On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistair23@gmail.com> wrote:
> >>
> >> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
> >> >
> >> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> >> > >
> >> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> >> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> > > > ---
> >> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> >> > > > include/hw/riscv/sifive_e.h | 1 +
> >> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
> >> > > >
> >> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> >> > > > index 472a98970b..cb7818341b 100644
> >> > > > --- a/hw/riscv/sifive_e.c
> >> > > > +++ b/hw/riscv/sifive_e.c
> >> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> >> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
> >> > > >
> >> > > > /* Mask ROM reset vector */
> >> > > > - uint32_t reset_vec[2] = {
> >> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> >> > > > - 0x00028067, /* 0x1004: jr t0 */
> >> > > > - };
> >> > > > + uint32_t reset_vec[2];
> >> > > > +
> >> > > > + if (s->revb) {
> >> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> >> > > > + } else {
> >> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> >> > > > + }
> >> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
> >> > > >
> >> > > > /* copy in the reset vector in little_endian byte order */
> >> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> >> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> >> > > > }
> >> > > > }
> >> > > >
> >> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> >> > > > +{
> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> >> > > > +
> >> > > > + return s->revb;
> >> > > > +}
> >> > > > +
> >> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> >> > > > +{
> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> >> > > > +
> >> > > > + s->revb = value;
> >> > > > +}
> >> > > > +
> >> > > > static void sifive_e_machine_instance_init(Object *obj)
> >> > > > {
> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> >> > > > +
> >> > > > + s->revb = false;
> >> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> >> > > > + sifive_e_machine_set_revb, NULL);
> >> > > > + object_property_set_description(obj, "revb",
> >> > > > + "Set on to tell QEMU that it should model "
> >> > > > + "the revB HiFive1 board",
> >> > > > + NULL);
> >> > > > }
> >> > > >
> >> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> >> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> >> > > > index 414992119e..0d3cd07fcc 100644
> >> > > > --- a/include/hw/riscv/sifive_e.h
> >> > > > +++ b/include/hw/riscv/sifive_e.h
> >> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
> >> > > >
> >> > > > /*< public >*/
> >> > > > SiFiveESoCState soc;
> >> > > > + bool revb;
> >> > > > } SiFiveEState;
> >> > > >
> >> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
> >> > >
> >> > > IIRC there are way more differences between the un-suffixed FE310 and the Rev
> >> > > B, specifically the interrupt map is all different.
> >> >
> >> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
> >> > all seem to be the same.
> >>
> >> Ping!
> >
> > Ping^2
> >
> > Applying to RISC-V tree.
>
> They're not: uart0 is interrupt 3 on the rev b but 5 on the non-rev b (which
> they don't call rev a but I'm going to :)). There's isn't even a uart1 in the
> DTS on the rev a, and the GPIO interrupts are different as well.
>
> The DTS files are in SiFive's SDK:
>
> https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1-revb/core.dts
> https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1/core.dts
>
> which should also generate some test programs. When I was there we tested on
> QEMU for the platforms that were supported, so there should be some support for
> doing so still.
I am reading the wrong data sheets?
For revB I looked at
https://sifive.cdn.prismic.io/sifive%2F9ecbb623-7c7f-4acc-966f-9bb10ecdb62e_fe310-g002.pdf,
page 46, table 26. The interrupts for the revB match what we currently
have in QEMU.
For revA https://sifive.cdn.prismic.io/sifive%2F500a69f8-af3a-4fd9-927f-10ca77077532_fe310-g000.pdf,
page 42, table 21 also matches what we have in QEMU.
To me it looks like both have two UARTs and both have the same
interrupt numbers.
The actual software I am running also hasn't changed UART interrupt
numbering between the two boards and UART interrupts are working
correctly.
Alistair
>
> >
> > Alistair
> >
> >>
> >> >
> >> > Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
@ 2020-06-18 23:18 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-06-18 23:18 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V
On Thu, Jun 18, 2020 at 3:42 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistair23@gmail.com wrote:
> > On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistair23@gmail.com> wrote:
> >>
> >> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
> >> >
> >> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> >> > >
> >> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
> >> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> > > > ---
> >> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
> >> > > > include/hw/riscv/sifive_e.h | 1 +
> >> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
> >> > > >
> >> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> >> > > > index 472a98970b..cb7818341b 100644
> >> > > > --- a/hw/riscv/sifive_e.c
> >> > > > +++ b/hw/riscv/sifive_e.c
> >> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
> >> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
> >> > > >
> >> > > > /* Mask ROM reset vector */
> >> > > > - uint32_t reset_vec[2] = {
> >> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> >> > > > - 0x00028067, /* 0x1004: jr t0 */
> >> > > > - };
> >> > > > + uint32_t reset_vec[2];
> >> > > > +
> >> > > > + if (s->revb) {
> >> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
> >> > > > + } else {
> >> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
> >> > > > + }
> >> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
> >> > > >
> >> > > > /* copy in the reset vector in little_endian byte order */
> >> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> >> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
> >> > > > }
> >> > > > }
> >> > > >
> >> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
> >> > > > +{
> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> >> > > > +
> >> > > > + return s->revb;
> >> > > > +}
> >> > > > +
> >> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
> >> > > > +{
> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> >> > > > +
> >> > > > + s->revb = value;
> >> > > > +}
> >> > > > +
> >> > > > static void sifive_e_machine_instance_init(Object *obj)
> >> > > > {
> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
> >> > > > +
> >> > > > + s->revb = false;
> >> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
> >> > > > + sifive_e_machine_set_revb, NULL);
> >> > > > + object_property_set_description(obj, "revb",
> >> > > > + "Set on to tell QEMU that it should model "
> >> > > > + "the revB HiFive1 board",
> >> > > > + NULL);
> >> > > > }
> >> > > >
> >> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> >> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> >> > > > index 414992119e..0d3cd07fcc 100644
> >> > > > --- a/include/hw/riscv/sifive_e.h
> >> > > > +++ b/include/hw/riscv/sifive_e.h
> >> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
> >> > > >
> >> > > > /*< public >*/
> >> > > > SiFiveESoCState soc;
> >> > > > + bool revb;
> >> > > > } SiFiveEState;
> >> > > >
> >> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
> >> > >
> >> > > IIRC there are way more differences between the un-suffixed FE310 and the Rev
> >> > > B, specifically the interrupt map is all different.
> >> >
> >> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
> >> > all seem to be the same.
> >>
> >> Ping!
> >
> > Ping^2
> >
> > Applying to RISC-V tree.
>
> They're not: uart0 is interrupt 3 on the rev b but 5 on the non-rev b (which
> they don't call rev a but I'm going to :)). There's isn't even a uart1 in the
> DTS on the rev a, and the GPIO interrupts are different as well.
>
> The DTS files are in SiFive's SDK:
>
> https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1-revb/core.dts
> https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1/core.dts
>
> which should also generate some test programs. When I was there we tested on
> QEMU for the platforms that were supported, so there should be some support for
> doing so still.
I am reading the wrong data sheets?
For revB I looked at
https://sifive.cdn.prismic.io/sifive%2F9ecbb623-7c7f-4acc-966f-9bb10ecdb62e_fe310-g002.pdf,
page 46, table 26. The interrupts for the revB match what we currently
have in QEMU.
For revA https://sifive.cdn.prismic.io/sifive%2F500a69f8-af3a-4fd9-927f-10ca77077532_fe310-g000.pdf,
page 42, table 21 also matches what we have in QEMU.
To me it looks like both have two UARTs and both have the same
interrupt numbers.
The actual software I am running also hasn't changed UART interrupt
numbering between the two boards and UART interrupts are working
correctly.
Alistair
>
> >
> > Alistair
> >
> >>
> >> >
> >> > Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
2020-06-18 23:18 ` Alistair Francis
@ 2020-06-19 3:42 ` Palmer Dabbelt
-1 siblings, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2020-06-19 3:42 UTC (permalink / raw)
To: alistair23; +Cc: qemu-riscv, Alistair Francis, qemu-devel
On Thu, 18 Jun 2020 16:18:20 PDT (-0700), alistair23@gmail.com wrote:
> On Thu, Jun 18, 2020 at 3:42 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistair23@gmail.com wrote:
>> > On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>> >>
>> >> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
>> >> >
>> >> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> >> > >
>> >> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
>> >> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> >> > > > ---
>> >> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
>> >> > > > include/hw/riscv/sifive_e.h | 1 +
>> >> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
>> >> > > >
>> >> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
>> >> > > > index 472a98970b..cb7818341b 100644
>> >> > > > --- a/hw/riscv/sifive_e.c
>> >> > > > +++ b/hw/riscv/sifive_e.c
>> >> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
>> >> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
>> >> > > >
>> >> > > > /* Mask ROM reset vector */
>> >> > > > - uint32_t reset_vec[2] = {
>> >> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
>> >> > > > - 0x00028067, /* 0x1004: jr t0 */
>> >> > > > - };
>> >> > > > + uint32_t reset_vec[2];
>> >> > > > +
>> >> > > > + if (s->revb) {
>> >> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
>> >> > > > + } else {
>> >> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
>> >> > > > + }
>> >> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
>> >> > > >
>> >> > > > /* copy in the reset vector in little_endian byte order */
>> >> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
>> >> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
>> >> > > > }
>> >> > > > }
>> >> > > >
>> >> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
>> >> > > > +{
>> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> >> > > > +
>> >> > > > + return s->revb;
>> >> > > > +}
>> >> > > > +
>> >> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
>> >> > > > +{
>> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> >> > > > +
>> >> > > > + s->revb = value;
>> >> > > > +}
>> >> > > > +
>> >> > > > static void sifive_e_machine_instance_init(Object *obj)
>> >> > > > {
>> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> >> > > > +
>> >> > > > + s->revb = false;
>> >> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
>> >> > > > + sifive_e_machine_set_revb, NULL);
>> >> > > > + object_property_set_description(obj, "revb",
>> >> > > > + "Set on to tell QEMU that it should model "
>> >> > > > + "the revB HiFive1 board",
>> >> > > > + NULL);
>> >> > > > }
>> >> > > >
>> >> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
>> >> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
>> >> > > > index 414992119e..0d3cd07fcc 100644
>> >> > > > --- a/include/hw/riscv/sifive_e.h
>> >> > > > +++ b/include/hw/riscv/sifive_e.h
>> >> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
>> >> > > >
>> >> > > > /*< public >*/
>> >> > > > SiFiveESoCState soc;
>> >> > > > + bool revb;
>> >> > > > } SiFiveEState;
>> >> > > >
>> >> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
>> >> > >
>> >> > > IIRC there are way more differences between the un-suffixed FE310 and the Rev
>> >> > > B, specifically the interrupt map is all different.
>> >> >
>> >> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
>> >> > all seem to be the same.
>> >>
>> >> Ping!
>> >
>> > Ping^2
>> >
>> > Applying to RISC-V tree.
>>
>> They're not: uart0 is interrupt 3 on the rev b but 5 on the non-rev b (which
>> they don't call rev a but I'm going to :)). There's isn't even a uart1 in the
>> DTS on the rev a, and the GPIO interrupts are different as well.
>>
>> The DTS files are in SiFive's SDK:
>>
>> https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1-revb/core.dts
>> https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1/core.dts
>>
>> which should also generate some test programs. When I was there we tested on
>> QEMU for the platforms that were supported, so there should be some support for
>> doing so still.
>
> I am reading the wrong data sheets?
>
> For revB I looked at
> https://sifive.cdn.prismic.io/sifive%2F9ecbb623-7c7f-4acc-966f-9bb10ecdb62e_fe310-g002.pdf,
> page 46, table 26. The interrupts for the revB match what we currently
> have in QEMU.
>
> For revA https://sifive.cdn.prismic.io/sifive%2F500a69f8-af3a-4fd9-927f-10ca77077532_fe310-g000.pdf,
> page 42, table 21 also matches what we have in QEMU.
>
> To me it looks like both have two UARTs and both have the same
> interrupt numbers.
>
> The actual software I am running also hasn't changed UART interrupt
> numbering between the two boards and UART interrupts are working
> correctly.
>
> Alistair
>
>>
>> >
>> > Alistair
>> >
>> >>
>> >> >
>> >> > Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/2] sifive_e: Support the revB machine
@ 2020-06-19 3:42 ` Palmer Dabbelt
0 siblings, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2020-06-19 3:42 UTC (permalink / raw)
To: alistair23; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On Thu, 18 Jun 2020 16:18:20 PDT (-0700), alistair23@gmail.com wrote:
> On Thu, Jun 18, 2020 at 3:42 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Wed, 10 Jun 2020 15:13:49 PDT (-0700), alistair23@gmail.com wrote:
>> > On Thu, May 28, 2020 at 11:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>> >>
>> >> On Thu, May 21, 2020 at 8:57 AM Alistair Francis <alistair23@gmail.com> wrote:
>> >> >
>> >> > On Wed, May 20, 2020 at 4:08 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> >> > >
>> >> > > On Thu, 14 May 2020 13:47:10 PDT (-0700), Alistair Francis wrote:
>> >> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> >> > > > ---
>> >> > > > hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
>> >> > > > include/hw/riscv/sifive_e.h | 1 +
>> >> > > > 2 files changed, 32 insertions(+), 4 deletions(-)
>> >> > > >
>> >> > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
>> >> > > > index 472a98970b..cb7818341b 100644
>> >> > > > --- a/hw/riscv/sifive_e.c
>> >> > > > +++ b/hw/riscv/sifive_e.c
>> >> > > > @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
>> >> > > > memmap[SIFIVE_E_DTIM].base, main_mem);
>> >> > > >
>> >> > > > /* Mask ROM reset vector */
>> >> > > > - uint32_t reset_vec[2] = {
>> >> > > > - 0x204002b7, /* 0x1000: lui t0,0x20400 */
>> >> > > > - 0x00028067, /* 0x1004: jr t0 */
>> >> > > > - };
>> >> > > > + uint32_t reset_vec[2];
>> >> > > > +
>> >> > > > + if (s->revb) {
>> >> > > > + reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
>> >> > > > + } else {
>> >> > > > + reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
>> >> > > > + }
>> >> > > > + reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
>> >> > > >
>> >> > > > /* copy in the reset vector in little_endian byte order */
>> >> > > > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
>> >> > > > @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
>> >> > > > }
>> >> > > > }
>> >> > > >
>> >> > > > +static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
>> >> > > > +{
>> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> >> > > > +
>> >> > > > + return s->revb;
>> >> > > > +}
>> >> > > > +
>> >> > > > +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
>> >> > > > +{
>> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> >> > > > +
>> >> > > > + s->revb = value;
>> >> > > > +}
>> >> > > > +
>> >> > > > static void sifive_e_machine_instance_init(Object *obj)
>> >> > > > {
>> >> > > > + SiFiveEState *s = RISCV_E_MACHINE(obj);
>> >> > > > +
>> >> > > > + s->revb = false;
>> >> > > > + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
>> >> > > > + sifive_e_machine_set_revb, NULL);
>> >> > > > + object_property_set_description(obj, "revb",
>> >> > > > + "Set on to tell QEMU that it should model "
>> >> > > > + "the revB HiFive1 board",
>> >> > > > + NULL);
>> >> > > > }
>> >> > > >
>> >> > > > static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
>> >> > > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
>> >> > > > index 414992119e..0d3cd07fcc 100644
>> >> > > > --- a/include/hw/riscv/sifive_e.h
>> >> > > > +++ b/include/hw/riscv/sifive_e.h
>> >> > > > @@ -45,6 +45,7 @@ typedef struct SiFiveEState {
>> >> > > >
>> >> > > > /*< public >*/
>> >> > > > SiFiveESoCState soc;
>> >> > > > + bool revb;
>> >> > > > } SiFiveEState;
>> >> > > >
>> >> > > > #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
>> >> > >
>> >> > > IIRC there are way more differences between the un-suffixed FE310 and the Rev
>> >> > > B, specifically the interrupt map is all different.
>> >> >
>> >> > The three IRQs that QEMU uses for the SiFive E (UART0, UART1 and GPIO)
>> >> > all seem to be the same.
>> >>
>> >> Ping!
>> >
>> > Ping^2
>> >
>> > Applying to RISC-V tree.
>>
>> They're not: uart0 is interrupt 3 on the rev b but 5 on the non-rev b (which
>> they don't call rev a but I'm going to :)). There's isn't even a uart1 in the
>> DTS on the rev a, and the GPIO interrupts are different as well.
>>
>> The DTS files are in SiFive's SDK:
>>
>> https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1-revb/core.dts
>> https://github.com/sifive/freedom-e-sdk/blob/master/bsp/sifive-hifive1/core.dts
>>
>> which should also generate some test programs. When I was there we tested on
>> QEMU for the platforms that were supported, so there should be some support for
>> doing so still.
>
> I am reading the wrong data sheets?
>
> For revB I looked at
> https://sifive.cdn.prismic.io/sifive%2F9ecbb623-7c7f-4acc-966f-9bb10ecdb62e_fe310-g002.pdf,
> page 46, table 26. The interrupts for the revB match what we currently
> have in QEMU.
>
> For revA https://sifive.cdn.prismic.io/sifive%2F500a69f8-af3a-4fd9-927f-10ca77077532_fe310-g000.pdf,
> page 42, table 21 also matches what we have in QEMU.
>
> To me it looks like both have two UARTs and both have the same
> interrupt numbers.
>
> The actual software I am running also hasn't changed UART interrupt
> numbering between the two boards and UART interrupts are working
> correctly.
>
> Alistair
>
>>
>> >
>> > Alistair
>> >
>> >>
>> >> >
>> >> > Alistair
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2020-06-19 3:43 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-14 20:47 [PATCH v1 1/2] riscv: sifive_e: Manually define the machine Alistair Francis
2020-05-14 20:47 ` Alistair Francis
2020-05-14 20:47 ` [PATCH v1 2/2] sifive_e: Support the revB machine Alistair Francis
2020-05-14 20:47 ` Alistair Francis
2020-05-20 23:08 ` Palmer Dabbelt
2020-05-20 23:08 ` Palmer Dabbelt
2020-05-21 15:57 ` Alistair Francis
2020-05-21 15:57 ` Alistair Francis
2020-05-28 18:13 ` Alistair Francis
2020-05-28 18:13 ` Alistair Francis
2020-06-10 22:13 ` Alistair Francis
2020-06-10 22:13 ` Alistair Francis
2020-06-18 22:42 ` Palmer Dabbelt
2020-06-18 22:42 ` Palmer Dabbelt
2020-06-18 23:18 ` Alistair Francis
2020-06-18 23:18 ` Alistair Francis
2020-06-19 3:42 ` Palmer Dabbelt
2020-06-19 3:42 ` Palmer Dabbelt
2020-05-20 23:08 ` [PATCH v1 1/2] riscv: sifive_e: Manually define the machine Palmer Dabbelt
2020-05-20 23:08 ` Palmer Dabbelt
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