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* [PATCH 1/3] RISC-V: Fix .init section permission update
@ 2021-01-29 19:00 ` Atish Patra
  0 siblings, 0 replies; 12+ messages in thread
From: Atish Patra @ 2021-01-29 19:00 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Geert Uytterhoeven, Albert Ou, Anup Patel,
	Ard Biesheuvel, Kirill A. Shutemov, linux-riscv,
	Nick Desaulniers, Palmer Dabbelt, Paul Walmsley,
	Sebastien Van Cauwenberghe, Zong Li

.init section permission should only updated to non-execute if
STRICT_KERNEL_RWX is enabled. Otherwise, this will lead to a kernel hang.

Fixes: 19a00869028f ("RISC-V: Protect all kernel sections including init early")

Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/kernel/setup.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 3fa3f26dde85..c7c0655dd45b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -293,6 +293,8 @@ void free_initmem(void)
 	unsigned long init_begin = (unsigned long)__init_begin;
 	unsigned long init_end = (unsigned long)__init_end;
 
-	set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT);
+	if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX))
+		set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT);
+
 	free_initmem_default(POISON_FREE_INITMEM);
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 1/3] RISC-V: Fix .init section permission update
@ 2021-01-29 19:00 ` Atish Patra
  0 siblings, 0 replies; 12+ messages in thread
From: Atish Patra @ 2021-01-29 19:00 UTC (permalink / raw)
  To: linux-kernel
  Cc: Sebastien Van Cauwenberghe, Albert Ou, Anup Patel, Atish Patra,
	Nick Desaulniers, Geert Uytterhoeven, Zong Li, Paul Walmsley,
	Palmer Dabbelt, linux-riscv, Ard Biesheuvel, Kirill A. Shutemov

.init section permission should only updated to non-execute if
STRICT_KERNEL_RWX is enabled. Otherwise, this will lead to a kernel hang.

Fixes: 19a00869028f ("RISC-V: Protect all kernel sections including init early")

Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/kernel/setup.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 3fa3f26dde85..c7c0655dd45b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -293,6 +293,8 @@ void free_initmem(void)
 	unsigned long init_begin = (unsigned long)__init_begin;
 	unsigned long init_end = (unsigned long)__init_end;
 
-	set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT);
+	if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX))
+		set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT);
+
 	free_initmem_default(POISON_FREE_INITMEM);
 }
-- 
2.25.1


_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 2/3] riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX
  2021-01-29 19:00 ` Atish Patra
@ 2021-01-29 19:00   ` Atish Patra
  -1 siblings, 0 replies; 12+ messages in thread
From: Atish Patra @ 2021-01-29 19:00 UTC (permalink / raw)
  To: linux-kernel
  Cc: Sebastien Van Cauwenberghe, Atish Patra, Albert Ou, Anup Patel,
	Ard Biesheuvel, Kirill A. Shutemov, linux-riscv,
	Nick Desaulniers, Palmer Dabbelt, Paul Walmsley, Zong Li

From: Sebastien Van Cauwenberghe <svancau@gmail.com>

Allows the sections to be aligned on smaller boundaries and
therefore results in a smaller kernel image size.

Signed-off-by: Sebastien Van Cauwenberghe <svancau@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/include/asm/set_memory.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h
index 211eb8244a45..8b80c80c7f1a 100644
--- a/arch/riscv/include/asm/set_memory.h
+++ b/arch/riscv/include/asm/set_memory.h
@@ -32,14 +32,14 @@ bool kernel_page_present(struct page *page);
 
 #endif /* __ASSEMBLY__ */
 
-#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
+#ifdef CONFIG_STRICT_KERNEL_RWX
 #ifdef CONFIG_64BIT
 #define SECTION_ALIGN (1 << 21)
 #else
 #define SECTION_ALIGN (1 << 22)
 #endif
-#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
+#else /* !CONFIG_STRICT_KERNEL_RWX */
 #define SECTION_ALIGN L1_CACHE_BYTES
-#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
+#endif /* CONFIG_STRICT_KERNEL_RWX */
 
 #endif /* _ASM_RISCV_SET_MEMORY_H */
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 2/3] riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX
@ 2021-01-29 19:00   ` Atish Patra
  0 siblings, 0 replies; 12+ messages in thread
From: Atish Patra @ 2021-01-29 19:00 UTC (permalink / raw)
  To: linux-kernel
  Cc: Sebastien Van Cauwenberghe, Albert Ou, Anup Patel, Atish Patra,
	Nick Desaulniers, Palmer Dabbelt, Zong Li, Paul Walmsley,
	linux-riscv, Ard Biesheuvel, Kirill A. Shutemov

From: Sebastien Van Cauwenberghe <svancau@gmail.com>

Allows the sections to be aligned on smaller boundaries and
therefore results in a smaller kernel image size.

Signed-off-by: Sebastien Van Cauwenberghe <svancau@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/include/asm/set_memory.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h
index 211eb8244a45..8b80c80c7f1a 100644
--- a/arch/riscv/include/asm/set_memory.h
+++ b/arch/riscv/include/asm/set_memory.h
@@ -32,14 +32,14 @@ bool kernel_page_present(struct page *page);
 
 #endif /* __ASSEMBLY__ */
 
-#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
+#ifdef CONFIG_STRICT_KERNEL_RWX
 #ifdef CONFIG_64BIT
 #define SECTION_ALIGN (1 << 21)
 #else
 #define SECTION_ALIGN (1 << 22)
 #endif
-#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
+#else /* !CONFIG_STRICT_KERNEL_RWX */
 #define SECTION_ALIGN L1_CACHE_BYTES
-#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
+#endif /* CONFIG_STRICT_KERNEL_RWX */
 
 #endif /* _ASM_RISCV_SET_MEMORY_H */
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 3/3] RISC-V: Define MAXPHYSMEM_1GB only for RV32
  2021-01-29 19:00 ` Atish Patra
@ 2021-01-29 19:00   ` Atish Patra
  -1 siblings, 0 replies; 12+ messages in thread
From: Atish Patra @ 2021-01-29 19:00 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Randy Dunlap, Geert Uytterhoeven, Albert Ou,
	Anup Patel, Ard Biesheuvel, Kirill A. Shutemov, linux-riscv,
	Nick Desaulniers, Palmer Dabbelt, Paul Walmsley,
	Sebastien Van Cauwenberghe, Zong Li

MAXPHYSMEM_1GB option was added for RV32 because RV32 only supports 1GB
of maximum physical memory. This lead to few compilation errors reported
by kernel test robot which created the following configuration combination
which are not useful but can be configured.

1. MAXPHYSMEM_1GB & RV64
2, MAXPHYSMEM_2GB & RV32

Fixes: e557793799c5 ("RISC-V: Fix maximum allowed phsyical memory for RV32")

Fix this by restricting MAXPHYSMEM_1GB for RV32 and MAXPHYSMEM_2GB only for
RV64.

Reported-by: Randy Dunlap <rdunlap@infradead.org>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index e9e2c1f0a690..e0a34eb5ed3b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -252,8 +252,10 @@ choice
 	default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY
 
 	config MAXPHYSMEM_1GB
+		depends on 32BIT
 		bool "1GiB"
 	config MAXPHYSMEM_2GB
+		depends on 64BIT && CMODEL_MEDLOW
 		bool "2GiB"
 	config MAXPHYSMEM_128GB
 		depends on 64BIT && CMODEL_MEDANY
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 3/3] RISC-V: Define MAXPHYSMEM_1GB only for RV32
@ 2021-01-29 19:00   ` Atish Patra
  0 siblings, 0 replies; 12+ messages in thread
From: Atish Patra @ 2021-01-29 19:00 UTC (permalink / raw)
  To: linux-kernel
  Cc: Sebastien Van Cauwenberghe, Randy Dunlap, Anup Patel,
	Atish Patra, Nick Desaulniers, Albert Ou, Geert Uytterhoeven,
	Zong Li, Paul Walmsley, Palmer Dabbelt, linux-riscv,
	Ard Biesheuvel, Kirill A. Shutemov

MAXPHYSMEM_1GB option was added for RV32 because RV32 only supports 1GB
of maximum physical memory. This lead to few compilation errors reported
by kernel test robot which created the following configuration combination
which are not useful but can be configured.

1. MAXPHYSMEM_1GB & RV64
2, MAXPHYSMEM_2GB & RV32

Fixes: e557793799c5 ("RISC-V: Fix maximum allowed phsyical memory for RV32")

Fix this by restricting MAXPHYSMEM_1GB for RV32 and MAXPHYSMEM_2GB only for
RV64.

Reported-by: Randy Dunlap <rdunlap@infradead.org>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index e9e2c1f0a690..e0a34eb5ed3b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -252,8 +252,10 @@ choice
 	default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY
 
 	config MAXPHYSMEM_1GB
+		depends on 32BIT
 		bool "1GiB"
 	config MAXPHYSMEM_2GB
+		depends on 64BIT && CMODEL_MEDLOW
 		bool "2GiB"
 	config MAXPHYSMEM_128GB
 		depends on 64BIT && CMODEL_MEDANY
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] RISC-V: Fix .init section permission update
  2021-01-29 19:00 ` Atish Patra
@ 2021-02-03  2:34   ` Palmer Dabbelt
  -1 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2021-02-03  2:34 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-kernel, Atish Patra, geert, aou, Anup Patel, ardb,
	kirill.shutemov, linux-riscv, ndesaulniers, Paul Walmsley,
	svancau, zong.li

On Fri, 29 Jan 2021 11:00:36 PST (-0800), Atish Patra wrote:
> .init section permission should only updated to non-execute if
> STRICT_KERNEL_RWX is enabled. Otherwise, this will lead to a kernel hang.
>
> Fixes: 19a00869028f ("RISC-V: Protect all kernel sections including init early")
>
> Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/kernel/setup.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 3fa3f26dde85..c7c0655dd45b 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -293,6 +293,8 @@ void free_initmem(void)
>  	unsigned long init_begin = (unsigned long)__init_begin;
>  	unsigned long init_end = (unsigned long)__init_end;
>
> -	set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT);
> +	if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX))
> +		set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT);
> +
>  	free_initmem_default(POISON_FREE_INITMEM);
>  }

Thanks, this is on fixes.

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] RISC-V: Fix .init section permission update
@ 2021-02-03  2:34   ` Palmer Dabbelt
  0 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2021-02-03  2:34 UTC (permalink / raw)
  To: Atish Patra
  Cc: svancau, aou, Anup Patel, linux-kernel, Atish Patra,
	ndesaulniers, geert, zong.li, Paul Walmsley, linux-riscv, ardb,
	kirill.shutemov

On Fri, 29 Jan 2021 11:00:36 PST (-0800), Atish Patra wrote:
> .init section permission should only updated to non-execute if
> STRICT_KERNEL_RWX is enabled. Otherwise, this will lead to a kernel hang.
>
> Fixes: 19a00869028f ("RISC-V: Protect all kernel sections including init early")
>
> Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/kernel/setup.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 3fa3f26dde85..c7c0655dd45b 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -293,6 +293,8 @@ void free_initmem(void)
>  	unsigned long init_begin = (unsigned long)__init_begin;
>  	unsigned long init_end = (unsigned long)__init_end;
>
> -	set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT);
> +	if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX))
> +		set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT);
> +
>  	free_initmem_default(POISON_FREE_INITMEM);
>  }

Thanks, this is on fixes.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX
  2021-01-29 19:00   ` Atish Patra
@ 2021-02-03  2:34     ` Palmer Dabbelt
  -1 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2021-02-03  2:34 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-kernel, svancau, Atish Patra, aou, Anup Patel, ardb,
	kirill.shutemov, linux-riscv, ndesaulniers, Paul Walmsley,
	zong.li

On Fri, 29 Jan 2021 11:00:37 PST (-0800), Atish Patra wrote:
> From: Sebastien Van Cauwenberghe <svancau@gmail.com>
>
> Allows the sections to be aligned on smaller boundaries and
> therefore results in a smaller kernel image size.
>
> Signed-off-by: Sebastien Van Cauwenberghe <svancau@gmail.com>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/include/asm/set_memory.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h
> index 211eb8244a45..8b80c80c7f1a 100644
> --- a/arch/riscv/include/asm/set_memory.h
> +++ b/arch/riscv/include/asm/set_memory.h
> @@ -32,14 +32,14 @@ bool kernel_page_present(struct page *page);
>
>  #endif /* __ASSEMBLY__ */
>
> -#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
> +#ifdef CONFIG_STRICT_KERNEL_RWX
>  #ifdef CONFIG_64BIT
>  #define SECTION_ALIGN (1 << 21)
>  #else
>  #define SECTION_ALIGN (1 << 22)
>  #endif
> -#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
> +#else /* !CONFIG_STRICT_KERNEL_RWX */
>  #define SECTION_ALIGN L1_CACHE_BYTES
> -#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
> +#endif /* CONFIG_STRICT_KERNEL_RWX */
>
>  #endif /* _ASM_RISCV_SET_MEMORY_H */

Thanks, this is on fixes.

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX
@ 2021-02-03  2:34     ` Palmer Dabbelt
  0 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2021-02-03  2:34 UTC (permalink / raw)
  To: Atish Patra
  Cc: svancau, aou, Anup Patel, linux-kernel, Atish Patra,
	ndesaulniers, zong.li, Paul Walmsley, linux-riscv, ardb,
	kirill.shutemov

On Fri, 29 Jan 2021 11:00:37 PST (-0800), Atish Patra wrote:
> From: Sebastien Van Cauwenberghe <svancau@gmail.com>
>
> Allows the sections to be aligned on smaller boundaries and
> therefore results in a smaller kernel image size.
>
> Signed-off-by: Sebastien Van Cauwenberghe <svancau@gmail.com>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/include/asm/set_memory.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h
> index 211eb8244a45..8b80c80c7f1a 100644
> --- a/arch/riscv/include/asm/set_memory.h
> +++ b/arch/riscv/include/asm/set_memory.h
> @@ -32,14 +32,14 @@ bool kernel_page_present(struct page *page);
>
>  #endif /* __ASSEMBLY__ */
>
> -#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
> +#ifdef CONFIG_STRICT_KERNEL_RWX
>  #ifdef CONFIG_64BIT
>  #define SECTION_ALIGN (1 << 21)
>  #else
>  #define SECTION_ALIGN (1 << 22)
>  #endif
> -#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
> +#else /* !CONFIG_STRICT_KERNEL_RWX */
>  #define SECTION_ALIGN L1_CACHE_BYTES
> -#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
> +#endif /* CONFIG_STRICT_KERNEL_RWX */
>
>  #endif /* _ASM_RISCV_SET_MEMORY_H */

Thanks, this is on fixes.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] RISC-V: Define MAXPHYSMEM_1GB only for RV32
  2021-01-29 19:00   ` Atish Patra
@ 2021-02-03  2:34     ` Palmer Dabbelt
  -1 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2021-02-03  2:34 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-kernel, Atish Patra, rdunlap, geert, aou, Anup Patel, ardb,
	kirill.shutemov, linux-riscv, ndesaulniers, Paul Walmsley,
	svancau, zong.li

On Fri, 29 Jan 2021 11:00:38 PST (-0800), Atish Patra wrote:
> MAXPHYSMEM_1GB option was added for RV32 because RV32 only supports 1GB
> of maximum physical memory. This lead to few compilation errors reported
> by kernel test robot which created the following configuration combination
> which are not useful but can be configured.
>
> 1. MAXPHYSMEM_1GB & RV64
> 2, MAXPHYSMEM_2GB & RV32
>
> Fixes: e557793799c5 ("RISC-V: Fix maximum allowed phsyical memory for RV32")
>
> Fix this by restricting MAXPHYSMEM_1GB for RV32 and MAXPHYSMEM_2GB only for
> RV64.
>
> Reported-by: Randy Dunlap <rdunlap@infradead.org>
> Acked-by: Randy Dunlap <rdunlap@infradead.org>
> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e9e2c1f0a690..e0a34eb5ed3b 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -252,8 +252,10 @@ choice
>  	default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY
>
>  	config MAXPHYSMEM_1GB
> +		depends on 32BIT
>  		bool "1GiB"
>  	config MAXPHYSMEM_2GB
> +		depends on 64BIT && CMODEL_MEDLOW
>  		bool "2GiB"
>  	config MAXPHYSMEM_128GB
>  		depends on 64BIT && CMODEL_MEDANY

Ah, I guess here's the patch :).  This is on fixes.

Thanks!

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] RISC-V: Define MAXPHYSMEM_1GB only for RV32
@ 2021-02-03  2:34     ` Palmer Dabbelt
  0 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2021-02-03  2:34 UTC (permalink / raw)
  To: Atish Patra
  Cc: svancau, rdunlap, Anup Patel, linux-kernel, Atish Patra,
	ndesaulniers, aou, geert, zong.li, Paul Walmsley, linux-riscv,
	ardb, kirill.shutemov

On Fri, 29 Jan 2021 11:00:38 PST (-0800), Atish Patra wrote:
> MAXPHYSMEM_1GB option was added for RV32 because RV32 only supports 1GB
> of maximum physical memory. This lead to few compilation errors reported
> by kernel test robot which created the following configuration combination
> which are not useful but can be configured.
>
> 1. MAXPHYSMEM_1GB & RV64
> 2, MAXPHYSMEM_2GB & RV32
>
> Fixes: e557793799c5 ("RISC-V: Fix maximum allowed phsyical memory for RV32")
>
> Fix this by restricting MAXPHYSMEM_1GB for RV32 and MAXPHYSMEM_2GB only for
> RV64.
>
> Reported-by: Randy Dunlap <rdunlap@infradead.org>
> Acked-by: Randy Dunlap <rdunlap@infradead.org>
> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e9e2c1f0a690..e0a34eb5ed3b 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -252,8 +252,10 @@ choice
>  	default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY
>
>  	config MAXPHYSMEM_1GB
> +		depends on 32BIT
>  		bool "1GiB"
>  	config MAXPHYSMEM_2GB
> +		depends on 64BIT && CMODEL_MEDLOW
>  		bool "2GiB"
>  	config MAXPHYSMEM_128GB
>  		depends on 64BIT && CMODEL_MEDANY

Ah, I guess here's the patch :).  This is on fixes.

Thanks!

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^ permalink raw reply	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-02-03  2:36 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-29 19:00 [PATCH 1/3] RISC-V: Fix .init section permission update Atish Patra
2021-01-29 19:00 ` Atish Patra
2021-01-29 19:00 ` [PATCH 2/3] riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX Atish Patra
2021-01-29 19:00   ` Atish Patra
2021-02-03  2:34   ` Palmer Dabbelt
2021-02-03  2:34     ` Palmer Dabbelt
2021-01-29 19:00 ` [PATCH 3/3] RISC-V: Define MAXPHYSMEM_1GB only for RV32 Atish Patra
2021-01-29 19:00   ` Atish Patra
2021-02-03  2:34   ` Palmer Dabbelt
2021-02-03  2:34     ` Palmer Dabbelt
2021-02-03  2:34 ` [PATCH 1/3] RISC-V: Fix .init section permission update Palmer Dabbelt
2021-02-03  2:34   ` Palmer Dabbelt

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