Re: [PATCH v2 2/2] RISC-V: defconfig: Enable Goldfish RTC driver

[Palmer Dabbelt <palmer@sifive.com>]

On Tue, 24 Sep 2019 23:38:08 PDT (-0700), Anup Patel wrote:
> We have Goldfish RTC device available on QEMU RISC-V virt machine
> hence enable required driver in RV32 and RV64 defconfigs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/configs/defconfig      | 3 +++
>  arch/riscv/configs/rv32_defconfig | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 3efff552a261..57b4f67b0c0b 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -73,7 +73,10 @@ CONFIG_USB_STORAGE=y
>  CONFIG_USB_UAS=y
>  CONFIG_MMC=y
>  CONFIG_MMC_SPI=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_GOLDFISH=y
>  CONFIG_VIRTIO_MMIO=y
> +CONFIG_GOLDFISH=y
>  CONFIG_EXT4_FS=y
>  CONFIG_EXT4_FS_POSIX_ACL=y
>  CONFIG_AUTOFS4_FS=y
> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> index 7da93e494445..50716c1395aa 100644
> --- a/arch/riscv/configs/rv32_defconfig
> +++ b/arch/riscv/configs/rv32_defconfig
> @@ -69,7 +69,10 @@ CONFIG_USB_OHCI_HCD=y
>  CONFIG_USB_OHCI_HCD_PLATFORM=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_USB_UAS=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_GOLDFISH=y
>  CONFIG_VIRTIO_MMIO=y
> +CONFIG_GOLDFISH=y
>  CONFIG_SIFIVE_PLIC=y
>  CONFIG_EXT4_FS=y
>  CONFIG_EXT4_FS_POSIX_ACL=y
> -- 
> 2.17.1

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

IIRC there was supposed to be a follow-up to your QEMU patch set to rebase it 
on top of a refactoring of their RTC code, but I don't see it in my inbox.  LMK 
if I missed it, as QEMU's soft freeze is in a few weeks and I'd like to make 
sure I get everything in.

Additionally: we should refactor our Kconfig to have some sort of 
CONFIG_SOC_VIRT that selects this stuff, like we have the CONFIG_SOC_SIFIVE.  
This will explicitly document why devices are in the defconfig, avoid 
duplicating a bunch of stuff between defconfigs, and provide an example of how 
we support multiple SOCs in a single image.

I don't see why either of these should block merging the patch, though.