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* [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
@ 2018-07-27  8:53 Jakub Bartmiński
  2018-07-27  8:53 ` [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used Jakub Bartmiński
                   ` (6 more replies)
  0 siblings, 7 replies; 17+ messages in thread
From: Jakub Bartmiński @ 2018-07-27  8:53 UTC (permalink / raw)
  To: intel-gfx

It would appear that the calculated GuC pin bias was larger than it should
be, as the GuC address space does NOT contain the "HW contexts RSVD" part
of the WOPCM. Thus, the GuC pin bias is simply the GuC WOPCM size.

v5:
Clarify the diagram to better represent the GuC address space.
Since we now don't use guc.base for the pin bias there's no need to
validate it. It also has already been verified in WOPCM init.

Bspec: 1180

Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c | 49 +++++++++++++-------------------
 1 file changed, 20 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index e12bd259df17..aa28368f8ba7 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -582,50 +582,41 @@ int intel_guc_resume(struct intel_guc *guc)
  *
  * ::
  *
- *     +==============> +====================+ <== GUC_GGTT_TOP
- *     ^                |                    |
- *     |                |                    |
- *     |                |        DRAM        |
- *     |                |       Memory       |
- *     |                |                    |
- *    GuC               |                    |
- *  Address  +========> +====================+ <== WOPCM Top
- *   Space   ^          |   HW contexts RSVD |
- *     |     |          |        WOPCM       |
- *     |     |     +==> +--------------------+ <== GuC WOPCM Top
- *     |    GuC    ^    |                    |
- *     |    GGTT   |    |                    |
- *     |    Pin   GuC   |        GuC         |
- *     |    Bias WOPCM  |       WOPCM        |
- *     |     |    Size  |                    |
- *     |     |     |    |                    |
- *     v     v     v    |                    |
- *     +=====+=====+==> +====================+ <== GuC WOPCM Base
- *                      |   Non-GuC WOPCM    |
- *                      |   (HuC/Reserved)   |
- *                      +====================+ <== WOPCM Base
+ *     +===========> +====================+ <== FFFF_FFFF
+ *     ^             |      Reserved      |
+ *     |             +====================+ <== GUC_GGTT_TOP
+ *     |             |                    |
+ *     |             |        DRAM        |
+ *    GuC            |                    |
+ *  Address    +===> +====================+ <== GuC ggtt_pin_bias
+ *   Space     ^     |                    |
+ *     |       |     |                    |
+ *     |      GuC    |        GuC         |
+ *     |     WOPCM   |       WOPCM        |
+ *     |      Size   |                    |
+ *     |       |     |                    |
+ *     v       v     |                    |
+ *     +=======+===> +====================+ <== 0000_0000
  *
- * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM
+ * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
  * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
- * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and
- * actual GuC WOPCM size.
+ * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
  */
 
 /**
  * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
  * @guc: intel_guc structure.
  *
- * This function will calculate and initialize the ggtt_pin_bias value based on
- * overall WOPCM size and GuC WOPCM size.
+ * This function will calculate and initialize the ggtt_pin_bias value
+ * based on the GuC WOPCM size.
  */
 static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
 {
 	struct drm_i915_private *i915 = guc_to_i915(guc);
 
 	GEM_BUG_ON(!i915->wopcm.size);
-	GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
 
-	guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
+	guc->ggtt_pin_bias = i915->wopcm.guc.size;
 }
 
 /**
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used.
  2018-07-27  8:53 [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Jakub Bartmiński
@ 2018-07-27  8:53 ` Jakub Bartmiński
  2018-07-27 10:20   ` Chris Wilson
  2018-07-27 12:04   ` Michal Wajdeczko
  2018-07-27  8:53 ` [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT Jakub Bartmiński
                   ` (5 subsequent siblings)
  6 siblings, 2 replies; 17+ messages in thread
From: Jakub Bartmiński @ 2018-07-27  8:53 UTC (permalink / raw)
  To: intel-gfx

There seems to be no reason for doing extra work on WOPCM partitioning
in the case GuC is not used, as the partitioning will not be used by the
intel_wopcm_init_hw function anyway.

Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/intel_wopcm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 74bf76f3fddc..09cc62b0d7ca 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -163,6 +163,9 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
 	u32 guc_wopcm_rsvd;
 	int err;
 
+	if (!USES_GUC(dev_priv))
+		return 0;
+
 	GEM_BUG_ON(!wopcm->size);
 
 	if (guc_fw_size >= wopcm->size) {
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT
  2018-07-27  8:53 [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Jakub Bartmiński
  2018-07-27  8:53 ` [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used Jakub Bartmiński
@ 2018-07-27  8:53 ` Jakub Bartmiński
  2018-07-27 10:29   ` Chris Wilson
  2018-07-27  8:53 ` [PATCH v6 4/6] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context Jakub Bartmiński
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 17+ messages in thread
From: Jakub Bartmiński @ 2018-07-27  8:53 UTC (permalink / raw)
  To: intel-gfx

Removing the pin bias from GuC allows us to not check for GuC every time
we pin a context, which fixes the assertion error on unresolved GuC
platform default in mock contexts selftest.

It also seems that we were using uninitialized WOPCM variables when
setting the GuC pin bias. The pin bias has to be set after the WOPCM,
but before the call to i915_gem_contexts_init where the first contexts
are pinned.

v2:
This also makes it so that there's no need to set GuC variables from
within the WOPCM init function or to move the WOPCM init, while keeping
the correct initialization order. Also for mock tests the pin bias is
left at 0 and we make sure that the pin bias with GuC will not be
smaller than without GuC.

v3:
Avoid unused i915 in intel_guc_ggtt_offset if debug is disabled.

v4:
Squash with WOPCM init reordering.
Moved the i915_ggtt_pin_bias helper to this patch, and made some
functions use it instead of directly dereferencing i915->ggtt.

v5:
Since we now don't use wopcm.guc.base for the pin bias there's no need to
validate it. It also has already been verified in WOPCM init.

v6:
Moved and renamed the function which now returns the wopcm.guc.size to
intel_guc.c:intel_guc_wopcm_region_size to avoid any possible confusion
with the pin_bias in ggtt, which should be used for pinning.
Deleted the now unnecessarily introduced includes from previous versions.
Dropped naming changes from dev_priv to i915 for better patch readability.

Fixes: f7dc0157e4b5 ("drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init")
Testcase: igt/drv_selftest/mock_contexts #GuC
Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 10 +-----
 drivers/gpu/drm/i915/i915_gem_gtt.c     |  8 +++++
 drivers/gpu/drm/i915/i915_gem_gtt.h     |  2 ++
 drivers/gpu/drm/i915/i915_vma.h         |  5 +++
 drivers/gpu/drm/i915/intel_guc.c        | 43 ++++++++++++-------------
 drivers/gpu/drm/i915/intel_guc.h        | 12 +++----
 drivers/gpu/drm/i915/intel_huc.c        |  2 +-
 drivers/gpu/drm/i915/intel_uc_fw.c      |  2 +-
 8 files changed, 44 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b10770cfccd2..32f96b8cd9c4 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -329,15 +329,7 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 	ctx->desc_template =
 		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
 
-	/*
-	 * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
-	 * present or not in use we still need a small bias as ring wraparound
-	 * at offset 0 sometimes hangs. No idea why.
-	 */
-	if (USES_GUC(dev_priv))
-		ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
-	else
-		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
+	ctx->ggtt_offset_bias = dev_priv->ggtt.pin_bias;
 
 	return ctx;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d0acef299b9c..8ac5214b3648 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2917,6 +2917,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	struct drm_mm_node *entry;
 	int ret;
 
+	/*
+	 * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
+	 * present or not in use we still need a small bias as ring wraparound
+	 * at offset 0 sometimes hangs. No idea why.
+	 */
+	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
+			       intel_guc_wopcm_region_size(&dev_priv->guc));
+
 	ret = intel_vgt_balloon(dev_priv);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 14e62651010b..71e8cf24c800 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -396,6 +396,8 @@ struct i915_ggtt {
 
 	int mtrr;
 
+	u32 pin_bias;
+
 	struct drm_mm_node error_capture;
 };
 
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index f06d66377107..abf6144e3296 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -207,6 +207,11 @@ static inline u32 i915_ggtt_offset(const struct i915_vma *vma)
 	return lower_32_bits(vma->node.start);
 }
 
+static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
+{
+	return i915_vm_to_ggtt(vma->vm)->pin_bias;
+}
+
 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
 {
 	i915_gem_object_get(vma->obj);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index aa28368f8ba7..8ab4653e89af 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -27,8 +27,6 @@
 #include "intel_guc_submission.h"
 #include "i915_drv.h"
 
-static void guc_init_ggtt_pin_bias(struct intel_guc *guc);
-
 static void gen8_guc_raise_irq(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -142,8 +140,6 @@ int intel_guc_init_misc(struct intel_guc *guc)
 	struct drm_i915_private *i915 = guc_to_i915(guc);
 	int ret;
 
-	guc_init_ggtt_pin_bias(guc);
-
 	ret = guc_init_wq(guc);
 	if (ret)
 		return ret;
@@ -603,22 +599,6 @@ int intel_guc_resume(struct intel_guc *guc)
  * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
  */
 
-/**
- * guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
- * @guc: intel_guc structure.
- *
- * This function will calculate and initialize the ggtt_pin_bias value
- * based on the GuC WOPCM size.
- */
-static void guc_init_ggtt_pin_bias(struct intel_guc *guc)
-{
-	struct drm_i915_private *i915 = guc_to_i915(guc);
-
-	GEM_BUG_ON(!i915->wopcm.size);
-
-	guc->ggtt_pin_bias = i915->wopcm.guc.size;
-}
-
 /**
  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
  * @guc:	the guc
@@ -637,6 +617,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
+	u64 flags;
 	int ret;
 
 	obj = i915_gem_object_create(dev_priv, size);
@@ -647,8 +628,8 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 	if (IS_ERR(vma))
 		goto err;
 
-	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
-			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
+	flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
+	ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
 	if (ret) {
 		vma = ERR_PTR(ret);
 		goto err;
@@ -660,3 +641,21 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 	i915_gem_object_put(obj);
 	return vma;
 }
+
+/**
+ * intel_guc_wopcm_region_size() - Get the size of the GuC region of WOPCM.
+ * @guc: intel_guc structure.
+ *
+ * Returns:
+ * 0 if GuC is not present or not in use.
+ * Otherwise, the GuC WOPCM size.
+ */
+u32 intel_guc_wopcm_region_size(struct intel_guc *guc)
+{
+	struct intel_wopcm *wopcm = &guc_to_i915(guc)->wopcm;
+
+	/* WOPCM must have already been partitioned */
+	GEM_BUG_ON(!wopcm->size);
+
+	return wopcm->guc.size;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4121928a495e..61fe3034cbe2 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -49,9 +49,6 @@ struct intel_guc {
 	struct intel_guc_log log;
 	struct intel_guc_ct ct;
 
-	/* Offset where Non-WOPCM memory starts. */
-	u32 ggtt_pin_bias;
-
 	/* Log snapshot if GuC errors during load */
 	struct drm_i915_gem_object *load_err_log;
 
@@ -130,10 +127,10 @@ static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
  * @vma: i915 graphics virtual memory area.
  *
  * GuC does not allow any gfx GGTT address that falls into range
- * [0, GuC ggtt_pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
- * Currently, in order to exclude [0, GuC ggtt_pin_bias) address space from
+ * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
+ * Currently, in order to exclude [0, ggtt.pin_bias) address space from
  * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
- * and pinned with PIN_OFFSET_BIAS along with the value of GuC ggtt_pin_bias.
+ * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
  *
  * Return: GGTT offset of the @vma.
  */
@@ -142,7 +139,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
 {
 	u32 offset = i915_ggtt_offset(vma);
 
-	GEM_BUG_ON(offset < guc->ggtt_pin_bias);
+	GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
 	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
 
 	return offset;
@@ -168,6 +165,7 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 int intel_guc_suspend(struct intel_guc *guc);
 int intel_guc_resume(struct intel_guc *guc);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
+u32 intel_guc_wopcm_region_size(struct intel_guc *guc);
 
 static inline int intel_guc_sanitize(struct intel_guc *guc)
 {
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index ffcad5fad6a7..37ef540dd280 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -63,7 +63,7 @@ int intel_huc_auth(struct intel_huc *huc)
 		return -ENOEXEC;
 
 	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
-				       PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
+				       PIN_OFFSET_BIAS | i915->ggtt.pin_bias);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 6e8e0b546743..fd496416087c 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -222,7 +222,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 		goto fail;
 	}
 
-	ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->guc.ggtt_pin_bias;
+	ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias;
 	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
 				       PIN_OFFSET_BIAS | ggtt_pin_bias);
 	if (IS_ERR(vma)) {
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v6 4/6] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context
  2018-07-27  8:53 [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Jakub Bartmiński
  2018-07-27  8:53 ` [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used Jakub Bartmiński
  2018-07-27  8:53 ` [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT Jakub Bartmiński
@ 2018-07-27  8:53 ` Jakub Bartmiński
  2018-07-27 10:30   ` Chris Wilson
  2018-07-27  8:53 ` [PATCH v6 5/6] drm/i915: Add a fault injection point to WOPCM init Jakub Bartmiński
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 17+ messages in thread
From: Jakub Bartmiński @ 2018-07-27  8:53 UTC (permalink / raw)
  To: intel-gfx

Since ggtt_offset_bias is now stored in ggtt.pin_bias, it is duplicated
inside i915_gem_context, and can instead be accessed directly from ggtt.

v3:
Added a helper function to retrieve the ggtt.pin_bias from the vma.

v4:
Moved the helper function to the previous patch in the series.
Dropped the bias from intel_ring_pin. This introduces a slight functional
change since we are always pinning the ring a bit higher if GuC is present
even though we don't really need to.

Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 --
 drivers/gpu/drm/i915/i915_gem_context.h |  3 ---
 drivers/gpu/drm/i915/intel_lrc.c        |  6 ++----
 drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++--------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 +---
 5 files changed, 9 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 32f96b8cd9c4..f15a039772db 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -329,8 +329,6 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 	ctx->desc_template =
 		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
 
-	ctx->ggtt_offset_bias = dev_priv->ggtt.pin_bias;
-
 	return ctx;
 
 err_pid:
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
index b116e4942c10..851dad6decd7 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -147,9 +147,6 @@ struct i915_gem_context {
 
 	struct i915_sched_attr sched;
 
-	/** ggtt_offset_bias: placement restriction for context objects */
-	u32 ggtt_offset_bias;
-
 	/** engine: per-engine logical HW state */
 	struct intel_context {
 		struct i915_gem_context *gem_context;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 35d37af0cb9a..c923eb998c28 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1363,9 +1363,7 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
 	}
 
 	flags = PIN_GLOBAL | PIN_HIGH;
-	if (ctx->ggtt_offset_bias)
-		flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
-
+	flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
 	return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
 }
 
@@ -1392,7 +1390,7 @@ __execlists_context_pin(struct intel_engine_cs *engine,
 		goto unpin_vma;
 	}
 
-	ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
+	ret = intel_ring_pin(ce->ring, ctx->i915);
 	if (ret)
 		goto unpin_map;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f4bd185c9369..8a48325249a3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1005,9 +1005,7 @@ i915_emit_bb_start(struct i915_request *rq,
 
 
 
-int intel_ring_pin(struct intel_ring *ring,
-		   struct drm_i915_private *i915,
-		   unsigned int offset_bias)
+int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private *i915)
 {
 	enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
 	struct i915_vma *vma = ring->vma;
@@ -1017,10 +1015,11 @@ int intel_ring_pin(struct intel_ring *ring,
 
 	GEM_BUG_ON(ring->vaddr);
 
-
 	flags = PIN_GLOBAL;
-	if (offset_bias)
-		flags |= PIN_OFFSET_BIAS | offset_bias;
+
+	/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
+	flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
+
 	if (vma->obj->stolen)
 		flags |= PIN_MAPPABLE;
 	else
@@ -1404,8 +1403,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
 		goto err;
 	}
 
-	/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
-	err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
+	err = intel_ring_pin(ring, engine->i915);
 	if (err)
 		goto err_ring;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index d1eee08e5f6b..7fe07b2de2a7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -784,9 +784,7 @@ struct intel_ring *
 intel_engine_create_ring(struct intel_engine_cs *engine,
 			 struct i915_timeline *timeline,
 			 int size);
-int intel_ring_pin(struct intel_ring *ring,
-		   struct drm_i915_private *i915,
-		   unsigned int offset_bias);
+int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private *i915);
 void intel_ring_reset(struct intel_ring *ring, u32 tail);
 unsigned int intel_ring_update_space(struct intel_ring *ring);
 void intel_ring_unpin(struct intel_ring *ring);
-- 
2.17.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v6 5/6] drm/i915: Add a fault injection point to WOPCM init
  2018-07-27  8:53 [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Jakub Bartmiński
                   ` (2 preceding siblings ...)
  2018-07-27  8:53 ` [PATCH v6 4/6] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context Jakub Bartmiński
@ 2018-07-27  8:53 ` Jakub Bartmiński
  2018-07-27 12:06   ` Michal Wajdeczko
  2018-07-27  8:53 ` [PATCH v6 6/6] HAX enable GuC for CI Jakub Bartmiński
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 17+ messages in thread
From: Jakub Bartmiński @ 2018-07-27  8:53 UTC (permalink / raw)
  To: intel-gfx

Add a fault injection point in the WOPCM initialization path.

v4:
Move the injection inside the WOPCM init function.

Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/intel_wopcm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 09cc62b0d7ca..92cb82dd0c07 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -168,6 +168,9 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
 
 	GEM_BUG_ON(!wopcm->size);
 
+	if (i915_inject_load_failure())
+		return -E2BIG;
+
 	if (guc_fw_size >= wopcm->size) {
 		DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
 			  guc_fw_size / 1024);
-- 
2.17.1

_______________________________________________
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^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH v6 6/6] HAX enable GuC for CI
  2018-07-27  8:53 [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Jakub Bartmiński
                   ` (3 preceding siblings ...)
  2018-07-27  8:53 ` [PATCH v6 5/6] drm/i915: Add a fault injection point to WOPCM init Jakub Bartmiński
@ 2018-07-27  8:53 ` Jakub Bartmiński
  2018-07-27  9:16 ` ✗ Fi.CI.SPARSE: warning for series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Patchwork
  2018-07-27  9:35 ` ✗ Fi.CI.BAT: failure " Patchwork
  6 siblings, 0 replies; 17+ messages in thread
From: Jakub Bartmiński @ 2018-07-27  8:53 UTC (permalink / raw)
  To: intel-gfx

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index aebe0469ddaa..3e4e128237ac 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
2.17.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* ✗ Fi.CI.SPARSE: warning for series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
  2018-07-27  8:53 [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Jakub Bartmiński
                   ` (4 preceding siblings ...)
  2018-07-27  8:53 ` [PATCH v6 6/6] HAX enable GuC for CI Jakub Bartmiński
@ 2018-07-27  9:16 ` Patchwork
  2018-07-27  9:35 ` ✗ Fi.CI.BAT: failure " Patchwork
  6 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-07-27  9:16 UTC (permalink / raw)
  To: Jakub Bartmiński; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
URL   : https://patchwork.freedesktop.org/series/47328/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
Okay!

Commit: drm/i915/guc: Do not partition WOPCM if GuC is not used.
Okay!

Commit: drm/i915/guc: Move the pin bias value from GuC to GGTT
+drivers/gpu/drm/i915/i915_gem_gtt.c:2937:26: warning: expression using sizeof(void)

Commit: drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context
Okay!

Commit: drm/i915: Add a fault injection point to WOPCM init
Okay!

Commit: HAX enable GuC for CI
Okay!

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* ✗ Fi.CI.BAT: failure for series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
  2018-07-27  8:53 [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Jakub Bartmiński
                   ` (5 preceding siblings ...)
  2018-07-27  9:16 ` ✗ Fi.CI.SPARSE: warning for series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Patchwork
@ 2018-07-27  9:35 ` Patchwork
  2018-07-27  9:51   ` Chris Wilson
  6 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2018-07-27  9:35 UTC (permalink / raw)
  To: Jakub Bartmiński; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
URL   : https://patchwork.freedesktop.org/series/47328/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4559 -> Patchwork_9788 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9788 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9788, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/47328/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9788:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_selftest@live_contexts:
      {fi-skl-iommu}:     PASS -> DMESG-FAIL

    igt@drv_selftest@live_guc:
      fi-kbl-7567u:       PASS -> DMESG-WARN
      fi-skl-gvtdvm:      PASS -> DMESG-WARN
      fi-bxt-dsi:         NOTRUN -> DMESG-WARN
      fi-whl-u:           PASS -> DMESG-WARN
      fi-kbl-7560u:       PASS -> DMESG-WARN
      {fi-kbl-8809g}:     PASS -> DMESG-WARN
      fi-kbl-r:           PASS -> DMESG-WARN
      fi-kbl-x1275:       PASS -> DMESG-WARN
      fi-bxt-j4205:       PASS -> DMESG-WARN
      fi-cfl-s3:          PASS -> DMESG-WARN
      {fi-cfl-8109u}:     PASS -> DMESG-WARN
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-cfl-8700k:       PASS -> DMESG-WARN

    igt@drv_selftest@live_hangcheck:
      fi-cfl-guc:         PASS -> DMESG-FAIL
      fi-bxt-dsi:         NOTRUN -> DMESG-FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_9788 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_guc:
      fi-skl-6600u:       PASS -> DMESG-WARN (fdo#107175)
      {fi-skl-iommu}:     PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6260u:       PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6700k2:      PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6770hq:      PASS -> DMESG-WARN (fdo#107175)
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#107175)

    igt@drv_selftest@live_hangcheck:
      fi-skl-6600u:       PASS -> DMESG-FAIL (fdo#107174)

    igt@drv_selftest@live_requests:
      {fi-skl-iommu}:     PASS -> DMESG-FAIL (fdo#107174) +1

    igt@kms_pipe_crc_basic@read-crc-pipe-c:
      fi-skl-6700k2:      PASS -> FAIL (fdo#103191)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_workarounds:
      {fi-cfl-8109u}:     DMESG-FAIL (fdo#107292) -> PASS
      {fi-bsw-kefka}:     DMESG-FAIL (fdo#107292) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS
      fi-skl-6700k2:      FAIL (fdo#103191) -> PASS

    
    ==== Warnings ====

    {igt@kms_psr@primary_page_flip}:
      fi-cnl-psr:         DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
  fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
  fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
  fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372


== Participating hosts (53 -> 47) ==

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


== Build changes ==

    * Linux: CI_DRM_4559 -> Patchwork_9788

  CI_DRM_4559: 749fbb7efb867a15963eb08a942ef6f9e0b3335b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4576: bcb37a9b20eeec97f15fac2222408cc2e0b77631 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9788: 34f02fc7ec216c4d154ba7d734b23c9025b4ab8a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

34f02fc7ec21 HAX enable GuC for CI
26371fcaeeea drm/i915: Add a fault injection point to WOPCM init
af030e7ad3d8 drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context
5147c269e913 drm/i915/guc: Move the pin bias value from GuC to GGTT
f559da993f6b drm/i915/guc: Do not partition WOPCM if GuC is not used.
287368e2c62a drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9788/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: ✗ Fi.CI.BAT: failure for series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
  2018-07-27  9:35 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-07-27  9:51   ` Chris Wilson
  2018-07-27 10:32     ` Bartminski, Jakub
  0 siblings, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2018-07-27  9:51 UTC (permalink / raw)
  To: Jakub Bartmiński, Patchwork; +Cc: intel-gfx

Quoting Patchwork (2018-07-27 10:35:57)
> == Series Details ==
> 
> Series: series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
> URL   : https://patchwork.freedesktop.org/series/47328/
> State : failure
> 
> == Summary ==
> 
> = CI Bug Log - changes from CI_DRM_4559 -> Patchwork_9788 =
> 
> == Summary - FAILURE ==
> 
>   Serious unknown changes coming with Patchwork_9788 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_9788, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://patchwork.freedesktop.org/api/1.0/series/47328/revisions/1/mbox/
> 
> == Possible new issues ==
> 
>   Here are the unknown changes that may have been introduced in Patchwork_9788:
> 
>   === IGT changes ===
> 
>     ==== Possible regressions ====
> 
>     igt@drv_selftest@live_contexts:
>       {fi-skl-iommu}:     PASS -> DMESG-FAIL

Ok, just guc related explosions. Are you happy that these are the usual
explosions? They do look like the usual fallout to me.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used.
  2018-07-27  8:53 ` [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used Jakub Bartmiński
@ 2018-07-27 10:20   ` Chris Wilson
  2018-07-27 12:04   ` Michal Wajdeczko
  1 sibling, 0 replies; 17+ messages in thread
From: Chris Wilson @ 2018-07-27 10:20 UTC (permalink / raw)
  To: Jakub Bartmiński, intel-gfx

Quoting Jakub Bartmiński (2018-07-27 09:53:46)
> There seems to be no reason for doing extra work on WOPCM partitioning
> in the case GuC is not used, as the partitioning will not be used by the
> intel_wopcm_init_hw function anyway.
> 
> Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_wopcm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
> index 74bf76f3fddc..09cc62b0d7ca 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -163,6 +163,9 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
>         u32 guc_wopcm_rsvd;
>         int err;
>  
> +       if (!USES_GUC(dev_priv))
> +               return 0;
> +
>         GEM_BUG_ON(!wopcm->size);

My personal preference would be that wopcm->size = 0 if !USES_GUC, but
hey ho.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT
  2018-07-27  8:53 ` [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT Jakub Bartmiński
@ 2018-07-27 10:29   ` Chris Wilson
  2018-07-27 12:03     ` Michal Wajdeczko
  0 siblings, 1 reply; 17+ messages in thread
From: Chris Wilson @ 2018-07-27 10:29 UTC (permalink / raw)
  To: Jakub Bartmiński, intel-gfx

Quoting Jakub Bartmiński (2018-07-27 09:53:47)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d0acef299b9c..8ac5214b3648 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2917,6 +2917,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>         struct drm_mm_node *entry;
>         int ret;
>  
> +       /*
> +        * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
> +        * present or not in use we still need a small bias as ring wraparound
> +        * at offset 0 sometimes hangs. No idea why.
> +        */
> +       ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
> +                              intel_guc_wopcm_region_size(&dev_priv->guc));

Hmm, it feels like this should fit in with ggtt_init_hw, but the current
setup makes that impossible.

intel_guc_wopcm_region_size() is a peculiar path to access
dev_priv->wopcm.

Do we not want something like intel_wopcm_lower_reserved_size()?

> +/**
> + * intel_guc_wopcm_region_size() - Get the size of the GuC region of WOPCM.
> + * @guc: intel_guc structure.
> + *
> + * Returns:
> + * 0 if GuC is not present or not in use.
> + * Otherwise, the GuC WOPCM size.
> + */
> +u32 intel_guc_wopcm_region_size(struct intel_guc *guc)
> +{
> +       struct intel_wopcm *wopcm = &guc_to_i915(guc)->wopcm;
> +
> +       /* WOPCM must have already been partitioned */
> +       GEM_BUG_ON(!wopcm->size);

Unrelated bug-on, since what you want is a statement that
intel_wopcm_init() was called and that doesn't provide it.
-Chris
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^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v6 4/6] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context
  2018-07-27  8:53 ` [PATCH v6 4/6] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context Jakub Bartmiński
@ 2018-07-27 10:30   ` Chris Wilson
  0 siblings, 0 replies; 17+ messages in thread
From: Chris Wilson @ 2018-07-27 10:30 UTC (permalink / raw)
  To: Jakub Bartmiński, intel-gfx

Quoting Jakub Bartmiński (2018-07-27 09:53:48)
> Since ggtt_offset_bias is now stored in ggtt.pin_bias, it is duplicated
> inside i915_gem_context, and can instead be accessed directly from ggtt.
> 
> v3:
> Added a helper function to retrieve the ggtt.pin_bias from the vma.
> 
> v4:
> Moved the helper function to the previous patch in the series.
> Dropped the bias from intel_ring_pin. This introduces a slight functional
> change since we are always pinning the ring a bit higher if GuC is present
> even though we don't really need to.
> 
> Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: ✗ Fi.CI.BAT: failure for series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias
  2018-07-27  9:51   ` Chris Wilson
@ 2018-07-27 10:32     ` Bartminski, Jakub
  0 siblings, 0 replies; 17+ messages in thread
From: Bartminski, Jakub @ 2018-07-27 10:32 UTC (permalink / raw)
  To: intel-gfx, chris, patchwork


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On Fri, 2018-07-27 at 10:51 +0100, Chris Wilson wrote:
> Quoting Patchwork (2018-07-27 10:35:57)
> > == Series Details ==
> > 
> > Series: series starting with [v6,1/6] drm/i915/guc: Avoid wasting
> > memory on incorrect GuC pin bias
> > URL   : https://patchwork.freedesktop.org/series/47328/
> > State : failure
> > 
> > == Summary ==
> > 
> > = CI Bug Log - changes from CI_DRM_4559 -> Patchwork_9788 =
> > 
> > == Summary - FAILURE ==
> > 
> >   Serious unknown changes coming with Patchwork_9788 absolutely
> > need to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the
> > changes
> >   introduced in Patchwork_9788, please notify your bug team to
> > allow them
> >   to document this new failure mode, which will reduce false
> > positives in CI.
> > 
> >   External URL: https://patchwork.freedesktop.org/api/1.0/series/47
> > 328/revisions/1/mbox/
> > 
> > == Possible new issues ==
> > 
> >   Here are the unknown changes that may have been introduced in
> > Patchwork_9788:
> > 
> >   === IGT changes ===
> > 
> >     ==== Possible regressions ====
> > 
> >     igt@drv_selftest@live_contexts:
> >       {fi-skl-iommu}:     PASS -> DMESG-FAIL
> 
> Ok, just guc related explosions. Are you happy that these are the
> usual
> explosions? They do look like the usual fallout to me.
> -Chris

The series does not cause them, enabling the GuC does. We're not happy
that this happens, but it's unrelated to the assert failure, and thus
something to be fixed later on.
- Jakub

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^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT
  2018-07-27 10:29   ` Chris Wilson
@ 2018-07-27 12:03     ` Michal Wajdeczko
  2018-07-27 12:07       ` Chris Wilson
  0 siblings, 1 reply; 17+ messages in thread
From: Michal Wajdeczko @ 2018-07-27 12:03 UTC (permalink / raw)
  To: Jakub Bartmiński, intel-gfx, Chris Wilson

On Fri, 27 Jul 2018 12:29:15 +0200, Chris Wilson  
<chris@chris-wilson.co.uk> wrote:

> Quoting Jakub Bartmiński (2018-07-27 09:53:47)
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c  
>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index d0acef299b9c..8ac5214b3648 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2917,6 +2917,14 @@ int i915_gem_init_ggtt(struct drm_i915_private  
>> *dev_priv)
>>         struct drm_mm_node *entry;
>>         int ret;
>>
>> +       /*
>> +        * GuC requires the ring to be placed in Non-WOPCM memory. If  
>> GuC is not
>> +        * present or not in use we still need a small bias as ring  
>> wraparound
>> +        * at offset 0 sometimes hangs. No idea why.
>> +        */
>> +       ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
>> +                               
>> intel_guc_wopcm_region_size(&dev_priv->guc));
>
> Hmm, it feels like this should fit in with ggtt_init_hw, but the current
> setup makes that impossible.
>
> intel_guc_wopcm_region_size() is a peculiar path to access
> dev_priv->wopcm.
>
> Do we not want something like intel_wopcm_lower_reserved_size()?

Earlier I was suggesting intel_guc_get_ggtt_pin_bias() as we should not
care how bias this is related to wopcm - only GuC should know that.

>
>> +/**
>> + * intel_guc_wopcm_region_size() - Get the size of the GuC region of  
>> WOPCM.
>> + * @guc: intel_guc structure.
>> + *
>> + * Returns:
>> + * 0 if GuC is not present or not in use.
>> + * Otherwise, the GuC WOPCM size.
>> + */
>> +u32 intel_guc_wopcm_region_size(struct intel_guc *guc)
>> +{
>> +       struct intel_wopcm *wopcm = &guc_to_i915(guc)->wopcm;
>> +
>> +       /* WOPCM must have already been partitioned */
>> +       GEM_BUG_ON(!wopcm->size);
>
> Unrelated bug-on, since what you want is a statement that
> intel_wopcm_init() was called and that doesn't provide it.

I guess GEM_BUG_ON(!wopcm->guc.size) should be better here.

Michal
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^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used.
  2018-07-27  8:53 ` [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used Jakub Bartmiński
  2018-07-27 10:20   ` Chris Wilson
@ 2018-07-27 12:04   ` Michal Wajdeczko
  1 sibling, 0 replies; 17+ messages in thread
From: Michal Wajdeczko @ 2018-07-27 12:04 UTC (permalink / raw)
  To: intel-gfx, Jakub Bartmiński

On Fri, 27 Jul 2018 10:53:46 +0200, Jakub Bartmiński  
<jakub.bartminski@intel.com> wrote:

> There seems to be no reason for doing extra work on WOPCM partitioning
> in the case GuC is not used, as the partitioning will not be used by the
> intel_wopcm_init_hw function anyway.
>
> Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v6 5/6] drm/i915: Add a fault injection point to WOPCM init
  2018-07-27  8:53 ` [PATCH v6 5/6] drm/i915: Add a fault injection point to WOPCM init Jakub Bartmiński
@ 2018-07-27 12:06   ` Michal Wajdeczko
  0 siblings, 0 replies; 17+ messages in thread
From: Michal Wajdeczko @ 2018-07-27 12:06 UTC (permalink / raw)
  To: intel-gfx, Jakub Bartmiński

On Fri, 27 Jul 2018 10:53:49 +0200, Jakub Bartmiński  
<jakub.bartminski@intel.com> wrote:

> Add a fault injection point in the WOPCM initialization path.
>
> v4:
> Move the injection inside the WOPCM init function.
>
> Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT
  2018-07-27 12:03     ` Michal Wajdeczko
@ 2018-07-27 12:07       ` Chris Wilson
  0 siblings, 0 replies; 17+ messages in thread
From: Chris Wilson @ 2018-07-27 12:07 UTC (permalink / raw)
  To: Jakub Bartmiński, Michal Wajdeczko, intel-gfx

Quoting Michal Wajdeczko (2018-07-27 13:03:14)
> On Fri, 27 Jul 2018 12:29:15 +0200, Chris Wilson  
> <chris@chris-wilson.co.uk> wrote:
> 
> > Quoting Jakub Bartmiński (2018-07-27 09:53:47)
> >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c  
> >> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> index d0acef299b9c..8ac5214b3648 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> @@ -2917,6 +2917,14 @@ int i915_gem_init_ggtt(struct drm_i915_private  
> >> *dev_priv)
> >>         struct drm_mm_node *entry;
> >>         int ret;
> >>
> >> +       /*
> >> +        * GuC requires the ring to be placed in Non-WOPCM memory. If  
> >> GuC is not
> >> +        * present or not in use we still need a small bias as ring  
> >> wraparound
> >> +        * at offset 0 sometimes hangs. No idea why.
> >> +        */
> >> +       ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
> >> +                               
> >> intel_guc_wopcm_region_size(&dev_priv->guc));
> >
> > Hmm, it feels like this should fit in with ggtt_init_hw, but the current
> > setup makes that impossible.
> >
> > intel_guc_wopcm_region_size() is a peculiar path to access
> > dev_priv->wopcm.
> >
> > Do we not want something like intel_wopcm_lower_reserved_size()?
> 
> Earlier I was suggesting intel_guc_get_ggtt_pin_bias() as we should not
> care how bias this is related to wopcm - only GuC should know that.

:) Here I only care that the reason we exclude anything from the GGTT is
self-evident.

	intel_guc_reserved_gtt_size();
	intel_wopcm_reserved_gtt_size();

make more sense to me as to why we would even have a 
ggtt->pin_bias = intel_X_reserved_gtt_size() here.
-Chris
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^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2018-07-27 12:08 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-27  8:53 [PATCH v6 1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Jakub Bartmiński
2018-07-27  8:53 ` [PATCH v6 2/6] drm/i915/guc: Do not partition WOPCM if GuC is not used Jakub Bartmiński
2018-07-27 10:20   ` Chris Wilson
2018-07-27 12:04   ` Michal Wajdeczko
2018-07-27  8:53 ` [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT Jakub Bartmiński
2018-07-27 10:29   ` Chris Wilson
2018-07-27 12:03     ` Michal Wajdeczko
2018-07-27 12:07       ` Chris Wilson
2018-07-27  8:53 ` [PATCH v6 4/6] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context Jakub Bartmiński
2018-07-27 10:30   ` Chris Wilson
2018-07-27  8:53 ` [PATCH v6 5/6] drm/i915: Add a fault injection point to WOPCM init Jakub Bartmiński
2018-07-27 12:06   ` Michal Wajdeczko
2018-07-27  8:53 ` [PATCH v6 6/6] HAX enable GuC for CI Jakub Bartmiński
2018-07-27  9:16 ` ✗ Fi.CI.SPARSE: warning for series starting with [v6,1/6] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias Patchwork
2018-07-27  9:35 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-07-27  9:51   ` Chris Wilson
2018-07-27 10:32     ` Bartminski, Jakub

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