* [Intel-xe] [PATCH] drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+
@ 2023-10-06 16:50 José Roberto de Souza
2023-10-06 17:16 ` Lucas De Marchi
2023-10-06 17:49 ` [Intel-xe] ✗ CI.Patch_applied: failure for " Patchwork
0 siblings, 2 replies; 5+ messages in thread
From: José Roberto de Souza @ 2023-10-06 16:50 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi
PIPE_CONTROL_TILE_CACHE_FLUSH/bit 28 is now reserved bit in PIPE_CONTROL
instruction for gfx20+, so here only setting it for older graphics
versions.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/xe/xe_ring_ops.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 6eec7c7e4bc56..c2aec32fc46ad 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -157,16 +157,19 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
{
struct xe_gt *gt = job->q->gt;
+ struct xe_device *xe = gt->tile->xe;
bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
u32 flags;
flags = (PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
+ if (GRAPHICS_VERx100(xe) < 2000)
+ flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
+
if (XE_WA(gt, 1409600907))
flags |= PIPE_CONTROL_DEPTH_STALL;
--
2.42.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-xe] [PATCH] drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+
2023-10-06 16:50 [Intel-xe] [PATCH] drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+ José Roberto de Souza
@ 2023-10-06 17:16 ` Lucas De Marchi
2023-10-06 17:23 ` Souza, Jose
2023-10-06 17:49 ` [Intel-xe] ✗ CI.Patch_applied: failure for " Patchwork
1 sibling, 1 reply; 5+ messages in thread
From: Lucas De Marchi @ 2023-10-06 17:16 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-xe
On Fri, Oct 06, 2023 at 09:50:53AM -0700, Jose Souza wrote:
>PIPE_CONTROL_TILE_CACHE_FLUSH/bit 28 is now reserved bit in PIPE_CONTROL
>instruction for gfx20+, so here only setting it for older graphics
>versions.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/xe/xe_ring_ops.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
>index 6eec7c7e4bc56..c2aec32fc46ad 100644
>--- a/drivers/gpu/drm/xe/xe_ring_ops.c
>+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>@@ -157,16 +157,19 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
> static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
> {
> struct xe_gt *gt = job->q->gt;
>+ struct xe_device *xe = gt->tile->xe;
gt_to_xe()
> bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
> u32 flags;
>
> flags = (PIPE_CONTROL_CS_STALL |
>- PIPE_CONTROL_TILE_CACHE_FLUSH |
> PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> PIPE_CONTROL_DC_FLUSH_ENABLE |
> PIPE_CONTROL_FLUSH_ENABLE);
>
>+ if (GRAPHICS_VERx100(xe) < 2000)
>+ flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
Looks correct that it doesn't exist in xe2. But looking at bspec 56551,
it doesn't seem it can't be set, but rather that it doesn't have any
effect on xe2. Is this not the case?
Lucas De Marchi
>+
> if (XE_WA(gt, 1409600907))
> flags |= PIPE_CONTROL_DEPTH_STALL;
>
>--
>2.42.0
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-xe] [PATCH] drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+
2023-10-06 17:16 ` Lucas De Marchi
@ 2023-10-06 17:23 ` Souza, Jose
2023-10-06 20:56 ` Lucas De Marchi
0 siblings, 1 reply; 5+ messages in thread
From: Souza, Jose @ 2023-10-06 17:23 UTC (permalink / raw)
To: De Marchi, Lucas; +Cc: intel-xe
On Fri, 2023-10-06 at 12:16 -0500, Lucas De Marchi wrote:
> On Fri, Oct 06, 2023 at 09:50:53AM -0700, Jose Souza wrote:
> > PIPE_CONTROL_TILE_CACHE_FLUSH/bit 28 is now reserved bit in PIPE_CONTROL
> > instruction for gfx20+, so here only setting it for older graphics
> > versions.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_ring_ops.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> > index 6eec7c7e4bc56..c2aec32fc46ad 100644
> > --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> > +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> > @@ -157,16 +157,19 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
> > static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
> > {
> > struct xe_gt *gt = job->q->gt;
> > + struct xe_device *xe = gt->tile->xe;
>
> gt_to_xe()
>
> > bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
> > u32 flags;
> >
> > flags = (PIPE_CONTROL_CS_STALL |
> > - PIPE_CONTROL_TILE_CACHE_FLUSH |
> > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> > PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> > PIPE_CONTROL_DC_FLUSH_ENABLE |
> > PIPE_CONTROL_FLUSH_ENABLE);
> >
> > + if (GRAPHICS_VERx100(xe) < 2000)
> > + flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
>
> Looks correct that it doesn't exist in xe2. But looking at bspec 56551,
> it doesn't seem it can't be set, but rather that it doesn't have any
> effect on xe2. Is this not the case?
Yeah I don't see any tests failing because this bit is set in Xe or Mesa but better not set reserved bits.
>
> Lucas De Marchi
>
> > +
> > if (XE_WA(gt, 1409600907))
> > flags |= PIPE_CONTROL_DEPTH_STALL;
> >
> > --
> > 2.42.0
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-xe] ✗ CI.Patch_applied: failure for drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+
2023-10-06 16:50 [Intel-xe] [PATCH] drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+ José Roberto de Souza
2023-10-06 17:16 ` Lucas De Marchi
@ 2023-10-06 17:49 ` Patchwork
1 sibling, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-10-06 17:49 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+
URL : https://patchwork.freedesktop.org/series/124739/
State : failure
== Summary ==
=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: f1b61d7d4 drm/xe: add gt tuning for indirect state
=== git am output follows ===
Applying: drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-xe] [PATCH] drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+
2023-10-06 17:23 ` Souza, Jose
@ 2023-10-06 20:56 ` Lucas De Marchi
0 siblings, 0 replies; 5+ messages in thread
From: Lucas De Marchi @ 2023-10-06 20:56 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-xe
On Fri, Oct 06, 2023 at 05:23:36PM +0000, Jose Souza wrote:
>On Fri, 2023-10-06 at 12:16 -0500, Lucas De Marchi wrote:
>> On Fri, Oct 06, 2023 at 09:50:53AM -0700, Jose Souza wrote:
>> > PIPE_CONTROL_TILE_CACHE_FLUSH/bit 28 is now reserved bit in PIPE_CONTROL
>> > instruction for gfx20+, so here only setting it for older graphics
>> > versions.
>> >
>> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> > ---
>> > drivers/gpu/drm/xe/xe_ring_ops.c | 5 ++++-
>> > 1 file changed, 4 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
>> > index 6eec7c7e4bc56..c2aec32fc46ad 100644
>> > --- a/drivers/gpu/drm/xe/xe_ring_ops.c
>> > +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>> > @@ -157,16 +157,19 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
>> > static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
>> > {
>> > struct xe_gt *gt = job->q->gt;
>> > + struct xe_device *xe = gt->tile->xe;
>>
>> gt_to_xe()
>>
>> > bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
>> > u32 flags;
>> >
>> > flags = (PIPE_CONTROL_CS_STALL |
>> > - PIPE_CONTROL_TILE_CACHE_FLUSH |
>> > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
>> > PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>> > PIPE_CONTROL_DC_FLUSH_ENABLE |
>> > PIPE_CONTROL_FLUSH_ENABLE);
>> >
>> > + if (GRAPHICS_VERx100(xe) < 2000)
>> > + flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
>>
>> Looks correct that it doesn't exist in xe2. But looking at bspec 56551,
>> it doesn't seem it can't be set, but rather that it doesn't have any
>> effect on xe2. Is this not the case?
>
>Yeah I don't see any tests failing because this bit is set in Xe or Mesa but better not set reserved bits.
Why better? We do that all the time in the driver when the bit is just
"not valid for the platform" rather than "can't be set". When it's
explicitely marked as reserved then it's a case by case analysis.
Lucas De Marchi
>
>>
>> Lucas De Marchi
>>
>> > +
>> > if (XE_WA(gt, 1409600907))
>> > flags |= PIPE_CONTROL_DEPTH_STALL;
>> >
>> > --
>> > 2.42.0
>> >
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-10-06 20:56 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2023-10-06 16:50 [Intel-xe] [PATCH] drm/xe: Remove PIPE_CONTROL_TILE_CACHE_FLUSH from PIPE_CONTROL in gfx20+ José Roberto de Souza
2023-10-06 17:16 ` Lucas De Marchi
2023-10-06 17:23 ` Souza, Jose
2023-10-06 20:56 ` Lucas De Marchi
2023-10-06 17:49 ` [Intel-xe] ✗ CI.Patch_applied: failure for " Patchwork
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