* [PATCH v6 00/11] riscv: add initial support for Canaan Kendryte K230
@ 2024-03-23 12:09 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:09 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
K230 is an ideal chip for RISC-V Vector 1.0 evaluation now. Add initial
support for it to allow more people to participate in building drivers
to mainline for it.
This kernel has been tested upon factory SDK [1] with
k230_evb_only_linux_defconfig and patched mainline opensbi [2] to skip
locked pmp and successfully booted to busybox on initrd with this log [3].
[1] https://github.com/kendryte/k230_sdk
[2] https://github.com/cyyself/opensbi/tree/k230
[3] https://gist.github.com/cyyself/b9445f38cc3ba1094924bd41c9086176
Changes since v5:
- Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210 SoCs
- Modify existing K210 drivers depends on SOC_CANAAN_K210 symbol
- Reword dts commit message
- Modify dts to use Full 512MB memory
- Rebase to linux mainline master
Changes since v4:
- Reword commit message on dts that the B-ext version of c908 is 1.0 rather
than 1.0-rc1
v4: https://lore.kernel.org/linux-riscv/tencent_587730262984A011834F42D0563BC6B10405@qq.com/
Changes since v3:
- Refactor Kconfig.soc which uses ARCH_CANAAN for regular Canaan SoCs and
rename SOC_CANAAN to SOC_CANAAN_K210 for K210 in patch [5/7]
- Sort dt-binding stings on Cannan SoCs in alphanumerical order
v3: https://lore.kernel.org/linux-riscv/tencent_BB2364BBF1812F4E304F7BDDD11E57356605@qq.com/
Changes since v2:
- Add MIT License to dts file
- Sort dt-binding stings in alphanumerical order
- Sort filename in dts Makefile in alphanumerical order
- Rename canmv-k230.dts to k230-canmv.dts
v2: https://lore.kernel.org/linux-riscv/tencent_64A9B4B31C2D70D5633042461AC9F80C0509@qq.com/
Changes since v1:
- Patch dt-bindings in clint and plic
- Use enum in K230 compatible dt bindings
- Fix dts to pass `make dtbs_check`
- Add more details in commit message
v1: https://lore.kernel.org/linux-riscv/tencent_E15F8FE0B6769E6338AE690C7F4844A31706@qq.com/
Yangyu Chen (11):
dt-bindings: riscv: Add T-HEAD C908 compatible
dt-bindings: add Canaan K230 boards compatible strings
dt-bindings: timer: Add Canaan K230 CLINT
dt-bindings: interrupt-controller: Add Canaan K230 PLIC
riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
soc: canaan: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210
clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
riscv: dts: add initial canmv-k230 and k230-evb dts
riscv: config: enable ARCH_CANAAN in defconfig
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/canaan.yaml | 8 +-
.../devicetree/bindings/riscv/cpus.yaml | 1 +
.../bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/Kconfig.socs | 8 +-
arch/riscv/Makefile | 2 +-
arch/riscv/boot/dts/canaan/Makefile | 2 +
arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 +++
arch/riscv/boot/dts/canaan/k230-evb.dts | 24 +++
arch/riscv/boot/dts/canaan/k230.dtsi | 140 ++++++++++++++++++
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/nommu_k210_defconfig | 3 +-
.../riscv/configs/nommu_k210_sdcard_defconfig | 3 +-
drivers/clk/Kconfig | 4 +-
drivers/pinctrl/Kconfig | 4 +-
drivers/reset/Kconfig | 4 +-
drivers/soc/Makefile | 2 +-
drivers/soc/canaan/Kconfig | 4 +-
18 files changed, 220 insertions(+), 16 deletions(-)
create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
base-commit: 8e938e39866920ddc266898e6ae1fffc5c8f51aa
--
2.43.0
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v6 01/11] dt-bindings: riscv: Add T-HEAD C908 compatible
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Conor Dooley
The thead,c908 is a RISC-V CPU core from T-HEAD Semiconductor which used
in Canaan Kendryte K230 SoC.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index b252c3966b8b..02f939449e54 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
- sifive,u74
- sifive,u74-mc
- thead,c906
+ - thead,c908
- thead,c910
- thead,c920
- const: riscv
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 01/11] dt-bindings: riscv: Add T-HEAD C908 compatible
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Conor Dooley
The thead,c908 is a RISC-V CPU core from T-HEAD Semiconductor which used
in Canaan Kendryte K230 SoC.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index b252c3966b8b..02f939449e54 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
- sifive,u74
- sifive,u74-mc
- thead,c906
+ - thead,c908
- thead,c910
- thead,c920
- const: riscv
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 02/11] dt-bindings: add Canaan K230 boards compatible strings
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Krzysztof Kozlowski
Since K230 was released, K210 is no longer the only SoC in the Kendryte
series, so remove the K210 string from the description. Also, add two
boards based on k230 to compatible strings to allow them to be used in the
dt.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
---
Documentation/devicetree/bindings/riscv/canaan.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml
index 41fd11f70a49..f9854ff43ac6 100644
--- a/Documentation/devicetree/bindings/riscv/canaan.yaml
+++ b/Documentation/devicetree/bindings/riscv/canaan.yaml
@@ -10,7 +10,7 @@ maintainers:
- Damien Le Moal <dlemoal@kernel.org>
description:
- Canaan Kendryte K210 SoC-based boards
+ Canaan Kendryte SoC-based boards
properties:
$nodename:
@@ -42,6 +42,12 @@ properties:
- items:
- const: canaan,kendryte-k210
+ - items:
+ - enum:
+ - canaan,canmv-k230
+ - canaan,k230-usip-lp3-evb
+ - const: canaan,kendryte-k230
+
additionalProperties: true
...
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 02/11] dt-bindings: add Canaan K230 boards compatible strings
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Krzysztof Kozlowski
Since K230 was released, K210 is no longer the only SoC in the Kendryte
series, so remove the K210 string from the description. Also, add two
boards based on k230 to compatible strings to allow them to be used in the
dt.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
---
Documentation/devicetree/bindings/riscv/canaan.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml
index 41fd11f70a49..f9854ff43ac6 100644
--- a/Documentation/devicetree/bindings/riscv/canaan.yaml
+++ b/Documentation/devicetree/bindings/riscv/canaan.yaml
@@ -10,7 +10,7 @@ maintainers:
- Damien Le Moal <dlemoal@kernel.org>
description:
- Canaan Kendryte K210 SoC-based boards
+ Canaan Kendryte SoC-based boards
properties:
$nodename:
@@ -42,6 +42,12 @@ properties:
- items:
- const: canaan,kendryte-k210
+ - items:
+ - enum:
+ - canaan,canmv-k230
+ - canaan,k230-usip-lp3-evb
+ - const: canaan,kendryte-k230
+
additionalProperties: true
...
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 03/11] dt-bindings: timer: Add Canaan K230 CLINT
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Rob Herring
Add compatible string for Canaan K230 CLINT.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index fced6f2d8ecb..06c67f20ad3c 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -38,6 +38,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-clint
+ - canaan,k230-clint
- sophgo,cv1800b-clint
- sophgo,cv1812h-clint
- thead,th1520-clint
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 03/11] dt-bindings: timer: Add Canaan K230 CLINT
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Rob Herring
Add compatible string for Canaan K230 CLINT.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index fced6f2d8ecb..06c67f20ad3c 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -38,6 +38,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-clint
+ - canaan,k230-clint
- sophgo,cv1800b-clint
- sophgo,cv1812h-clint
- thead,th1520-clint
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 04/11] dt-bindings: interrupt-controller: Add Canaan K230 PLIC
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Rob Herring
Add compatible string for Canaan K230 PLIC.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 709b2211276b..122f9b7b3f52 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -65,6 +65,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-plic
+ - canaan,k230-plic
- sophgo,cv1800b-plic
- sophgo,cv1812h-plic
- sophgo,sg2042-plic
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 04/11] dt-bindings: interrupt-controller: Add Canaan K230 PLIC
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Rob Herring
Add compatible string for Canaan K230 PLIC.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 709b2211276b..122f9b7b3f52 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -65,6 +65,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-plic
+ - canaan,k230-plic
- sophgo,cv1800b-plic
- sophgo,cv1812h-plic
- sophgo,sg2042-plic
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 05/11] riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4], we remove the use of
SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from
now on. And allows ARCH_CANAAN to be selected for other Canaan SoCs.
Then, since we have Canaan Kendryte K230 with MMU now, the use of
SOC_CANAAN is no longer only referred to K210. Thus, we introduce a new
symbol SOC_CANAAN_K210 for any conditional code or driver selection
specific to the K210, so users will not try to build some K210-specific
things when MMU is enabled and see it fails to boot on K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
arch/riscv/Kconfig.socs | 8 +++++---
arch/riscv/Makefile | 2 +-
arch/riscv/configs/nommu_k210_defconfig | 3 ++-
arch/riscv/configs/nommu_k210_sdcard_defconfig | 3 ++-
4 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 623de5f8a208..5710aee456ac 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -72,11 +72,13 @@ config SOC_VIRT
This enables support for QEMU Virt Machine.
config ARCH_CANAAN
- def_bool SOC_CANAAN
+ bool "Canaan Kendryte SoC"
+ help
+ This enables support for Canaan Kendryte SoC platform hardware.
-config SOC_CANAAN
+config SOC_CANAAN_K210
bool "Canaan Kendryte K210 SoC"
- depends on !MMU
+ depends on !MMU && ARCH_CANAAN
select CLINT_TIMER if RISCV_M_MODE
select ARCH_HAS_RESET_CONTROLLER
select PINCTRL
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0b7d109258e7..294b2b3e8e6a 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -149,7 +149,7 @@ vdso-install-y += arch/riscv/kernel/vdso/vdso.so.dbg
vdso-install-$(CONFIG_COMPAT) += arch/riscv/kernel/compat_vdso/compat_vdso.so.dbg:../compat_vdso/compat_vdso.so
ifneq ($(CONFIG_XIP_KERNEL),y)
-ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy)
+ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN_K210),yy)
KBUILD_IMAGE := $(boot)/loader.bin
else
ifeq ($(CONFIG_EFI_ZBOOT),)
diff --git a/arch/riscv/configs/nommu_k210_defconfig b/arch/riscv/configs/nommu_k210_defconfig
index 7e75200543f4..2552e78074a3 100644
--- a/arch/riscv/configs/nommu_k210_defconfig
+++ b/arch/riscv/configs/nommu_k210_defconfig
@@ -27,7 +27,8 @@ CONFIG_EXPERT=y
CONFIG_SLUB=y
CONFIG_SLUB_TINY=y
# CONFIG_MMU is not set
-CONFIG_SOC_CANAAN=y
+CONFIG_ARCH_CANAAN=y
+CONFIG_SOC_CANAAN_K210=y
CONFIG_NONPORTABLE=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
diff --git a/arch/riscv/configs/nommu_k210_sdcard_defconfig b/arch/riscv/configs/nommu_k210_sdcard_defconfig
index 0ba353e9ca71..8f67fb830585 100644
--- a/arch/riscv/configs/nommu_k210_sdcard_defconfig
+++ b/arch/riscv/configs/nommu_k210_sdcard_defconfig
@@ -19,7 +19,8 @@ CONFIG_EXPERT=y
CONFIG_SLUB=y
CONFIG_SLUB_TINY=y
# CONFIG_MMU is not set
-CONFIG_SOC_CANAAN=y
+CONFIG_ARCH_CANAAN=y
+CONFIG_SOC_CANAAN_K210=y
CONFIG_NONPORTABLE=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 05/11] riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4], we remove the use of
SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from
now on. And allows ARCH_CANAAN to be selected for other Canaan SoCs.
Then, since we have Canaan Kendryte K230 with MMU now, the use of
SOC_CANAAN is no longer only referred to K210. Thus, we introduce a new
symbol SOC_CANAAN_K210 for any conditional code or driver selection
specific to the K210, so users will not try to build some K210-specific
things when MMU is enabled and see it fails to boot on K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
arch/riscv/Kconfig.socs | 8 +++++---
arch/riscv/Makefile | 2 +-
arch/riscv/configs/nommu_k210_defconfig | 3 ++-
arch/riscv/configs/nommu_k210_sdcard_defconfig | 3 ++-
4 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 623de5f8a208..5710aee456ac 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -72,11 +72,13 @@ config SOC_VIRT
This enables support for QEMU Virt Machine.
config ARCH_CANAAN
- def_bool SOC_CANAAN
+ bool "Canaan Kendryte SoC"
+ help
+ This enables support for Canaan Kendryte SoC platform hardware.
-config SOC_CANAAN
+config SOC_CANAAN_K210
bool "Canaan Kendryte K210 SoC"
- depends on !MMU
+ depends on !MMU && ARCH_CANAAN
select CLINT_TIMER if RISCV_M_MODE
select ARCH_HAS_RESET_CONTROLLER
select PINCTRL
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0b7d109258e7..294b2b3e8e6a 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -149,7 +149,7 @@ vdso-install-y += arch/riscv/kernel/vdso/vdso.so.dbg
vdso-install-$(CONFIG_COMPAT) += arch/riscv/kernel/compat_vdso/compat_vdso.so.dbg:../compat_vdso/compat_vdso.so
ifneq ($(CONFIG_XIP_KERNEL),y)
-ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy)
+ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN_K210),yy)
KBUILD_IMAGE := $(boot)/loader.bin
else
ifeq ($(CONFIG_EFI_ZBOOT),)
diff --git a/arch/riscv/configs/nommu_k210_defconfig b/arch/riscv/configs/nommu_k210_defconfig
index 7e75200543f4..2552e78074a3 100644
--- a/arch/riscv/configs/nommu_k210_defconfig
+++ b/arch/riscv/configs/nommu_k210_defconfig
@@ -27,7 +27,8 @@ CONFIG_EXPERT=y
CONFIG_SLUB=y
CONFIG_SLUB_TINY=y
# CONFIG_MMU is not set
-CONFIG_SOC_CANAAN=y
+CONFIG_ARCH_CANAAN=y
+CONFIG_SOC_CANAAN_K210=y
CONFIG_NONPORTABLE=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
diff --git a/arch/riscv/configs/nommu_k210_sdcard_defconfig b/arch/riscv/configs/nommu_k210_sdcard_defconfig
index 0ba353e9ca71..8f67fb830585 100644
--- a/arch/riscv/configs/nommu_k210_sdcard_defconfig
+++ b/arch/riscv/configs/nommu_k210_sdcard_defconfig
@@ -19,7 +19,8 @@ CONFIG_EXPERT=y
CONFIG_SLUB=y
CONFIG_SLUB_TINY=y
# CONFIG_MMU is not set
-CONFIG_SOC_CANAAN=y
+CONFIG_ARCH_CANAAN=y
+CONFIG_SOC_CANAAN_K210=y
CONFIG_NONPORTABLE=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* Re: [PATCH v6 05/11] riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
2024-03-23 12:12 ` Yangyu Chen
@ 2024-03-25 10:52 ` Dan Carpenter
-1 siblings, 0 replies; 54+ messages in thread
From: Dan Carpenter @ 2024-03-25 10:52 UTC (permalink / raw)
To: Yangyu Chen
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
On Sat, Mar 23, 2024 at 08:12:17PM +0800, Yangyu Chen wrote:
> Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> SoCs is already on the mailing list [2,3,4], we remove the use of
> SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from
> now on. And allows ARCH_CANAAN to be selected for other Canaan SoCs.
>
> Then, since we have Canaan Kendryte K230 with MMU now, the use of
> SOC_CANAAN is no longer only referred to K210. Thus, we introduce a new
> symbol SOC_CANAAN_K210 for any conditional code or driver selection
> specific to the K210, so users will not try to build some K210-specific
> things when MMU is enabled and see it fails to boot on K210.
>
> [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
> arch/riscv/Kconfig.socs | 8 +++++---
> arch/riscv/Makefile | 2 +-
> arch/riscv/configs/nommu_k210_defconfig | 3 ++-
> arch/riscv/configs/nommu_k210_sdcard_defconfig | 3 ++-
> 4 files changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 623de5f8a208..5710aee456ac 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -72,11 +72,13 @@ config SOC_VIRT
> This enables support for QEMU Virt Machine.
>
> config ARCH_CANAAN
> - def_bool SOC_CANAAN
> + bool "Canaan Kendryte SoC"
> + help
> + This enables support for Canaan Kendryte SoC platform hardware.
>
> -config SOC_CANAAN
> +config SOC_CANAAN_K210
This breaks git bisect, right? There are references to SOC_CANAAN that
are get updated later in the patch series. You can't delete SOC_CANAAN
and leave the other references dangling.
regards,
dan carpenter
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 05/11] riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
@ 2024-03-25 10:52 ` Dan Carpenter
0 siblings, 0 replies; 54+ messages in thread
From: Dan Carpenter @ 2024-03-25 10:52 UTC (permalink / raw)
To: Yangyu Chen
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
On Sat, Mar 23, 2024 at 08:12:17PM +0800, Yangyu Chen wrote:
> Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> SoCs is already on the mailing list [2,3,4], we remove the use of
> SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from
> now on. And allows ARCH_CANAAN to be selected for other Canaan SoCs.
>
> Then, since we have Canaan Kendryte K230 with MMU now, the use of
> SOC_CANAAN is no longer only referred to K210. Thus, we introduce a new
> symbol SOC_CANAAN_K210 for any conditional code or driver selection
> specific to the K210, so users will not try to build some K210-specific
> things when MMU is enabled and see it fails to boot on K210.
>
> [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
> arch/riscv/Kconfig.socs | 8 +++++---
> arch/riscv/Makefile | 2 +-
> arch/riscv/configs/nommu_k210_defconfig | 3 ++-
> arch/riscv/configs/nommu_k210_sdcard_defconfig | 3 ++-
> 4 files changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 623de5f8a208..5710aee456ac 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -72,11 +72,13 @@ config SOC_VIRT
> This enables support for QEMU Virt Machine.
>
> config ARCH_CANAAN
> - def_bool SOC_CANAAN
> + bool "Canaan Kendryte SoC"
> + help
> + This enables support for Canaan Kendryte SoC platform hardware.
>
> -config SOC_CANAAN
> +config SOC_CANAAN_K210
This breaks git bisect, right? There are references to SOC_CANAAN that
are get updated later in the patch series. You can't delete SOC_CANAAN
and leave the other references dangling.
regards,
dan carpenter
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 05/11] riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
2024-03-25 10:52 ` Dan Carpenter
@ 2024-03-25 11:10 ` Conor Dooley
-1 siblings, 0 replies; 54+ messages in thread
From: Conor Dooley @ 2024-03-25 11:10 UTC (permalink / raw)
To: Dan Carpenter
Cc: Yangyu Chen, linux-riscv, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 2777 bytes --]
On Mon, Mar 25, 2024 at 01:52:42PM +0300, Dan Carpenter wrote:
> On Sat, Mar 23, 2024 at 08:12:17PM +0800, Yangyu Chen wrote:
> > Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> > SoCs is already on the mailing list [2,3,4], we remove the use of
> > SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from
> > now on. And allows ARCH_CANAAN to be selected for other Canaan SoCs.
> >
> > Then, since we have Canaan Kendryte K230 with MMU now, the use of
> > SOC_CANAAN is no longer only referred to K210. Thus, we introduce a new
> > symbol SOC_CANAAN_K210 for any conditional code or driver selection
> > specific to the K210, so users will not try to build some K210-specific
> > things when MMU is enabled and see it fails to boot on K210.
> >
> > [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> > [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> > [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> > [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
> >
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > ---
> > arch/riscv/Kconfig.socs | 8 +++++---
> > arch/riscv/Makefile | 2 +-
> > arch/riscv/configs/nommu_k210_defconfig | 3 ++-
> > arch/riscv/configs/nommu_k210_sdcard_defconfig | 3 ++-
> > 4 files changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 623de5f8a208..5710aee456ac 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -72,11 +72,13 @@ config SOC_VIRT
> > This enables support for QEMU Virt Machine.
> >
> > config ARCH_CANAAN
> > - def_bool SOC_CANAAN
> > + bool "Canaan Kendryte SoC"
> > + help
> > + This enables support for Canaan Kendryte SoC platform hardware.
> >
> > -config SOC_CANAAN
> > +config SOC_CANAAN_K210
>
> This breaks git bisect, right? There are references to SOC_CANAAN that
> are get updated later in the patch series. You can't delete SOC_CANAAN
> and leave the other references dangling.
Right. I thought that I had said to resend the patch from v5 and solicit
acks to take it via the soc tree [1]. Splitting it out like this means you
have to introduce a symbol that shadows the original one and then switch
only once all references have been removed. If this series went into 6.10,
which it should, the switch would be in 6.11. I think the chances of a
meaningful conflict are low with the treewide swap so it should be safe
to do.
1 - https://lore.kernel.org/all/20240320-ideology-pasty-d3aea07cc519@spud/
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 05/11] riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
@ 2024-03-25 11:10 ` Conor Dooley
0 siblings, 0 replies; 54+ messages in thread
From: Conor Dooley @ 2024-03-25 11:10 UTC (permalink / raw)
To: Dan Carpenter
Cc: Yangyu Chen, linux-riscv, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2777 bytes --]
On Mon, Mar 25, 2024 at 01:52:42PM +0300, Dan Carpenter wrote:
> On Sat, Mar 23, 2024 at 08:12:17PM +0800, Yangyu Chen wrote:
> > Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> > SoCs is already on the mailing list [2,3,4], we remove the use of
> > SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from
> > now on. And allows ARCH_CANAAN to be selected for other Canaan SoCs.
> >
> > Then, since we have Canaan Kendryte K230 with MMU now, the use of
> > SOC_CANAAN is no longer only referred to K210. Thus, we introduce a new
> > symbol SOC_CANAAN_K210 for any conditional code or driver selection
> > specific to the K210, so users will not try to build some K210-specific
> > things when MMU is enabled and see it fails to boot on K210.
> >
> > [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> > [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> > [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> > [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
> >
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > ---
> > arch/riscv/Kconfig.socs | 8 +++++---
> > arch/riscv/Makefile | 2 +-
> > arch/riscv/configs/nommu_k210_defconfig | 3 ++-
> > arch/riscv/configs/nommu_k210_sdcard_defconfig | 3 ++-
> > 4 files changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 623de5f8a208..5710aee456ac 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -72,11 +72,13 @@ config SOC_VIRT
> > This enables support for QEMU Virt Machine.
> >
> > config ARCH_CANAAN
> > - def_bool SOC_CANAAN
> > + bool "Canaan Kendryte SoC"
> > + help
> > + This enables support for Canaan Kendryte SoC platform hardware.
> >
> > -config SOC_CANAAN
> > +config SOC_CANAAN_K210
>
> This breaks git bisect, right? There are references to SOC_CANAAN that
> are get updated later in the patch series. You can't delete SOC_CANAAN
> and leave the other references dangling.
Right. I thought that I had said to resend the patch from v5 and solicit
acks to take it via the soc tree [1]. Splitting it out like this means you
have to introduce a symbol that shadows the original one and then switch
only once all references have been removed. If this series went into 6.10,
which it should, the switch would be in 6.11. I think the chances of a
meaningful conflict are low with the treewide swap so it should be safe
to do.
1 - https://lore.kernel.org/all/20240320-ideology-pasty-d3aea07cc519@spud/
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v6 06/11] soc: canaan: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4], we remove the use of
SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from now
on. Thus, we should also change the Makefile here to use ARCH_CANAAN.
Then, since we have introduced SOC_CANAAN_K210 for K210-specific drivers,
we should replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
drivers/soc/Makefile | 2 +-
drivers/soc/canaan/Kconfig | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index ba8f5b5460e1..fb2bd31387d0 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -7,7 +7,7 @@ obj-y += apple/
obj-y += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
obj-y += bcm/
-obj-$(CONFIG_SOC_CANAAN) += canaan/
+obj-$(CONFIG_ARCH_CANAAN) += canaan/
obj-$(CONFIG_ARCH_DOVE) += dove/
obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += fsl/
diff --git a/drivers/soc/canaan/Kconfig b/drivers/soc/canaan/Kconfig
index 43ced2bf8444..3121d351fea6 100644
--- a/drivers/soc/canaan/Kconfig
+++ b/drivers/soc/canaan/Kconfig
@@ -2,9 +2,9 @@
config SOC_K210_SYSCTL
bool "Canaan Kendryte K210 SoC system controller"
- depends on RISCV && SOC_CANAAN && OF
+ depends on RISCV && SOC_CANAAN_K210 && OF
depends on COMMON_CLK_K210
- default SOC_CANAAN
+ default SOC_CANAAN_K210
select PM
select MFD_SYSCON
help
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 06/11] soc: canaan: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4], we remove the use of
SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from now
on. Thus, we should also change the Makefile here to use ARCH_CANAAN.
Then, since we have introduced SOC_CANAAN_K210 for K210-specific drivers,
we should replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
drivers/soc/Makefile | 2 +-
drivers/soc/canaan/Kconfig | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index ba8f5b5460e1..fb2bd31387d0 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -7,7 +7,7 @@ obj-y += apple/
obj-y += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
obj-y += bcm/
-obj-$(CONFIG_SOC_CANAAN) += canaan/
+obj-$(CONFIG_ARCH_CANAAN) += canaan/
obj-$(CONFIG_ARCH_DOVE) += dove/
obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += fsl/
diff --git a/drivers/soc/canaan/Kconfig b/drivers/soc/canaan/Kconfig
index 43ced2bf8444..3121d351fea6 100644
--- a/drivers/soc/canaan/Kconfig
+++ b/drivers/soc/canaan/Kconfig
@@ -2,9 +2,9 @@
config SOC_K210_SYSCTL
bool "Canaan Kendryte K210 SoC system controller"
- depends on RISCV && SOC_CANAAN && OF
+ depends on RISCV && SOC_CANAAN_K210 && OF
depends on COMMON_CLK_K210
- default SOC_CANAAN
+ default SOC_CANAAN_K210
select PM
select MFD_SYSCON
help
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 07/11] clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4], we remove the use of
SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
drivers/clk/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 50af5fc7f570..7517a0dfd15c 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -451,8 +451,8 @@ config COMMON_CLK_FIXED_MMIO
config COMMON_CLK_K210
bool "Clock driver for the Canaan Kendryte K210 SoC"
- depends on OF && RISCV && SOC_CANAAN
- default SOC_CANAAN
+ depends on OF && RISCV && SOC_CANAAN_K210
+ default SOC_CANAAN_K210
help
Support for the Canaan Kendryte K210 RISC-V SoC clocks.
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 07/11] clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4], we remove the use of
SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
drivers/clk/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 50af5fc7f570..7517a0dfd15c 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -451,8 +451,8 @@ config COMMON_CLK_FIXED_MMIO
config COMMON_CLK_K210
bool "Clock driver for the Canaan Kendryte K210 SoC"
- depends on OF && RISCV && SOC_CANAAN
- default SOC_CANAAN
+ depends on OF && RISCV && SOC_CANAAN_K210
+ default SOC_CANAAN_K210
help
Support for the Canaan Kendryte K210 RISC-V SoC clocks.
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* Re: [PATCH v6 07/11] clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
2024-03-23 12:12 ` Yangyu Chen
@ 2024-04-05 21:47 ` Stephen Boyd
-1 siblings, 0 replies; 54+ messages in thread
From: Stephen Boyd @ 2024-04-05 21:47 UTC (permalink / raw)
To: Yangyu Chen, linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Linus Walleij, Philipp Zabel, linux-gpio,
linux-clk, devicetree, linux-kernel, Yangyu Chen
Quoting Yangyu Chen (2024-03-23 05:12:19)
> Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> SoCs is already on the mailing list [2,3,4], we remove the use of
> SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
>
> Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
> when it has the symbol SOC_CANAAN_K210.
>
> [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 07/11] clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
@ 2024-04-05 21:47 ` Stephen Boyd
0 siblings, 0 replies; 54+ messages in thread
From: Stephen Boyd @ 2024-04-05 21:47 UTC (permalink / raw)
To: Yangyu Chen, linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Linus Walleij, Philipp Zabel, linux-gpio,
linux-clk, devicetree, linux-kernel, Yangyu Chen
Quoting Yangyu Chen (2024-03-23 05:12:19)
> Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> SoCs is already on the mailing list [2,3,4], we remove the use of
> SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
>
> Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
> when it has the symbol SOC_CANAAN_K210.
>
> [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4], we remove the use of
SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
drivers/pinctrl/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d45657aa986a..1be05efccc29 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -235,13 +235,13 @@ config PINCTRL_INGENIC
config PINCTRL_K210
bool "Pinctrl driver for the Canaan Kendryte K210 SoC"
- depends on RISCV && SOC_CANAAN && OF
+ depends on RISCV && SOC_CANAAN_K210 && OF
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select GPIOLIB
select OF_GPIO
select REGMAP_MMIO
- default SOC_CANAAN
+ default SOC_CANAAN_K210
help
Add support for the Canaan Kendryte K210 RISC-V SOC Field
Programmable IO Array (FPIOA) controller.
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4], we remove the use of
SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
drivers/pinctrl/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d45657aa986a..1be05efccc29 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -235,13 +235,13 @@ config PINCTRL_INGENIC
config PINCTRL_K210
bool "Pinctrl driver for the Canaan Kendryte K210 SoC"
- depends on RISCV && SOC_CANAAN && OF
+ depends on RISCV && SOC_CANAAN_K210 && OF
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select GPIOLIB
select OF_GPIO
select REGMAP_MMIO
- default SOC_CANAAN
+ default SOC_CANAAN_K210
help
Add support for the Canaan Kendryte K210 RISC-V SOC Field
Programmable IO Array (FPIOA) controller.
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
2024-03-23 12:12 ` Yangyu Chen
@ 2024-04-02 12:31 ` Linus Walleij
-1 siblings, 0 replies; 54+ messages in thread
From: Linus Walleij @ 2024-04-02 12:31 UTC (permalink / raw)
To: Yangyu Chen
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel
On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
> Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> SoCs is already on the mailing list [2,3,4], we remove the use of
> SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
>
> Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
> when it has the symbol SOC_CANAAN_K210.
>
> [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Is this patch something I can just apply to the pinctrl tree?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
@ 2024-04-02 12:31 ` Linus Walleij
0 siblings, 0 replies; 54+ messages in thread
From: Linus Walleij @ 2024-04-02 12:31 UTC (permalink / raw)
To: Yangyu Chen
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel
On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
> Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> SoCs is already on the mailing list [2,3,4], we remove the use of
> SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
>
> Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
> when it has the symbol SOC_CANAAN_K210.
>
> [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Is this patch something I can just apply to the pinctrl tree?
Yours,
Linus Walleij
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
2024-04-02 12:31 ` Linus Walleij
@ 2024-04-02 12:56 ` Conor Dooley
-1 siblings, 0 replies; 54+ messages in thread
From: Conor Dooley @ 2024-04-02 12:56 UTC (permalink / raw)
To: Linus Walleij
Cc: Yangyu Chen, linux-riscv, Conor Dooley, Damien Le Moal,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Michael Turquette, Stephen Boyd,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1453 bytes --]
On Tue, Apr 02, 2024 at 02:31:36PM +0200, Linus Walleij wrote:
> On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
>
> > Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> > SoCs is already on the mailing list [2,3,4], we remove the use of
> > SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
> >
> > Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
> > when it has the symbol SOC_CANAAN_K210.
> >
> > [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> > [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> > [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> > [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
> >
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Is this patch something I can just apply to the pinctrl tree?
The new symbol doesn't exist in the pinctrl tree, so the driver will
cease to be compilable. Yangyu sent a standalone version of these symbol
changes:
https://lore.kernel.org/all/tencent_DB11214C8D0D7C48829ADA128E7BB8F13108@qq.com/
That whole series needs to go through one tree though, for the same reason.
If your ack transfers to that (identical patch) I can take the whole lot
via the soc tree for v6.10.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
@ 2024-04-02 12:56 ` Conor Dooley
0 siblings, 0 replies; 54+ messages in thread
From: Conor Dooley @ 2024-04-02 12:56 UTC (permalink / raw)
To: Linus Walleij
Cc: Yangyu Chen, linux-riscv, Conor Dooley, Damien Le Moal,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Michael Turquette, Stephen Boyd,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1453 bytes --]
On Tue, Apr 02, 2024 at 02:31:36PM +0200, Linus Walleij wrote:
> On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
>
> > Since SOC_FOO should be deprecated from patch [1], and cleanup for other
> > SoCs is already on the mailing list [2,3,4], we remove the use of
> > SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
> >
> > Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
> > when it has the symbol SOC_CANAAN_K210.
> >
> > [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
> > [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
> > [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
> > [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
> >
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Is this patch something I can just apply to the pinctrl tree?
The new symbol doesn't exist in the pinctrl tree, so the driver will
cease to be compilable. Yangyu sent a standalone version of these symbol
changes:
https://lore.kernel.org/all/tencent_DB11214C8D0D7C48829ADA128E7BB8F13108@qq.com/
That whole series needs to go through one tree though, for the same reason.
If your ack transfers to that (identical patch) I can take the whole lot
via the soc tree for v6.10.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
2024-04-02 12:56 ` Conor Dooley
@ 2024-04-04 11:58 ` Linus Walleij
-1 siblings, 0 replies; 54+ messages in thread
From: Linus Walleij @ 2024-04-04 11:58 UTC (permalink / raw)
To: Conor Dooley
Cc: Yangyu Chen, linux-riscv, Conor Dooley, Damien Le Moal,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Michael Turquette, Stephen Boyd,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
On Tue, Apr 2, 2024 at 2:58 PM Conor Dooley <conor.dooley@microchip.com> wrote:
> On Tue, Apr 02, 2024 at 02:31:36PM +0200, Linus Walleij wrote:
> > On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
> > Is this patch something I can just apply to the pinctrl tree?
>
> The new symbol doesn't exist in the pinctrl tree, so the driver will
> cease to be compilable. Yangyu sent a standalone version of these symbol
> changes:
> https://lore.kernel.org/all/tencent_DB11214C8D0D7C48829ADA128E7BB8F13108@qq.com/
> That whole series needs to go through one tree though, for the same reason.
OK
> If your ack transfers to that (identical patch) I can take the whole lot
> via the soc tree for v6.10.
Yeah that's fine, go ahead.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
@ 2024-04-04 11:58 ` Linus Walleij
0 siblings, 0 replies; 54+ messages in thread
From: Linus Walleij @ 2024-04-04 11:58 UTC (permalink / raw)
To: Conor Dooley
Cc: Yangyu Chen, linux-riscv, Conor Dooley, Damien Le Moal,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Michael Turquette, Stephen Boyd,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
On Tue, Apr 2, 2024 at 2:58 PM Conor Dooley <conor.dooley@microchip.com> wrote:
> On Tue, Apr 02, 2024 at 02:31:36PM +0200, Linus Walleij wrote:
> > On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
> > Is this patch something I can just apply to the pinctrl tree?
>
> The new symbol doesn't exist in the pinctrl tree, so the driver will
> cease to be compilable. Yangyu sent a standalone version of these symbol
> changes:
> https://lore.kernel.org/all/tencent_DB11214C8D0D7C48829ADA128E7BB8F13108@qq.com/
> That whole series needs to go through one tree though, for the same reason.
OK
> If your ack transfers to that (identical patch) I can take the whole lot
> via the soc tree for v6.10.
Yeah that's fine, go ahead.
Yours,
Linus Walleij
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
2024-04-02 12:31 ` Linus Walleij
@ 2024-04-03 8:38 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-04-03 8:38 UTC (permalink / raw)
To: Linus Walleij
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel
> On Apr 2, 2024, at 20:31, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
>
>> Since SOC_FOO should be deprecated from patch [1], and cleanup for other
>> SoCs is already on the mailing list [2,3,4], we remove the use of
>> SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
>>
>> Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
>> when it has the symbol SOC_CANAAN_K210.
>>
>> [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
>> [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
>> [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
>> [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
>>
>> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
Please add Acked-by to this email [1]. I will separate them in the next
revision.
[1]
https://lore.kernel.org/linux-riscv/tencent_DB11214C8D0D7C48829ADA128E7BB8F13108@qq.com/
Thanks.
> Is this patch something I can just apply to the pinctrl tree?
>
I think not. As Conor said.
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 08/11] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
@ 2024-04-03 8:38 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-04-03 8:38 UTC (permalink / raw)
To: Linus Walleij
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel
> On Apr 2, 2024, at 20:31, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Sat, Mar 23, 2024 at 1:13 PM Yangyu Chen <cyy@cyyself.name> wrote:
>
>> Since SOC_FOO should be deprecated from patch [1], and cleanup for other
>> SoCs is already on the mailing list [2,3,4], we remove the use of
>> SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
>>
>> Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
>> when it has the symbol SOC_CANAAN_K210.
>>
>> [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
>> [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
>> [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
>> [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
>>
>> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
Please add Acked-by to this email [1]. I will separate them in the next
revision.
[1]
https://lore.kernel.org/linux-riscv/tencent_DB11214C8D0D7C48829ADA128E7BB8F13108@qq.com/
Thanks.
> Is this patch something I can just apply to the pinctrl tree?
>
I think not. As Conor said.
> Yours,
> Linus Walleij
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v6 09/11] reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4,5], we remove the use of
SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
[5] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
drivers/reset/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 85b27c42cf65..7112f5932609 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -103,9 +103,9 @@ config RESET_INTEL_GW
config RESET_K210
bool "Reset controller driver for Canaan Kendryte K210 SoC"
- depends on (SOC_CANAAN || COMPILE_TEST) && OF
+ depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
select MFD_SYSCON
- default SOC_CANAAN
+ default SOC_CANAAN_K210
help
Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
Say Y if you want to control reset signals provided by this
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 09/11] reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already on the mailing list [2,3,4,5], we remove the use of
SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,
Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.
[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/
[5] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
drivers/reset/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 85b27c42cf65..7112f5932609 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -103,9 +103,9 @@ config RESET_INTEL_GW
config RESET_K210
bool "Reset controller driver for Canaan Kendryte K210 SoC"
- depends on (SOC_CANAAN || COMPILE_TEST) && OF
+ depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
select MFD_SYSCON
- default SOC_CANAAN
+ default SOC_CANAAN_K210
help
Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
Say Y if you want to control reset signals provided by this
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Add initial dts for CanMV-K230 and K230-EVB powered by Canaan Kendryte
K230 SoC [1].
Some key consideration:
- Only place BigCore which is 1.6GHz RV64GCBV
The existence of cache coherence between the two cores remains unknown
since they have dedicated L2 caches. And the factory SDK uses it for
other OS by default. I don't know whether the two CPUs on K230 SoC
can be used in one system. So only place BigCore here.
Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
CPU1, the CSR.MHARTID of this core is 0.
- Support for "zba" "zbb" "zbc" "zbs" are tested by hand
The user manual of C908 from T-Head does not document it specifically.
It just said it supports B extension V1.0. [2]
I have tested it by using this [3] which attempts to execute "add.uw",
"andn", "clmulr", "bclr" and they doesn't traps on K230. But on JH7110,
"clmulr" and "bclr" will trap.
- Support for "zicbom" is tested by hand
Have tested with some out-of-tree drivers from [4] that need DMA and they
do not come to the dts currently.
- Cache parameters are inferred from T-Head docs [2] and Canaan docs [1]
L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
The numbers of cache sets are calculated from these parameters.
- MMU only supports Sv39
The T-Head docs [2] say the C908 core can be configured to support Sv48 and
Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type in
dts and boot the mainline kernel. However, it failed during the kernel
probe and fell back to Sv39. I also tested it on M-Mode software, writing
Sv48 to satp.mode will not trap but will leave the CSR unchanged. While
writing Sv39, it will take effect. It shows that this CPU does not support
Sv48.
- Svpbmt and T-Head MAEE both supported
T-Head C908 does support both Svpbmt and T-Head MAEE for page-based memory
attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt is used
here for mainline kernel support for K230. If the kernel wants to use
Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS before
entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0 on
T-Head MAEE is NonCachable Memory. Once the kernel switches from bare metal
to Sv39, It will lose dirty cache line modifications that haven't been
written back to the memory.
[1] https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
[2] https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
[3] https://github.com/cyyself/rvb_test
[4] https://github.com/cyyself/linux/tree/k230-mainline
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
arch/riscv/boot/dts/canaan/Makefile | 2 +
arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
arch/riscv/boot/dts/canaan/k230.dtsi | 140 ++++++++++++++++++++++
4 files changed, 190 insertions(+)
create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile
index 987d1f0c41f0..7d54ea5c6f3d 100644
--- a/arch/riscv/boot/dts/canaan/Makefile
+++ b/arch/riscv/boot/dts/canaan/Makefile
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts
new file mode 100644
index 000000000000..9565915cead6
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k230.dtsi"
+
+/ {
+ model = "Canaan CanMV-K230";
+ compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ddr: memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts
new file mode 100644
index 000000000000..f898b8e62368
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k230.dtsi"
+
+/ {
+ model = "Kendryte K230 EVB";
+ compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-k230";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ddr: memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi
new file mode 100644
index 000000000000..7da49498945e
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230.dtsi
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "canaan,kendryte-k230";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <27000000>;
+
+ cpu@0 {
+ compatible = "thead,c908", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa = "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicntr", "zicsr",
+ "zifencei", "zihpm", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <262144>;
+ cache-sets = <256>;
+ cache-unified;
+ };
+ };
+
+ apb_clk: apb-clk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "apb_clk";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-noncoherent;
+ ranges;
+
+ plic: interrupt-controller@f00000000 {
+ compatible = "canaan,k230-plic" ,"thead,c900-plic";
+ reg = <0xf 0x00000000 0x0 0x04000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <208>;
+ };
+
+ clint: timer@f04000000 {
+ compatible = "canaan,k230-clint", "thead,c900-clint";
+ reg = <0xf 0x04000000 0x0 0x00010000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
+
+ uart0: serial@91400000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91400000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@91401000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91401000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@91402000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91402000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@91403000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91403000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@91404000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91404000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen
Add initial dts for CanMV-K230 and K230-EVB powered by Canaan Kendryte
K230 SoC [1].
Some key consideration:
- Only place BigCore which is 1.6GHz RV64GCBV
The existence of cache coherence between the two cores remains unknown
since they have dedicated L2 caches. And the factory SDK uses it for
other OS by default. I don't know whether the two CPUs on K230 SoC
can be used in one system. So only place BigCore here.
Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
CPU1, the CSR.MHARTID of this core is 0.
- Support for "zba" "zbb" "zbc" "zbs" are tested by hand
The user manual of C908 from T-Head does not document it specifically.
It just said it supports B extension V1.0. [2]
I have tested it by using this [3] which attempts to execute "add.uw",
"andn", "clmulr", "bclr" and they doesn't traps on K230. But on JH7110,
"clmulr" and "bclr" will trap.
- Support for "zicbom" is tested by hand
Have tested with some out-of-tree drivers from [4] that need DMA and they
do not come to the dts currently.
- Cache parameters are inferred from T-Head docs [2] and Canaan docs [1]
L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
The numbers of cache sets are calculated from these parameters.
- MMU only supports Sv39
The T-Head docs [2] say the C908 core can be configured to support Sv48 and
Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type in
dts and boot the mainline kernel. However, it failed during the kernel
probe and fell back to Sv39. I also tested it on M-Mode software, writing
Sv48 to satp.mode will not trap but will leave the CSR unchanged. While
writing Sv39, it will take effect. It shows that this CPU does not support
Sv48.
- Svpbmt and T-Head MAEE both supported
T-Head C908 does support both Svpbmt and T-Head MAEE for page-based memory
attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt is used
here for mainline kernel support for K230. If the kernel wants to use
Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS before
entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0 on
T-Head MAEE is NonCachable Memory. Once the kernel switches from bare metal
to Sv39, It will lose dirty cache line modifications that haven't been
written back to the memory.
[1] https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
[2] https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
[3] https://github.com/cyyself/rvb_test
[4] https://github.com/cyyself/linux/tree/k230-mainline
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
---
arch/riscv/boot/dts/canaan/Makefile | 2 +
arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
arch/riscv/boot/dts/canaan/k230.dtsi | 140 ++++++++++++++++++++++
4 files changed, 190 insertions(+)
create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile
index 987d1f0c41f0..7d54ea5c6f3d 100644
--- a/arch/riscv/boot/dts/canaan/Makefile
+++ b/arch/riscv/boot/dts/canaan/Makefile
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts
new file mode 100644
index 000000000000..9565915cead6
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k230.dtsi"
+
+/ {
+ model = "Canaan CanMV-K230";
+ compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ddr: memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts
new file mode 100644
index 000000000000..f898b8e62368
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k230.dtsi"
+
+/ {
+ model = "Kendryte K230 EVB";
+ compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-k230";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ddr: memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi
new file mode 100644
index 000000000000..7da49498945e
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230.dtsi
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "canaan,kendryte-k230";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <27000000>;
+
+ cpu@0 {
+ compatible = "thead,c908", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa = "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zba", "zbb",
+ "zbc", "zbs", "zicbom", "zicntr", "zicsr",
+ "zifencei", "zihpm", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <262144>;
+ cache-sets = <256>;
+ cache-unified;
+ };
+ };
+
+ apb_clk: apb-clk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "apb_clk";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-noncoherent;
+ ranges;
+
+ plic: interrupt-controller@f00000000 {
+ compatible = "canaan,k230-plic" ,"thead,c900-plic";
+ reg = <0xf 0x00000000 0x0 0x04000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <208>;
+ };
+
+ clint: timer@f04000000 {
+ compatible = "canaan,k230-clint", "thead,c900-clint";
+ reg = <0xf 0x04000000 0x0 0x00010000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
+
+ uart0: serial@91400000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91400000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@91401000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91401000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@91402000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91402000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@91403000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91403000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@91404000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x91404000 0x0 0x1000>;
+ clocks = <&apb_clk>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+};
--
2.43.0
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^ permalink raw reply related [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
2024-03-23 12:12 ` Yangyu Chen
@ 2024-03-24 16:23 ` Icenowy Zheng
-1 siblings, 0 replies; 54+ messages in thread
From: Icenowy Zheng @ 2024-03-24 16:23 UTC (permalink / raw)
To: Yangyu Chen, linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel
在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan
> Kendryte
> K230 SoC [1].
>
> Some key consideration:
>
> - Only place BigCore which is 1.6GHz RV64GCBV
>
> The existence of cache coherence between the two cores remains
> unknown
> since they have dedicated L2 caches. And the factory SDK uses it for
> other OS by default. I don't know whether the two CPUs on K230 SoC
> can be used in one system. So only place BigCore here.
>
> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
> CPU1, the CSR.MHARTID of this core is 0.
I assume as these two cores do not have any coherency, they are just in
different hartid namespace.
>
> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>
> The user manual of C908 from T-Head does not document it
> specifically.
> It just said it supports B extension V1.0. [2]
>
> I have tested it by using this [3] which attempts to execute
> "add.uw",
> "andn", "clmulr", "bclr" and they doesn't traps on K230. But on
> JH7110,
> "clmulr" and "bclr" will trap.
>
> - Support for "zicbom" is tested by hand
>
> Have tested with some out-of-tree drivers from [4] that need DMA and
> they
> do not come to the dts currently.
>
> - Cache parameters are inferred from T-Head docs [2] and Canaan docs
> [1]
>
> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
> L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
>
> The numbers of cache sets are calculated from these parameters.
>
> - MMU only supports Sv39
>
> The T-Head docs [2] say the C908 core can be configured to support
> Sv48 and
> Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type
> in
> dts and boot the mainline kernel. However, it failed during the
> kernel
> probe and fell back to Sv39. I also tested it on M-Mode software,
> writing
> Sv48 to satp.mode will not trap but will leave the CSR unchanged.
It's specified by the spec that writing a unsupported mode to SATP will
leave SATP unchanged, and it's also how the kernel detects for Sv48/57.
If a hardware fail to implement this behavior (make SATP changes when
writing an unsupported mode), the kernel will fail to boot and manually
specify MMU mode by putting noXlvl to command line is required. This
behavior may be observed on FSL1030M SoC of Milk-V Vega (if it ever
runs mainline kernel).
> While
> writing Sv39, it will take effect. It shows that this CPU does not
> support
> Sv48.
>
> - Svpbmt and T-Head MAEE both supported
>
> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
> memory
> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
> is used
> here for mainline kernel support for K230. If the kernel wants to use
> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
> before
> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
> on
> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
> metal
> to Sv39, It will lose dirty cache line modifications that haven't
> been
> written back to the memory.
As MXSTATUS has a S-mode read-only mirror known as SXSTATUS, maybe the
kernel should detect SXSTATUS to decide whether to use Svpbmt or
Xtheadpbmt (BTW Svnapot conflicts with Xtheadpbmt too).
>
> [1]
> https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
> [2]
> https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
> [3] https://github.com/cyyself/rvb_test
> [4] https://github.com/cyyself/linux/tree/k230-mainline
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
> arch/riscv/boot/dts/canaan/Makefile | 2 +
> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
> arch/riscv/boot/dts/canaan/k230.dtsi | 140
> ++++++++++++++++++++++
> 4 files changed, 190 insertions(+)
> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>
> diff --git a/arch/riscv/boot/dts/canaan/Makefile
> b/arch/riscv/boot/dts/canaan/Makefile
> index 987d1f0c41f0..7d54ea5c6f3d 100644
> --- a/arch/riscv/boot/dts/canaan/Makefile
> +++ b/arch/riscv/boot/dts/canaan/Makefile
> @@ -1,6 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
> +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
> diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts
> b/arch/riscv/boot/dts/canaan/k230-canmv.dts
> new file mode 100644
> index 000000000000..9565915cead6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k230.dtsi"
> +
> +/ {
> + model = "Canaan CanMV-K230";
> + compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ddr: memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x20000000>;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts
> b/arch/riscv/boot/dts/canaan/k230-evb.dts
> new file mode 100644
> index 000000000000..f898b8e62368
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k230.dtsi"
> +
> +/ {
> + model = "Kendryte K230 EVB";
> + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-
> k230";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ddr: memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x20000000>;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi
> b/arch/riscv/boot/dts/canaan/k230.dtsi
> new file mode 100644
> index 000000000000..7da49498945e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230.dtsi
> @@ -0,0 +1,140 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "canaan,kendryte-k230";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <27000000>;
> +
> + cpu@0 {
> + compatible = "thead,c908", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa =
> "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f",
> "d", "c", "v", "zba", "zbb",
> + "zbc", "zbs",
> "zicbom", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> "svpbmt";
> + riscv,cbom-block-size = <64>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <128>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + l2_cache: l2-cache {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <262144>;
> + cache-sets = <256>;
> + cache-unified;
> + };
> + };
> +
> + apb_clk: apb-clk-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <50000000>;
> + clock-output-names = "apb_clk";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + plic: interrupt-controller@f00000000 {
> + compatible = "canaan,k230-plic" ,"thead,c900-
> plic";
> + reg = <0xf 0x00000000 0x0 0x04000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <208>;
> + };
> +
> + clint: timer@f04000000 {
> + compatible = "canaan,k230-clint",
> "thead,c900-clint";
> + reg = <0xf 0x04000000 0x0 0x00010000>;
> + interrupts-extended = <&cpu0_intc 3>,
> <&cpu0_intc 7>;
> + };
> +
> + uart0: serial@91400000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91400000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@91401000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91401000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@91402000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91402000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@91403000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91403000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@91404000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91404000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> +};
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
@ 2024-03-24 16:23 ` Icenowy Zheng
0 siblings, 0 replies; 54+ messages in thread
From: Icenowy Zheng @ 2024-03-24 16:23 UTC (permalink / raw)
To: Yangyu Chen, linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel
在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan
> Kendryte
> K230 SoC [1].
>
> Some key consideration:
>
> - Only place BigCore which is 1.6GHz RV64GCBV
>
> The existence of cache coherence between the two cores remains
> unknown
> since they have dedicated L2 caches. And the factory SDK uses it for
> other OS by default. I don't know whether the two CPUs on K230 SoC
> can be used in one system. So only place BigCore here.
>
> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
> CPU1, the CSR.MHARTID of this core is 0.
I assume as these two cores do not have any coherency, they are just in
different hartid namespace.
>
> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>
> The user manual of C908 from T-Head does not document it
> specifically.
> It just said it supports B extension V1.0. [2]
>
> I have tested it by using this [3] which attempts to execute
> "add.uw",
> "andn", "clmulr", "bclr" and they doesn't traps on K230. But on
> JH7110,
> "clmulr" and "bclr" will trap.
>
> - Support for "zicbom" is tested by hand
>
> Have tested with some out-of-tree drivers from [4] that need DMA and
> they
> do not come to the dts currently.
>
> - Cache parameters are inferred from T-Head docs [2] and Canaan docs
> [1]
>
> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
> L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
>
> The numbers of cache sets are calculated from these parameters.
>
> - MMU only supports Sv39
>
> The T-Head docs [2] say the C908 core can be configured to support
> Sv48 and
> Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type
> in
> dts and boot the mainline kernel. However, it failed during the
> kernel
> probe and fell back to Sv39. I also tested it on M-Mode software,
> writing
> Sv48 to satp.mode will not trap but will leave the CSR unchanged.
It's specified by the spec that writing a unsupported mode to SATP will
leave SATP unchanged, and it's also how the kernel detects for Sv48/57.
If a hardware fail to implement this behavior (make SATP changes when
writing an unsupported mode), the kernel will fail to boot and manually
specify MMU mode by putting noXlvl to command line is required. This
behavior may be observed on FSL1030M SoC of Milk-V Vega (if it ever
runs mainline kernel).
> While
> writing Sv39, it will take effect. It shows that this CPU does not
> support
> Sv48.
>
> - Svpbmt and T-Head MAEE both supported
>
> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
> memory
> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
> is used
> here for mainline kernel support for K230. If the kernel wants to use
> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
> before
> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
> on
> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
> metal
> to Sv39, It will lose dirty cache line modifications that haven't
> been
> written back to the memory.
As MXSTATUS has a S-mode read-only mirror known as SXSTATUS, maybe the
kernel should detect SXSTATUS to decide whether to use Svpbmt or
Xtheadpbmt (BTW Svnapot conflicts with Xtheadpbmt too).
>
> [1]
> https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
> [2]
> https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
> [3] https://github.com/cyyself/rvb_test
> [4] https://github.com/cyyself/linux/tree/k230-mainline
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
> arch/riscv/boot/dts/canaan/Makefile | 2 +
> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
> arch/riscv/boot/dts/canaan/k230.dtsi | 140
> ++++++++++++++++++++++
> 4 files changed, 190 insertions(+)
> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>
> diff --git a/arch/riscv/boot/dts/canaan/Makefile
> b/arch/riscv/boot/dts/canaan/Makefile
> index 987d1f0c41f0..7d54ea5c6f3d 100644
> --- a/arch/riscv/boot/dts/canaan/Makefile
> +++ b/arch/riscv/boot/dts/canaan/Makefile
> @@ -1,6 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
> +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
> diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts
> b/arch/riscv/boot/dts/canaan/k230-canmv.dts
> new file mode 100644
> index 000000000000..9565915cead6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k230.dtsi"
> +
> +/ {
> + model = "Canaan CanMV-K230";
> + compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ddr: memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x20000000>;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts
> b/arch/riscv/boot/dts/canaan/k230-evb.dts
> new file mode 100644
> index 000000000000..f898b8e62368
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k230.dtsi"
> +
> +/ {
> + model = "Kendryte K230 EVB";
> + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-
> k230";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ddr: memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x20000000>;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi
> b/arch/riscv/boot/dts/canaan/k230.dtsi
> new file mode 100644
> index 000000000000..7da49498945e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230.dtsi
> @@ -0,0 +1,140 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "canaan,kendryte-k230";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <27000000>;
> +
> + cpu@0 {
> + compatible = "thead,c908", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa =
> "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f",
> "d", "c", "v", "zba", "zbb",
> + "zbc", "zbs",
> "zicbom", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> "svpbmt";
> + riscv,cbom-block-size = <64>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <128>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + l2_cache: l2-cache {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <262144>;
> + cache-sets = <256>;
> + cache-unified;
> + };
> + };
> +
> + apb_clk: apb-clk-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <50000000>;
> + clock-output-names = "apb_clk";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + plic: interrupt-controller@f00000000 {
> + compatible = "canaan,k230-plic" ,"thead,c900-
> plic";
> + reg = <0xf 0x00000000 0x0 0x04000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <208>;
> + };
> +
> + clint: timer@f04000000 {
> + compatible = "canaan,k230-clint",
> "thead,c900-clint";
> + reg = <0xf 0x04000000 0x0 0x00010000>;
> + interrupts-extended = <&cpu0_intc 3>,
> <&cpu0_intc 7>;
> + };
> +
> + uart0: serial@91400000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91400000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@91401000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91401000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@91402000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91402000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@91403000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91403000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@91404000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91404000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
2024-03-24 16:23 ` Icenowy Zheng
@ 2024-03-25 3:10 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-25 3:10 UTC (permalink / raw)
To: Icenowy Zheng
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
> On Mar 25, 2024, at 00:23, Icenowy Zheng <uwu@icenowy.me> wrote:
>
> 在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
>> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan
>> Kendryte
>> K230 SoC [1].
>>
>> Some key consideration:
>>
>> - Only place BigCore which is 1.6GHz RV64GCBV
>>
>> The existence of cache coherence between the two cores remains
>> unknown
>> since they have dedicated L2 caches. And the factory SDK uses it for
>> other OS by default. I don't know whether the two CPUs on K230 SoC
>> can be used in one system. So only place BigCore here.
>>
>> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
>> CPU1, the CSR.MHARTID of this core is 0.
>
> I assume as these two cores do not have any coherency, they are just in
> different hartid namespace.
>
Thanks for this hint.
>>
>> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>>
>> The user manual of C908 from T-Head does not document it
>> specifically.
>> It just said it supports B extension V1.0. [2]
>>
>> I have tested it by using this [3] which attempts to execute
>> "add.uw",
>> "andn", "clmulr", "bclr" and they doesn't traps on K230. But on
>> JH7110,
>> "clmulr" and "bclr" will trap.
>>
>> - Support for "zicbom" is tested by hand
>>
>> Have tested with some out-of-tree drivers from [4] that need DMA and
>> they
>> do not come to the dts currently.
>>
>> - Cache parameters are inferred from T-Head docs [2] and Canaan docs
>> [1]
>>
>> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
>>
>> The numbers of cache sets are calculated from these parameters.
>>
>> - MMU only supports Sv39
>>
>> The T-Head docs [2] say the C908 core can be configured to support
>> Sv48 and
>> Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type
>> in
>> dts and boot the mainline kernel. However, it failed during the
>> kernel
>> probe and fell back to Sv39. I also tested it on M-Mode software,
>> writing
>> Sv48 to satp.mode will not trap but will leave the CSR unchanged.
>
> It's specified by the spec that writing a unsupported mode to SATP will
> leave SATP unchanged, and it's also how the kernel detects for Sv48/57.
>
> If a hardware fail to implement this behavior (make SATP changes when
> writing an unsupported mode), the kernel will fail to boot and manually
> specify MMU mode by putting noXlvl to command line is required. This
> behavior may be observed on FSL1030M SoC of Milk-V Vega (if it ever
> runs mainline kernel).
>
OK.
>> While
>> writing Sv39, it will take effect. It shows that this CPU does not
>> support
>> Sv48.
>>
>> - Svpbmt and T-Head MAEE both supported
>>
>> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
>> memory
>> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
>> is used
>> here for mainline kernel support for K230. If the kernel wants to use
>> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
>> before
>> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
>> on
>> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
>> metal
>> to Sv39, It will lose dirty cache line modifications that haven't
>> been
>> written back to the memory.
>
> As MXSTATUS has a S-mode read-only mirror known as SXSTATUS, maybe the
> kernel should detect SXSTATUS to decide whether to use Svpbmt or
> Xtheadpbmt (BTW Svnapot conflicts with Xtheadpbmt too).
>
Thanks for this hint. I may need to change some code in the T-Head PBMT probe.
>>
>> [1]
>> https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
>> [2]
>> https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
>> [3] https://github.com/cyyself/rvb_test
>> [4] https://github.com/cyyself/linux/tree/k230-mainline
>>
>> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>> ---
>> arch/riscv/boot/dts/canaan/Makefile | 2 +
>> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
>> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
>> arch/riscv/boot/dts/canaan/k230.dtsi | 140
>> ++++++++++++++++++++++
>> 4 files changed, 190 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
>> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
>> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/canaan/Makefile
>> b/arch/riscv/boot/dts/canaan/Makefile
>> index 987d1f0c41f0..7d54ea5c6f3d 100644
>> --- a/arch/riscv/boot/dts/canaan/Makefile
>> +++ b/arch/riscv/boot/dts/canaan/Makefile
>> @@ -1,6 +1,8 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
>> diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> b/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> new file mode 100644
>> index 000000000000..9565915cead6
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include "k230.dtsi"
>> +
>> +/ {
>> + model = "Canaan CanMV-K230";
>> + compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + ddr: memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x20000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts
>> b/arch/riscv/boot/dts/canaan/k230-evb.dts
>> new file mode 100644
>> index 000000000000..f898b8e62368
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include "k230.dtsi"
>> +
>> +/ {
>> + model = "Kendryte K230 EVB";
>> + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-
>> k230";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + ddr: memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x20000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi
>> b/arch/riscv/boot/dts/canaan/k230.dtsi
>> new file mode 100644
>> index 000000000000..7da49498945e
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230.dtsi
>> @@ -0,0 +1,140 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +/dts-v1/;
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + compatible = "canaan,kendryte-k230";
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + timebase-frequency = <27000000>;
>> +
>> + cpu@0 {
>> + compatible = "thead,c908", "riscv";
>> + device_type = "cpu";
>> + reg = <0>;
>> + riscv,isa =
>> "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
>> + riscv,isa-base = "rv64i";
>> + riscv,isa-extensions = "i", "m", "a", "f",
>> "d", "c", "v", "zba", "zbb",
>> + "zbc", "zbs",
>> "zicbom", "zicntr", "zicsr",
>> + "zifencei", "zihpm",
>> "svpbmt";
>> + riscv,cbom-block-size = <64>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <128>;
>> + d-cache-size = <32768>;
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <128>;
>> + i-cache-size = <32768>;
>> + next-level-cache = <&l2_cache>;
>> + mmu-type = "riscv,sv39";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + l2_cache: l2-cache {
>> + compatible = "cache";
>> + cache-block-size = <64>;
>> + cache-level = <2>;
>> + cache-size = <262144>;
>> + cache-sets = <256>;
>> + cache-unified;
>> + };
>> + };
>> +
>> + apb_clk: apb-clk-clock {
>> + compatible = "fixed-clock";
>> + clock-frequency = <50000000>;
>> + clock-output-names = "apb_clk";
>> + #clock-cells = <0>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + interrupt-parent = <&plic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + dma-noncoherent;
>> + ranges;
>> +
>> + plic: interrupt-controller@f00000000 {
>> + compatible = "canaan,k230-plic" ,"thead,c900-
>> plic";
>> + reg = <0xf 0x00000000 0x0 0x04000000>;
>> + interrupts-extended = <&cpu0_intc 11>,
>> <&cpu0_intc 9>;
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <2>;
>> + riscv,ndev = <208>;
>> + };
>> +
>> + clint: timer@f04000000 {
>> + compatible = "canaan,k230-clint",
>> "thead,c900-clint";
>> + reg = <0xf 0x04000000 0x0 0x00010000>;
>> + interrupts-extended = <&cpu0_intc 3>,
>> <&cpu0_intc 7>;
>> + };
>> +
>> + uart0: serial@91400000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91400000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@91401000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91401000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@91402000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91402000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@91403000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91403000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@91404000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91404000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
@ 2024-03-25 3:10 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-25 3:10 UTC (permalink / raw)
To: Icenowy Zheng
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
> On Mar 25, 2024, at 00:23, Icenowy Zheng <uwu@icenowy.me> wrote:
>
> 在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
>> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan
>> Kendryte
>> K230 SoC [1].
>>
>> Some key consideration:
>>
>> - Only place BigCore which is 1.6GHz RV64GCBV
>>
>> The existence of cache coherence between the two cores remains
>> unknown
>> since they have dedicated L2 caches. And the factory SDK uses it for
>> other OS by default. I don't know whether the two CPUs on K230 SoC
>> can be used in one system. So only place BigCore here.
>>
>> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
>> CPU1, the CSR.MHARTID of this core is 0.
>
> I assume as these two cores do not have any coherency, they are just in
> different hartid namespace.
>
Thanks for this hint.
>>
>> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>>
>> The user manual of C908 from T-Head does not document it
>> specifically.
>> It just said it supports B extension V1.0. [2]
>>
>> I have tested it by using this [3] which attempts to execute
>> "add.uw",
>> "andn", "clmulr", "bclr" and they doesn't traps on K230. But on
>> JH7110,
>> "clmulr" and "bclr" will trap.
>>
>> - Support for "zicbom" is tested by hand
>>
>> Have tested with some out-of-tree drivers from [4] that need DMA and
>> they
>> do not come to the dts currently.
>>
>> - Cache parameters are inferred from T-Head docs [2] and Canaan docs
>> [1]
>>
>> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
>>
>> The numbers of cache sets are calculated from these parameters.
>>
>> - MMU only supports Sv39
>>
>> The T-Head docs [2] say the C908 core can be configured to support
>> Sv48 and
>> Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type
>> in
>> dts and boot the mainline kernel. However, it failed during the
>> kernel
>> probe and fell back to Sv39. I also tested it on M-Mode software,
>> writing
>> Sv48 to satp.mode will not trap but will leave the CSR unchanged.
>
> It's specified by the spec that writing a unsupported mode to SATP will
> leave SATP unchanged, and it's also how the kernel detects for Sv48/57.
>
> If a hardware fail to implement this behavior (make SATP changes when
> writing an unsupported mode), the kernel will fail to boot and manually
> specify MMU mode by putting noXlvl to command line is required. This
> behavior may be observed on FSL1030M SoC of Milk-V Vega (if it ever
> runs mainline kernel).
>
OK.
>> While
>> writing Sv39, it will take effect. It shows that this CPU does not
>> support
>> Sv48.
>>
>> - Svpbmt and T-Head MAEE both supported
>>
>> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
>> memory
>> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
>> is used
>> here for mainline kernel support for K230. If the kernel wants to use
>> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
>> before
>> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
>> on
>> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
>> metal
>> to Sv39, It will lose dirty cache line modifications that haven't
>> been
>> written back to the memory.
>
> As MXSTATUS has a S-mode read-only mirror known as SXSTATUS, maybe the
> kernel should detect SXSTATUS to decide whether to use Svpbmt or
> Xtheadpbmt (BTW Svnapot conflicts with Xtheadpbmt too).
>
Thanks for this hint. I may need to change some code in the T-Head PBMT probe.
>>
>> [1]
>> https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
>> [2]
>> https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
>> [3] https://github.com/cyyself/rvb_test
>> [4] https://github.com/cyyself/linux/tree/k230-mainline
>>
>> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>> ---
>> arch/riscv/boot/dts/canaan/Makefile | 2 +
>> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
>> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
>> arch/riscv/boot/dts/canaan/k230.dtsi | 140
>> ++++++++++++++++++++++
>> 4 files changed, 190 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
>> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
>> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/canaan/Makefile
>> b/arch/riscv/boot/dts/canaan/Makefile
>> index 987d1f0c41f0..7d54ea5c6f3d 100644
>> --- a/arch/riscv/boot/dts/canaan/Makefile
>> +++ b/arch/riscv/boot/dts/canaan/Makefile
>> @@ -1,6 +1,8 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
>> diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> b/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> new file mode 100644
>> index 000000000000..9565915cead6
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include "k230.dtsi"
>> +
>> +/ {
>> + model = "Canaan CanMV-K230";
>> + compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + ddr: memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x20000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts
>> b/arch/riscv/boot/dts/canaan/k230-evb.dts
>> new file mode 100644
>> index 000000000000..f898b8e62368
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include "k230.dtsi"
>> +
>> +/ {
>> + model = "Kendryte K230 EVB";
>> + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-
>> k230";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + ddr: memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x20000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi
>> b/arch/riscv/boot/dts/canaan/k230.dtsi
>> new file mode 100644
>> index 000000000000..7da49498945e
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230.dtsi
>> @@ -0,0 +1,140 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +/dts-v1/;
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + compatible = "canaan,kendryte-k230";
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + timebase-frequency = <27000000>;
>> +
>> + cpu@0 {
>> + compatible = "thead,c908", "riscv";
>> + device_type = "cpu";
>> + reg = <0>;
>> + riscv,isa =
>> "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
>> + riscv,isa-base = "rv64i";
>> + riscv,isa-extensions = "i", "m", "a", "f",
>> "d", "c", "v", "zba", "zbb",
>> + "zbc", "zbs",
>> "zicbom", "zicntr", "zicsr",
>> + "zifencei", "zihpm",
>> "svpbmt";
>> + riscv,cbom-block-size = <64>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <128>;
>> + d-cache-size = <32768>;
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <128>;
>> + i-cache-size = <32768>;
>> + next-level-cache = <&l2_cache>;
>> + mmu-type = "riscv,sv39";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + l2_cache: l2-cache {
>> + compatible = "cache";
>> + cache-block-size = <64>;
>> + cache-level = <2>;
>> + cache-size = <262144>;
>> + cache-sets = <256>;
>> + cache-unified;
>> + };
>> + };
>> +
>> + apb_clk: apb-clk-clock {
>> + compatible = "fixed-clock";
>> + clock-frequency = <50000000>;
>> + clock-output-names = "apb_clk";
>> + #clock-cells = <0>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + interrupt-parent = <&plic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + dma-noncoherent;
>> + ranges;
>> +
>> + plic: interrupt-controller@f00000000 {
>> + compatible = "canaan,k230-plic" ,"thead,c900-
>> plic";
>> + reg = <0xf 0x00000000 0x0 0x04000000>;
>> + interrupts-extended = <&cpu0_intc 11>,
>> <&cpu0_intc 9>;
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <2>;
>> + riscv,ndev = <208>;
>> + };
>> +
>> + clint: timer@f04000000 {
>> + compatible = "canaan,k230-clint",
>> "thead,c900-clint";
>> + reg = <0xf 0x04000000 0x0 0x00010000>;
>> + interrupts-extended = <&cpu0_intc 3>,
>> <&cpu0_intc 7>;
>> + };
>> +
>> + uart0: serial@91400000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91400000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@91401000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91401000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@91402000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91402000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@91403000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91403000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@91404000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91404000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
2024-03-25 3:10 ` Yangyu Chen
@ 2024-04-05 15:52 ` Conor Dooley
-1 siblings, 0 replies; 54+ messages in thread
From: Conor Dooley @ 2024-04-05 15:52 UTC (permalink / raw)
To: Yangyu Chen
Cc: Icenowy Zheng, linux-riscv, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1414 bytes --]
On Mon, Mar 25, 2024 at 11:10:49AM +0800, Yangyu Chen wrote:
> > On Mar 25, 2024, at 00:23, Icenowy Zheng <uwu@icenowy.me> wrote:
> > 在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
> >> - Svpbmt and T-Head MAEE both supported
> >>
> >> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
> >> memory
> >> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
> >> is used
> >> here for mainline kernel support for K230. If the kernel wants to use
> >> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
> >> before
> >> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
> >> on
> >> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
> >> metal
> >> to Sv39, It will lose dirty cache line modifications that haven't
> >> been
> >> written back to the memory.
> >
> > As MXSTATUS has a S-mode read-only mirror known as SXSTATUS, maybe the
> > kernel should detect SXSTATUS to decide whether to use Svpbmt or
> > Xtheadpbmt (BTW Svnapot conflicts with Xtheadpbmt too).
> >
>
> Thanks for this hint. I may need to change some code in the T-Head PBMT probe.
For now, I'd rather we just focused on supporting the standard
extensions on this SoC in mainline. I've applied the patches re-doing
the Kconfig options just now, feel free to resend these patches
whenever.
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
@ 2024-04-05 15:52 ` Conor Dooley
0 siblings, 0 replies; 54+ messages in thread
From: Conor Dooley @ 2024-04-05 15:52 UTC (permalink / raw)
To: Yangyu Chen
Cc: Philipp Zabel, devicetree, Albert Ou, Stephen Boyd,
Michael Turquette, linux-kernel, Rob Herring, linux-clk,
linux-gpio, Damien Le Moal, Palmer Dabbelt, Krzysztof Kozlowski,
Paul Walmsley, Guo Ren, linux-riscv, Linus Walleij
[-- Attachment #1.1: Type: text/plain, Size: 1414 bytes --]
On Mon, Mar 25, 2024 at 11:10:49AM +0800, Yangyu Chen wrote:
> > On Mar 25, 2024, at 00:23, Icenowy Zheng <uwu@icenowy.me> wrote:
> > 在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
> >> - Svpbmt and T-Head MAEE both supported
> >>
> >> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
> >> memory
> >> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
> >> is used
> >> here for mainline kernel support for K230. If the kernel wants to use
> >> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
> >> before
> >> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
> >> on
> >> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
> >> metal
> >> to Sv39, It will lose dirty cache line modifications that haven't
> >> been
> >> written back to the memory.
> >
> > As MXSTATUS has a S-mode read-only mirror known as SXSTATUS, maybe the
> > kernel should detect SXSTATUS to decide whether to use Svpbmt or
> > Xtheadpbmt (BTW Svnapot conflicts with Xtheadpbmt too).
> >
>
> Thanks for this hint. I may need to change some code in the T-Head PBMT probe.
For now, I'd rather we just focused on supporting the standard
extensions on this SoC in mainline. I've applied the patches re-doing
the Kconfig options just now, feel free to resend these patches
whenever.
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
2024-03-23 12:12 ` Yangyu Chen
@ 2024-03-24 16:24 ` Icenowy Zheng
-1 siblings, 0 replies; 54+ messages in thread
From: Icenowy Zheng @ 2024-03-24 16:24 UTC (permalink / raw)
To: Yangyu Chen, linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel
在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan
> Kendryte
> K230 SoC [1].
>
> Some key consideration:
>
> - Only place BigCore which is 1.6GHz RV64GCBV
>
> The existence of cache coherence between the two cores remains
> unknown
> since they have dedicated L2 caches. And the factory SDK uses it for
> other OS by default. I don't know whether the two CPUs on K230 SoC
> can be used in one system. So only place BigCore here.
>
> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
> CPU1, the CSR.MHARTID of this core is 0.
>
> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>
> The user manual of C908 from T-Head does not document it
> specifically.
> It just said it supports B extension V1.0. [2]
>
> I have tested it by using this [3] which attempts to execute
> "add.uw",
> "andn", "clmulr", "bclr" and they doesn't traps on K230. But on
> JH7110,
> "clmulr" and "bclr" will trap.
>
> - Support for "zicbom" is tested by hand
>
> Have tested with some out-of-tree drivers from [4] that need DMA and
> they
> do not come to the dts currently.
>
> - Cache parameters are inferred from T-Head docs [2] and Canaan docs
> [1]
>
> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
> L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
>
> The numbers of cache sets are calculated from these parameters.
>
> - MMU only supports Sv39
>
> The T-Head docs [2] say the C908 core can be configured to support
> Sv48 and
> Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type
> in
> dts and boot the mainline kernel. However, it failed during the
> kernel
> probe and fell back to Sv39. I also tested it on M-Mode software,
> writing
> Sv48 to satp.mode will not trap but will leave the CSR unchanged.
> While
> writing Sv39, it will take effect. It shows that this CPU does not
> support
> Sv48.
>
> - Svpbmt and T-Head MAEE both supported
>
> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
> memory
> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
> is used
> here for mainline kernel support for K230. If the kernel wants to use
> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
> before
> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
> on
> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
> metal
> to Sv39, It will lose dirty cache line modifications that haven't
> been
> written back to the memory.
>
> [1]
> https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
> [2]
> https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
> [3] https://github.com/cyyself/rvb_test
> [4] https://github.com/cyyself/linux/tree/k230-mainline
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
> arch/riscv/boot/dts/canaan/Makefile | 2 +
> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
> arch/riscv/boot/dts/canaan/k230.dtsi | 140
> ++++++++++++++++++++++
> 4 files changed, 190 insertions(+)
> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>
> diff --git a/arch/riscv/boot/dts/canaan/Makefile
> b/arch/riscv/boot/dts/canaan/Makefile
> index 987d1f0c41f0..7d54ea5c6f3d 100644
> --- a/arch/riscv/boot/dts/canaan/Makefile
> +++ b/arch/riscv/boot/dts/canaan/Makefile
> @@ -1,6 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
> +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
BTW did you test on K230 EVB? I think only CanMV is currently publicly
available.
If K230 EVB support is not tested, I suggest not adding it.
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
> diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts
> b/arch/riscv/boot/dts/canaan/k230-canmv.dts
> new file mode 100644
> index 000000000000..9565915cead6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k230.dtsi"
> +
> +/ {
> + model = "Canaan CanMV-K230";
> + compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ddr: memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x20000000>;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts
> b/arch/riscv/boot/dts/canaan/k230-evb.dts
> new file mode 100644
> index 000000000000..f898b8e62368
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k230.dtsi"
> +
> +/ {
> + model = "Kendryte K230 EVB";
> + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-
> k230";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ddr: memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x20000000>;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi
> b/arch/riscv/boot/dts/canaan/k230.dtsi
> new file mode 100644
> index 000000000000..7da49498945e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230.dtsi
> @@ -0,0 +1,140 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "canaan,kendryte-k230";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <27000000>;
> +
> + cpu@0 {
> + compatible = "thead,c908", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa =
> "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f",
> "d", "c", "v", "zba", "zbb",
> + "zbc", "zbs",
> "zicbom", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> "svpbmt";
> + riscv,cbom-block-size = <64>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <128>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + l2_cache: l2-cache {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <262144>;
> + cache-sets = <256>;
> + cache-unified;
> + };
> + };
> +
> + apb_clk: apb-clk-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <50000000>;
> + clock-output-names = "apb_clk";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + plic: interrupt-controller@f00000000 {
> + compatible = "canaan,k230-plic" ,"thead,c900-
> plic";
> + reg = <0xf 0x00000000 0x0 0x04000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <208>;
> + };
> +
> + clint: timer@f04000000 {
> + compatible = "canaan,k230-clint",
> "thead,c900-clint";
> + reg = <0xf 0x04000000 0x0 0x00010000>;
> + interrupts-extended = <&cpu0_intc 3>,
> <&cpu0_intc 7>;
> + };
> +
> + uart0: serial@91400000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91400000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@91401000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91401000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@91402000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91402000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@91403000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91403000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@91404000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91404000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> +};
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^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
@ 2024-03-24 16:24 ` Icenowy Zheng
0 siblings, 0 replies; 54+ messages in thread
From: Icenowy Zheng @ 2024-03-24 16:24 UTC (permalink / raw)
To: Yangyu Chen, linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel
在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan
> Kendryte
> K230 SoC [1].
>
> Some key consideration:
>
> - Only place BigCore which is 1.6GHz RV64GCBV
>
> The existence of cache coherence between the two cores remains
> unknown
> since they have dedicated L2 caches. And the factory SDK uses it for
> other OS by default. I don't know whether the two CPUs on K230 SoC
> can be used in one system. So only place BigCore here.
>
> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
> CPU1, the CSR.MHARTID of this core is 0.
>
> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>
> The user manual of C908 from T-Head does not document it
> specifically.
> It just said it supports B extension V1.0. [2]
>
> I have tested it by using this [3] which attempts to execute
> "add.uw",
> "andn", "clmulr", "bclr" and they doesn't traps on K230. But on
> JH7110,
> "clmulr" and "bclr" will trap.
>
> - Support for "zicbom" is tested by hand
>
> Have tested with some out-of-tree drivers from [4] that need DMA and
> they
> do not come to the dts currently.
>
> - Cache parameters are inferred from T-Head docs [2] and Canaan docs
> [1]
>
> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
> L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
>
> The numbers of cache sets are calculated from these parameters.
>
> - MMU only supports Sv39
>
> The T-Head docs [2] say the C908 core can be configured to support
> Sv48 and
> Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type
> in
> dts and boot the mainline kernel. However, it failed during the
> kernel
> probe and fell back to Sv39. I also tested it on M-Mode software,
> writing
> Sv48 to satp.mode will not trap but will leave the CSR unchanged.
> While
> writing Sv39, it will take effect. It shows that this CPU does not
> support
> Sv48.
>
> - Svpbmt and T-Head MAEE both supported
>
> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
> memory
> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
> is used
> here for mainline kernel support for K230. If the kernel wants to use
> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
> before
> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
> on
> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
> metal
> to Sv39, It will lose dirty cache line modifications that haven't
> been
> written back to the memory.
>
> [1]
> https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
> [2]
> https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
> [3] https://github.com/cyyself/rvb_test
> [4] https://github.com/cyyself/linux/tree/k230-mainline
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
> arch/riscv/boot/dts/canaan/Makefile | 2 +
> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
> arch/riscv/boot/dts/canaan/k230.dtsi | 140
> ++++++++++++++++++++++
> 4 files changed, 190 insertions(+)
> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>
> diff --git a/arch/riscv/boot/dts/canaan/Makefile
> b/arch/riscv/boot/dts/canaan/Makefile
> index 987d1f0c41f0..7d54ea5c6f3d 100644
> --- a/arch/riscv/boot/dts/canaan/Makefile
> +++ b/arch/riscv/boot/dts/canaan/Makefile
> @@ -1,6 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
> +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
BTW did you test on K230 EVB? I think only CanMV is currently publicly
available.
If K230 EVB support is not tested, I suggest not adding it.
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
> diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts
> b/arch/riscv/boot/dts/canaan/k230-canmv.dts
> new file mode 100644
> index 000000000000..9565915cead6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k230.dtsi"
> +
> +/ {
> + model = "Canaan CanMV-K230";
> + compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ddr: memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x20000000>;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts
> b/arch/riscv/boot/dts/canaan/k230-evb.dts
> new file mode 100644
> index 000000000000..f898b8e62368
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include "k230.dtsi"
> +
> +/ {
> + model = "Kendryte K230 EVB";
> + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-
> k230";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + ddr: memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x20000000>;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi
> b/arch/riscv/boot/dts/canaan/k230.dtsi
> new file mode 100644
> index 000000000000..7da49498945e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/canaan/k230.dtsi
> @@ -0,0 +1,140 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "canaan,kendryte-k230";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <27000000>;
> +
> + cpu@0 {
> + compatible = "thead,c908", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa =
> "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f",
> "d", "c", "v", "zba", "zbb",
> + "zbc", "zbs",
> "zicbom", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> "svpbmt";
> + riscv,cbom-block-size = <64>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <128>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + l2_cache: l2-cache {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <262144>;
> + cache-sets = <256>;
> + cache-unified;
> + };
> + };
> +
> + apb_clk: apb-clk-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <50000000>;
> + clock-output-names = "apb_clk";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + plic: interrupt-controller@f00000000 {
> + compatible = "canaan,k230-plic" ,"thead,c900-
> plic";
> + reg = <0xf 0x00000000 0x0 0x04000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <208>;
> + };
> +
> + clint: timer@f04000000 {
> + compatible = "canaan,k230-clint",
> "thead,c900-clint";
> + reg = <0xf 0x04000000 0x0 0x00010000>;
> + interrupts-extended = <&cpu0_intc 3>,
> <&cpu0_intc 7>;
> + };
> +
> + uart0: serial@91400000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91400000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@91401000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91401000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@91402000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91402000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@91403000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91403000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@91404000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x91404000 0x0 0x1000>;
> + clocks = <&apb_clk>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
2024-03-24 16:24 ` Icenowy Zheng
@ 2024-03-25 2:59 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-25 2:59 UTC (permalink / raw)
To: Icenowy Zheng
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
> On Mar 25, 2024, at 00:24, Icenowy Zheng <uwu@icenowy.me> wrote:
>
> 在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
>> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan
>> Kendryte
>> K230 SoC [1].
>>
>> Some key consideration:
>>
>> - Only place BigCore which is 1.6GHz RV64GCBV
>>
>> The existence of cache coherence between the two cores remains
>> unknown
>> since they have dedicated L2 caches. And the factory SDK uses it for
>> other OS by default. I don't know whether the two CPUs on K230 SoC
>> can be used in one system. So only place BigCore here.
>>
>> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
>> CPU1, the CSR.MHARTID of this core is 0.
>>
>> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>>
>> The user manual of C908 from T-Head does not document it
>> specifically.
>> It just said it supports B extension V1.0. [2]
>>
>> I have tested it by using this [3] which attempts to execute
>> "add.uw",
>> "andn", "clmulr", "bclr" and they doesn't traps on K230. But on
>> JH7110,
>> "clmulr" and "bclr" will trap.
>>
>> - Support for "zicbom" is tested by hand
>>
>> Have tested with some out-of-tree drivers from [4] that need DMA and
>> they
>> do not come to the dts currently.
>>
>> - Cache parameters are inferred from T-Head docs [2] and Canaan docs
>> [1]
>>
>> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
>>
>> The numbers of cache sets are calculated from these parameters.
>>
>> - MMU only supports Sv39
>>
>> The T-Head docs [2] say the C908 core can be configured to support
>> Sv48 and
>> Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type
>> in
>> dts and boot the mainline kernel. However, it failed during the
>> kernel
>> probe and fell back to Sv39. I also tested it on M-Mode software,
>> writing
>> Sv48 to satp.mode will not trap but will leave the CSR unchanged.
>> While
>> writing Sv39, it will take effect. It shows that this CPU does not
>> support
>> Sv48.
>>
>> - Svpbmt and T-Head MAEE both supported
>>
>> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
>> memory
>> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
>> is used
>> here for mainline kernel support for K230. If the kernel wants to use
>> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
>> before
>> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
>> on
>> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
>> metal
>> to Sv39, It will lose dirty cache line modifications that haven't
>> been
>> written back to the memory.
>>
>> [1]
>> https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
>> [2]
>> https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
>> [3] https://github.com/cyyself/rvb_test
>> [4] https://github.com/cyyself/linux/tree/k230-mainline
>>
>> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>> ---
>> arch/riscv/boot/dts/canaan/Makefile | 2 +
>> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
>> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
>> arch/riscv/boot/dts/canaan/k230.dtsi | 140
>> ++++++++++++++++++++++
>> 4 files changed, 190 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
>> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
>> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/canaan/Makefile
>> b/arch/riscv/boot/dts/canaan/Makefile
>> index 987d1f0c41f0..7d54ea5c6f3d 100644
>> --- a/arch/riscv/boot/dts/canaan/Makefile
>> +++ b/arch/riscv/boot/dts/canaan/Makefile
>> @@ -1,6 +1,8 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
>
> BTW did you test on K230 EVB? I think only CanMV is currently publicly
> available.
>
> If K230 EVB support is not tested, I suggest not adding it.
>
Actually I got one K230 EVB and tested on it.
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
>> diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> b/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> new file mode 100644
>> index 000000000000..9565915cead6
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include "k230.dtsi"
>> +
>> +/ {
>> + model = "Canaan CanMV-K230";
>> + compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + ddr: memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x20000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts
>> b/arch/riscv/boot/dts/canaan/k230-evb.dts
>> new file mode 100644
>> index 000000000000..f898b8e62368
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include "k230.dtsi"
>> +
>> +/ {
>> + model = "Kendryte K230 EVB";
>> + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-
>> k230";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + ddr: memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x20000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi
>> b/arch/riscv/boot/dts/canaan/k230.dtsi
>> new file mode 100644
>> index 000000000000..7da49498945e
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230.dtsi
>> @@ -0,0 +1,140 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +/dts-v1/;
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + compatible = "canaan,kendryte-k230";
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + timebase-frequency = <27000000>;
>> +
>> + cpu@0 {
>> + compatible = "thead,c908", "riscv";
>> + device_type = "cpu";
>> + reg = <0>;
>> + riscv,isa =
>> "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
>> + riscv,isa-base = "rv64i";
>> + riscv,isa-extensions = "i", "m", "a", "f",
>> "d", "c", "v", "zba", "zbb",
>> + "zbc", "zbs",
>> "zicbom", "zicntr", "zicsr",
>> + "zifencei", "zihpm",
>> "svpbmt";
>> + riscv,cbom-block-size = <64>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <128>;
>> + d-cache-size = <32768>;
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <128>;
>> + i-cache-size = <32768>;
>> + next-level-cache = <&l2_cache>;
>> + mmu-type = "riscv,sv39";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + l2_cache: l2-cache {
>> + compatible = "cache";
>> + cache-block-size = <64>;
>> + cache-level = <2>;
>> + cache-size = <262144>;
>> + cache-sets = <256>;
>> + cache-unified;
>> + };
>> + };
>> +
>> + apb_clk: apb-clk-clock {
>> + compatible = "fixed-clock";
>> + clock-frequency = <50000000>;
>> + clock-output-names = "apb_clk";
>> + #clock-cells = <0>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + interrupt-parent = <&plic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + dma-noncoherent;
>> + ranges;
>> +
>> + plic: interrupt-controller@f00000000 {
>> + compatible = "canaan,k230-plic" ,"thead,c900-
>> plic";
>> + reg = <0xf 0x00000000 0x0 0x04000000>;
>> + interrupts-extended = <&cpu0_intc 11>,
>> <&cpu0_intc 9>;
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <2>;
>> + riscv,ndev = <208>;
>> + };
>> +
>> + clint: timer@f04000000 {
>> + compatible = "canaan,k230-clint",
>> "thead,c900-clint";
>> + reg = <0xf 0x04000000 0x0 0x00010000>;
>> + interrupts-extended = <&cpu0_intc 3>,
>> <&cpu0_intc 7>;
>> + };
>> +
>> + uart0: serial@91400000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91400000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@91401000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91401000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@91402000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91402000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@91403000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91403000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@91404000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91404000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
@ 2024-03-25 2:59 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-25 2:59 UTC (permalink / raw)
To: Icenowy Zheng
Cc: linux-riscv, Conor Dooley, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
> On Mar 25, 2024, at 00:24, Icenowy Zheng <uwu@icenowy.me> wrote:
>
> 在 2024-03-23星期六的 20:12 +0800,Yangyu Chen写道:
>> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan
>> Kendryte
>> K230 SoC [1].
>>
>> Some key consideration:
>>
>> - Only place BigCore which is 1.6GHz RV64GCBV
>>
>> The existence of cache coherence between the two cores remains
>> unknown
>> since they have dedicated L2 caches. And the factory SDK uses it for
>> other OS by default. I don't know whether the two CPUs on K230 SoC
>> can be used in one system. So only place BigCore here.
>>
>> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
>> CPU1, the CSR.MHARTID of this core is 0.
>>
>> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>>
>> The user manual of C908 from T-Head does not document it
>> specifically.
>> It just said it supports B extension V1.0. [2]
>>
>> I have tested it by using this [3] which attempts to execute
>> "add.uw",
>> "andn", "clmulr", "bclr" and they doesn't traps on K230. But on
>> JH7110,
>> "clmulr" and "bclr" will trap.
>>
>> - Support for "zicbom" is tested by hand
>>
>> Have tested with some out-of-tree drivers from [4] that need DMA and
>> they
>> do not come to the dts currently.
>>
>> - Cache parameters are inferred from T-Head docs [2] and Canaan docs
>> [1]
>>
>> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L2: 256KB, PIPT 16-way set-associative, 64B Cacheline
>>
>> The numbers of cache sets are calculated from these parameters.
>>
>> - MMU only supports Sv39
>>
>> The T-Head docs [2] say the C908 core can be configured to support
>> Sv48 and
>> Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type
>> in
>> dts and boot the mainline kernel. However, it failed during the
>> kernel
>> probe and fell back to Sv39. I also tested it on M-Mode software,
>> writing
>> Sv48 to satp.mode will not trap but will leave the CSR unchanged.
>> While
>> writing Sv39, it will take effect. It shows that this CPU does not
>> support
>> Sv48.
>>
>> - Svpbmt and T-Head MAEE both supported
>>
>> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
>> memory
>> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
>> is used
>> here for mainline kernel support for K230. If the kernel wants to use
>> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
>> before
>> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
>> on
>> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
>> metal
>> to Sv39, It will lose dirty cache line modifications that haven't
>> been
>> written back to the memory.
>>
>> [1]
>> https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
>> [2]
>> https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
>> [3] https://github.com/cyyself/rvb_test
>> [4] https://github.com/cyyself/linux/tree/k230-mainline
>>
>> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>> ---
>> arch/riscv/boot/dts/canaan/Makefile | 2 +
>> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++
>> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++
>> arch/riscv/boot/dts/canaan/k230.dtsi | 140
>> ++++++++++++++++++++++
>> 4 files changed, 190 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
>> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
>> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/canaan/Makefile
>> b/arch/riscv/boot/dts/canaan/Makefile
>> index 987d1f0c41f0..7d54ea5c6f3d 100644
>> --- a/arch/riscv/boot/dts/canaan/Makefile
>> +++ b/arch/riscv/boot/dts/canaan/Makefile
>> @@ -1,6 +1,8 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
>
> BTW did you test on K230 EVB? I think only CanMV is currently publicly
> available.
>
> If K230 EVB support is not tested, I suggest not adding it.
>
Actually I got one K230 EVB and tested on it.
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
>> dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
>> diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> b/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> new file mode 100644
>> index 000000000000..9565915cead6
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include "k230.dtsi"
>> +
>> +/ {
>> + model = "Canaan CanMV-K230";
>> + compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + ddr: memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x20000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts
>> b/arch/riscv/boot/dts/canaan/k230-evb.dts
>> new file mode 100644
>> index 000000000000..f898b8e62368
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include "k230.dtsi"
>> +
>> +/ {
>> + model = "Kendryte K230 EVB";
>> + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-
>> k230";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + ddr: memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x20000000>;
>> + };
>> +};
>> +
>> +&uart0 {
>> + status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi
>> b/arch/riscv/boot/dts/canaan/k230.dtsi
>> new file mode 100644
>> index 000000000000..7da49498945e
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/k230.dtsi
>> @@ -0,0 +1,140 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +/dts-v1/;
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + compatible = "canaan,kendryte-k230";
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + timebase-frequency = <27000000>;
>> +
>> + cpu@0 {
>> + compatible = "thead,c908", "riscv";
>> + device_type = "cpu";
>> + reg = <0>;
>> + riscv,isa =
>> "rv64imafdcv_zba_zbb_zbc_zbs_zicbom_svpbmt";
>> + riscv,isa-base = "rv64i";
>> + riscv,isa-extensions = "i", "m", "a", "f",
>> "d", "c", "v", "zba", "zbb",
>> + "zbc", "zbs",
>> "zicbom", "zicntr", "zicsr",
>> + "zifencei", "zihpm",
>> "svpbmt";
>> + riscv,cbom-block-size = <64>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <128>;
>> + d-cache-size = <32768>;
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <128>;
>> + i-cache-size = <32768>;
>> + next-level-cache = <&l2_cache>;
>> + mmu-type = "riscv,sv39";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + l2_cache: l2-cache {
>> + compatible = "cache";
>> + cache-block-size = <64>;
>> + cache-level = <2>;
>> + cache-size = <262144>;
>> + cache-sets = <256>;
>> + cache-unified;
>> + };
>> + };
>> +
>> + apb_clk: apb-clk-clock {
>> + compatible = "fixed-clock";
>> + clock-frequency = <50000000>;
>> + clock-output-names = "apb_clk";
>> + #clock-cells = <0>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + interrupt-parent = <&plic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + dma-noncoherent;
>> + ranges;
>> +
>> + plic: interrupt-controller@f00000000 {
>> + compatible = "canaan,k230-plic" ,"thead,c900-
>> plic";
>> + reg = <0xf 0x00000000 0x0 0x04000000>;
>> + interrupts-extended = <&cpu0_intc 11>,
>> <&cpu0_intc 9>;
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <2>;
>> + riscv,ndev = <208>;
>> + };
>> +
>> + clint: timer@f04000000 {
>> + compatible = "canaan,k230-clint",
>> "thead,c900-clint";
>> + reg = <0xf 0x04000000 0x0 0x00010000>;
>> + interrupts-extended = <&cpu0_intc 3>,
>> <&cpu0_intc 7>;
>> + };
>> +
>> + uart0: serial@91400000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91400000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@91401000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91401000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@91402000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91402000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@91403000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91403000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@91404000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x0 0x91404000 0x0 0x1000>;
>> + clocks = <&apb_clk>;
>> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + status = "disabled";
>> + };
>> + };
>> +};
>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
2024-03-23 12:12 ` Yangyu Chen
@ 2024-03-25 2:03 ` Qingfang Deng
-1 siblings, 0 replies; 54+ messages in thread
From: Qingfang Deng @ 2024-03-25 2:03 UTC (permalink / raw)
To: cyy
Cc: aou, conor, devicetree, dlemoal, guoren, krzysztof.kozlowski+dt,
linus.walleij, linux-clk, linux-gpio, linux-kernel, linux-riscv,
mturquette, p.zabel, palmer, paul.walmsley, robh+dt, sboyd
Hi Yangyu,
> - Support for "zicbom" is tested by hand
C908 also supports zicbop and zicboz. You may add them as well.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
@ 2024-03-25 2:03 ` Qingfang Deng
0 siblings, 0 replies; 54+ messages in thread
From: Qingfang Deng @ 2024-03-25 2:03 UTC (permalink / raw)
To: cyy
Cc: aou, conor, devicetree, dlemoal, guoren, krzysztof.kozlowski+dt,
linus.walleij, linux-clk, linux-gpio, linux-kernel, linux-riscv,
mturquette, p.zabel, palmer, paul.walmsley, robh+dt, sboyd
Hi Yangyu,
> - Support for "zicbom" is tested by hand
C908 also supports zicbop and zicboz. You may add them as well.
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
2024-03-25 2:03 ` Qingfang Deng
@ 2024-03-25 2:57 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-25 2:57 UTC (permalink / raw)
To: Qingfang Deng
Cc: Albert Ou, Conor Dooley, devicetree, Damien Le Moal, Guo Ren,
Krzysztof Kozlowski, linus.walleij, linux-clk, linux-gpio,
linux-kernel, linux-riscv, mturquette, p.zabel, Palmer Dabbelt,
Paul Walmsley, Rob Herring, sboyd
Thanks. I will add them at next revision.
> On Mar 25, 2024, at 10:03, Qingfang Deng <dqfext@gmail.com> wrote:
>
> Hi Yangyu,
>
>> - Support for "zicbom" is tested by hand
>
> C908 also supports zicbop and zicboz. You may add them as well.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
@ 2024-03-25 2:57 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-25 2:57 UTC (permalink / raw)
To: Qingfang Deng
Cc: Albert Ou, Conor Dooley, devicetree, Damien Le Moal, Guo Ren,
Krzysztof Kozlowski, linus.walleij, linux-clk, linux-gpio,
linux-kernel, linux-riscv, mturquette, p.zabel, Palmer Dabbelt,
Paul Walmsley, Rob Herring, sboyd
Thanks. I will add them at next revision.
> On Mar 25, 2024, at 10:03, Qingfang Deng <dqfext@gmail.com> wrote:
>
> Hi Yangyu,
>
>> - Support for "zicbom" is tested by hand
>
> C908 also supports zicbop and zicboz. You may add them as well.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH v6 11/11] riscv: config: enable ARCH_CANAAN in defconfig
2024-03-23 12:09 ` Yangyu Chen
@ 2024-03-23 12:12 ` Yangyu Chen
-1 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Conor Dooley
Since K230 has been supported, allow ARCH_CANAAN to be selected to build dt
and drivers for it in defconfig.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index eaf34e871e30..1d5524cdd47d 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -33,6 +33,7 @@ CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_THEAD=y
CONFIG_SOC_VIRT=y
+CONFIG_ARCH_CANAAN=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
--
2.43.0
^ permalink raw reply related [flat|nested] 54+ messages in thread
* [PATCH v6 11/11] riscv: config: enable ARCH_CANAAN in defconfig
@ 2024-03-23 12:12 ` Yangyu Chen
0 siblings, 0 replies; 54+ messages in thread
From: Yangyu Chen @ 2024-03-23 12:12 UTC (permalink / raw)
To: linux-riscv
Cc: Conor Dooley, Damien Le Moal, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
linux-gpio, linux-clk, devicetree, linux-kernel, Yangyu Chen,
Conor Dooley
Since K230 has been supported, allow ARCH_CANAAN to be selected to build dt
and drivers for it in defconfig.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index eaf34e871e30..1d5524cdd47d 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -33,6 +33,7 @@ CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_THEAD=y
CONFIG_SOC_VIRT=y
+CONFIG_ARCH_CANAAN=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 54+ messages in thread
* Re: [PATCH v6 00/11] riscv: add initial support for Canaan Kendryte K230
2024-03-23 12:09 ` Yangyu Chen
@ 2024-04-03 18:22 ` Palmer Dabbelt
-1 siblings, 0 replies; 54+ messages in thread
From: Palmer Dabbelt @ 2024-04-03 18:22 UTC (permalink / raw)
To: cyy
Cc: linux-riscv, Conor Dooley, dlemoal, robh+dt,
krzysztof.kozlowski+dt, Paul Walmsley, aou, guoren, mturquette,
sboyd, linus.walleij, p.zabel, linux-gpio, linux-clk, devicetree,
linux-kernel, cyy
On Sat, 23 Mar 2024 05:09:42 PDT (-0700), cyy@cyyself.name wrote:
> K230 is an ideal chip for RISC-V Vector 1.0 evaluation now. Add initial
> support for it to allow more people to participate in building drivers
> to mainline for it.
>
> This kernel has been tested upon factory SDK [1] with
> k230_evb_only_linux_defconfig and patched mainline opensbi [2] to skip
> locked pmp and successfully booted to busybox on initrd with this log [3].
>
> [1] https://github.com/kendryte/k230_sdk
> [2] https://github.com/cyyself/opensbi/tree/k230
> [3] https://gist.github.com/cyyself/b9445f38cc3ba1094924bd41c9086176
>
> Changes since v5:
> - Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210 SoCs
> - Modify existing K210 drivers depends on SOC_CANAAN_K210 symbol
> - Reword dts commit message
> - Modify dts to use Full 512MB memory
> - Rebase to linux mainline master
>
> Changes since v4:
> - Reword commit message on dts that the B-ext version of c908 is 1.0 rather
> than 1.0-rc1
>
> v4: https://lore.kernel.org/linux-riscv/tencent_587730262984A011834F42D0563BC6B10405@qq.com/
>
> Changes since v3:
> - Refactor Kconfig.soc which uses ARCH_CANAAN for regular Canaan SoCs and
> rename SOC_CANAAN to SOC_CANAAN_K210 for K210 in patch [5/7]
> - Sort dt-binding stings on Cannan SoCs in alphanumerical order
>
> v3: https://lore.kernel.org/linux-riscv/tencent_BB2364BBF1812F4E304F7BDDD11E57356605@qq.com/
>
> Changes since v2:
> - Add MIT License to dts file
> - Sort dt-binding stings in alphanumerical order
> - Sort filename in dts Makefile in alphanumerical order
> - Rename canmv-k230.dts to k230-canmv.dts
>
> v2: https://lore.kernel.org/linux-riscv/tencent_64A9B4B31C2D70D5633042461AC9F80C0509@qq.com/
>
> Changes since v1:
> - Patch dt-bindings in clint and plic
> - Use enum in K230 compatible dt bindings
> - Fix dts to pass `make dtbs_check`
> - Add more details in commit message
>
> v1: https://lore.kernel.org/linux-riscv/tencent_E15F8FE0B6769E6338AE690C7F4844A31706@qq.com/
>
> Yangyu Chen (11):
> dt-bindings: riscv: Add T-HEAD C908 compatible
> dt-bindings: add Canaan K230 boards compatible strings
> dt-bindings: timer: Add Canaan K230 CLINT
> dt-bindings: interrupt-controller: Add Canaan K230 PLIC
> riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
> soc: canaan: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210
> clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
> pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
> reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
> riscv: dts: add initial canmv-k230 and k230-evb dts
> riscv: config: enable ARCH_CANAAN in defconfig
>
> .../sifive,plic-1.0.0.yaml | 1 +
> .../devicetree/bindings/riscv/canaan.yaml | 8 +-
> .../devicetree/bindings/riscv/cpus.yaml | 1 +
> .../bindings/timer/sifive,clint.yaml | 1 +
> arch/riscv/Kconfig.socs | 8 +-
> arch/riscv/Makefile | 2 +-
> arch/riscv/boot/dts/canaan/Makefile | 2 +
> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 +++
> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 +++
> arch/riscv/boot/dts/canaan/k230.dtsi | 140 ++++++++++++++++++
> arch/riscv/configs/defconfig | 1 +
> arch/riscv/configs/nommu_k210_defconfig | 3 +-
> .../riscv/configs/nommu_k210_sdcard_defconfig | 3 +-
> drivers/clk/Kconfig | 4 +-
> drivers/pinctrl/Kconfig | 4 +-
> drivers/reset/Kconfig | 4 +-
> drivers/soc/Makefile | 2 +-
> drivers/soc/canaan/Kconfig | 4 +-
> 18 files changed, 220 insertions(+), 16 deletions(-)
> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>
> base-commit: 8e938e39866920ddc266898e6ae1fffc5c8f51aa
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH v6 00/11] riscv: add initial support for Canaan Kendryte K230
@ 2024-04-03 18:22 ` Palmer Dabbelt
0 siblings, 0 replies; 54+ messages in thread
From: Palmer Dabbelt @ 2024-04-03 18:22 UTC (permalink / raw)
To: cyy
Cc: linux-riscv, Conor Dooley, dlemoal, robh+dt,
krzysztof.kozlowski+dt, Paul Walmsley, aou, guoren, mturquette,
sboyd, linus.walleij, p.zabel, linux-gpio, linux-clk, devicetree,
linux-kernel, cyy
On Sat, 23 Mar 2024 05:09:42 PDT (-0700), cyy@cyyself.name wrote:
> K230 is an ideal chip for RISC-V Vector 1.0 evaluation now. Add initial
> support for it to allow more people to participate in building drivers
> to mainline for it.
>
> This kernel has been tested upon factory SDK [1] with
> k230_evb_only_linux_defconfig and patched mainline opensbi [2] to skip
> locked pmp and successfully booted to busybox on initrd with this log [3].
>
> [1] https://github.com/kendryte/k230_sdk
> [2] https://github.com/cyyself/opensbi/tree/k230
> [3] https://gist.github.com/cyyself/b9445f38cc3ba1094924bd41c9086176
>
> Changes since v5:
> - Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210 SoCs
> - Modify existing K210 drivers depends on SOC_CANAAN_K210 symbol
> - Reword dts commit message
> - Modify dts to use Full 512MB memory
> - Rebase to linux mainline master
>
> Changes since v4:
> - Reword commit message on dts that the B-ext version of c908 is 1.0 rather
> than 1.0-rc1
>
> v4: https://lore.kernel.org/linux-riscv/tencent_587730262984A011834F42D0563BC6B10405@qq.com/
>
> Changes since v3:
> - Refactor Kconfig.soc which uses ARCH_CANAAN for regular Canaan SoCs and
> rename SOC_CANAAN to SOC_CANAAN_K210 for K210 in patch [5/7]
> - Sort dt-binding stings on Cannan SoCs in alphanumerical order
>
> v3: https://lore.kernel.org/linux-riscv/tencent_BB2364BBF1812F4E304F7BDDD11E57356605@qq.com/
>
> Changes since v2:
> - Add MIT License to dts file
> - Sort dt-binding stings in alphanumerical order
> - Sort filename in dts Makefile in alphanumerical order
> - Rename canmv-k230.dts to k230-canmv.dts
>
> v2: https://lore.kernel.org/linux-riscv/tencent_64A9B4B31C2D70D5633042461AC9F80C0509@qq.com/
>
> Changes since v1:
> - Patch dt-bindings in clint and plic
> - Use enum in K230 compatible dt bindings
> - Fix dts to pass `make dtbs_check`
> - Add more details in commit message
>
> v1: https://lore.kernel.org/linux-riscv/tencent_E15F8FE0B6769E6338AE690C7F4844A31706@qq.com/
>
> Yangyu Chen (11):
> dt-bindings: riscv: Add T-HEAD C908 compatible
> dt-bindings: add Canaan K230 boards compatible strings
> dt-bindings: timer: Add Canaan K230 CLINT
> dt-bindings: interrupt-controller: Add Canaan K230 PLIC
> riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
> soc: canaan: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210
> clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
> pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
> reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
> riscv: dts: add initial canmv-k230 and k230-evb dts
> riscv: config: enable ARCH_CANAAN in defconfig
>
> .../sifive,plic-1.0.0.yaml | 1 +
> .../devicetree/bindings/riscv/canaan.yaml | 8 +-
> .../devicetree/bindings/riscv/cpus.yaml | 1 +
> .../bindings/timer/sifive,clint.yaml | 1 +
> arch/riscv/Kconfig.socs | 8 +-
> arch/riscv/Makefile | 2 +-
> arch/riscv/boot/dts/canaan/Makefile | 2 +
> arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 +++
> arch/riscv/boot/dts/canaan/k230-evb.dts | 24 +++
> arch/riscv/boot/dts/canaan/k230.dtsi | 140 ++++++++++++++++++
> arch/riscv/configs/defconfig | 1 +
> arch/riscv/configs/nommu_k210_defconfig | 3 +-
> .../riscv/configs/nommu_k210_sdcard_defconfig | 3 +-
> drivers/clk/Kconfig | 4 +-
> drivers/pinctrl/Kconfig | 4 +-
> drivers/reset/Kconfig | 4 +-
> drivers/soc/Makefile | 2 +-
> drivers/soc/canaan/Kconfig | 4 +-
> 18 files changed, 220 insertions(+), 16 deletions(-)
> create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
> create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>
> base-commit: 8e938e39866920ddc266898e6ae1fffc5c8f51aa
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
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