* [PATCH] perf/x86: enable Intel Cedarview Atom suppport
@ 2012-08-20 9:24 Stephane Eranian
2012-08-20 9:41 ` Andi Kleen
2012-09-04 18:52 ` [tip:perf/urgent] perf/x86: Enable " tip-bot for Stephane Eranian
0 siblings, 2 replies; 4+ messages in thread
From: Stephane Eranian @ 2012-08-20 9:24 UTC (permalink / raw)
To: linux-kernel; +Cc: peterz, mingo, andi, zheng.z.yan
This patch enables perf_events support for Intel Cedarview
Atom (model 54) processors. Support includes PEBS and LBR.
Tested on my Atom N2600 netbook.
Signed-off-by: Stephane Eranian <eranian@google.com>
---
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 7f2739e..0d3d63a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
break;
case 28: /* Atom */
+ case 54: /* Cedariew */
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 520b426..da02e9c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
* to have an operational LBR which can freeze
* on PMU interrupt
*/
- if (boot_cpu_data.x86_mask < 10) {
+ if (boot_cpu_data.x86_model == 28
+ && boot_cpu_data.x86_mask < 10) {
pr_cont("LBR disabled due to erratum");
return;
}
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] perf/x86: enable Intel Cedarview Atom suppport
2012-08-20 9:24 [PATCH] perf/x86: enable Intel Cedarview Atom suppport Stephane Eranian
@ 2012-08-20 9:41 ` Andi Kleen
2012-08-20 10:06 ` Stephane Eranian
2012-09-04 18:52 ` [tip:perf/urgent] perf/x86: Enable " tip-bot for Stephane Eranian
1 sibling, 1 reply; 4+ messages in thread
From: Andi Kleen @ 2012-08-20 9:41 UTC (permalink / raw)
To: Stephane Eranian; +Cc: linux-kernel, peterz, mingo, andi, zheng.z.yan
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 7f2739e..0d3d63a 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
> break;
>
> case 28: /* Atom */
> + case 54: /* Cedariew */
Ack. We currently miss some more 32nm Atoms too, will send patches soon.
> memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
> sizeof(hw_cache_event_ids));
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> index 520b426..da02e9c 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> @@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
> * to have an operational LBR which can freeze
> * on PMU interrupt
> */
> - if (boot_cpu_data.x86_mask < 10) {
> + if (boot_cpu_data.x86_model == 28
> + && boot_cpu_data.x86_mask < 10) {
Is that correct?
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] perf/x86: enable Intel Cedarview Atom suppport
2012-08-20 9:41 ` Andi Kleen
@ 2012-08-20 10:06 ` Stephane Eranian
0 siblings, 0 replies; 4+ messages in thread
From: Stephane Eranian @ 2012-08-20 10:06 UTC (permalink / raw)
To: Andi Kleen; +Cc: linux-kernel, peterz, mingo, zheng.z.yan
On Mon, Aug 20, 2012 at 11:41 AM, Andi Kleen <andi@firstfloor.org> wrote:
>> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
>> index 7f2739e..0d3d63a 100644
>> --- a/arch/x86/kernel/cpu/perf_event_intel.c
>> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
>> @@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
>> break;
>>
>> case 28: /* Atom */
>> + case 54: /* Cedariew */
>
> Ack. We currently miss some more 32nm Atoms too, will send patches soon.
>
>> memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
>> sizeof(hw_cache_event_ids));
>>
>> diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
>> index 520b426..da02e9c 100644
>> --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
>> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
>> @@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
>> * to have an operational LBR which can freeze
>> * on PMU interrupt
>> */
>> - if (boot_cpu_data.x86_mask < 10) {
>> + if (boot_cpu_data.x86_model == 28
>> + && boot_cpu_data.x86_mask < 10) {
>
> Is that correct?
>
Yes, had to do that to re-enable LBR on Cedarview.
The < 10 is a trick to disable LBR on very old Atom (prior to N4xx generation).
^ permalink raw reply [flat|nested] 4+ messages in thread
* [tip:perf/urgent] perf/x86: Enable Intel Cedarview Atom suppport
2012-08-20 9:24 [PATCH] perf/x86: enable Intel Cedarview Atom suppport Stephane Eranian
2012-08-20 9:41 ` Andi Kleen
@ 2012-09-04 18:52 ` tip-bot for Stephane Eranian
1 sibling, 0 replies; 4+ messages in thread
From: tip-bot for Stephane Eranian @ 2012-09-04 18:52 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, eranian, hpa, mingo, a.p.zijlstra, tglx
Commit-ID: 3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4
Gitweb: http://git.kernel.org/tip/3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4
Author: Stephane Eranian <eranian@google.com>
AuthorDate: Mon, 20 Aug 2012 11:24:21 +0200
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 4 Sep 2012 17:29:23 +0200
perf/x86: Enable Intel Cedarview Atom suppport
This patch enables perf_events support for Intel Cedarview
Atom (model 54) processors. Support includes PEBS and LBR.
Tested on my Atom N2600 netbook.
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/20120820092421.GA11284@quad
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/perf_event_intel.c | 1 +
arch/x86/kernel/cpu/perf_event_intel_lbr.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 7f2739e..0d3d63a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
break;
case 28: /* Atom */
+ case 54: /* Cedariew */
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 520b426..da02e9c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
* to have an operational LBR which can freeze
* on PMU interrupt
*/
- if (boot_cpu_data.x86_mask < 10) {
+ if (boot_cpu_data.x86_model == 28
+ && boot_cpu_data.x86_mask < 10) {
pr_cont("LBR disabled due to erratum");
return;
}
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2012-08-20 9:24 [PATCH] perf/x86: enable Intel Cedarview Atom suppport Stephane Eranian
2012-08-20 9:41 ` Andi Kleen
2012-08-20 10:06 ` Stephane Eranian
2012-09-04 18:52 ` [tip:perf/urgent] perf/x86: Enable " tip-bot for Stephane Eranian
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