From: Keith Packard <keithp@keithp.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Jesse Barnes <jbarnes@virtuousgeek.org>,
Dave Airlie <airlied@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: no LVDS on Intel SandyBridge SDVs
Date: Tue, 21 Dec 2010 12:12:42 -0800 [thread overview]
Message-ID: <yunwrn2q405.fsf@aiko.keithp.com> (raw)
In-Reply-To: <5b55a1$j1b72o@fmsmga002.fm.intel.com>
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On Tue, 21 Dec 2010 19:55:15 +0000, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> The test we do is simply whether the LVDS i2c pins are addressable. That
> requires differentiating between an IO error and a NAK, which at present
> is only possible using GMBUS. The reference to this method I found in the
> BIOS writers' guide, but of course that doesn't actually explain how it
> works (especially the significance of address 0xa0).
I can't see how that would work without an i2c receiver on the DDC
bus...
But, then, I've been surprised by DDC in the past, so perhaps it's worth
a test on a device that has LVDS but does not have EDID.
--
keith.packard@intel.com
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next prev parent reply other threads:[~2010-12-21 20:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-20 20:05 [PATCH] drm/i915: no LVDS on Intel SandyBridge SDVs Jesse Barnes
2010-12-20 20:46 ` Chris Wilson
2010-12-21 2:43 ` Dave Airlie
2010-12-21 2:53 ` Jesse Barnes
2010-12-21 11:36 ` Chris Wilson
2010-12-21 18:14 ` Keith Packard
2010-12-21 19:55 ` Chris Wilson
2010-12-21 20:12 ` Keith Packard [this message]
2010-12-22 14:47 ` Chris Wilson
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