Re: [PATCH v9 1/10] x86, mm, pat: Set WT to PA7 slot of PAT MSR

From: Thomas Gleixner <tglx@linutronix.de>
To: Toshi Kani <toshi.kani@hp.com>
Cc: hpa@zytor.com, mingo@redhat.com, akpm@linux-foundation.org,
	arnd@arndb.de, linux-mm@kvack.org, linux-kernel@vger.kernel.org,
	x86@kernel.org, linux-nvdimm@ml01.01.org, jgross@suse.com,
	stefan.bader@canonical.com, luto@amacapital.net, hmh@hmh.eng.br,
	yigal@plexistor.com, konrad.wilk@oracle.com, Elliott@hp.com,
	mcgrof@suse.com, hch@lst.de
Subject: Re: [PATCH v9 1/10] x86, mm, pat: Set WT to PA7 slot of PAT MSR
Date: Fri, 22 May 2015 08:55:49 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.11.1505220855330.5457@nanos> (raw)
In-Reply-To: <1431551151-19124-2-git-send-email-toshi.kani@hp.com>

On Wed, 13 May 2015, Toshi Kani wrote:
> This patch sets WT to the PA7 slot in the PAT MSR when the processor
> is not affected by the PAT errata.  The PA7 slot is chosen to improve
> robustness in the presence of errata that might cause the high PAT bit
> to be ignored.  This way a buggy PA7 slot access will hit the PA3 slot,
> which is UC, so at worst we lose performance without causing a correctness
> issue.
> 
> The following Intel processors are affected by the PAT errata.
> 
>    errata               cpuid
>    ----------------------------------------------------
>    Pentium 2, A52       family 0x6, model 0x5
>    Pentium 3, E27       family 0x6, model 0x7, 0x8
>    Pentium 3 Xenon, G26 family 0x6, model 0x7, 0x8, 0xa
>    Pentium M, Y26       family 0x6, model 0x9
>    Pentium M 90nm, X9   family 0x6, model 0xd
>    Pentium 4, N46       family 0xf, model 0x0
> 
> Instead of making sharp boundary checks, this patch makes conservative
> checks to exclude all Pentium 2, 3, M and 4 family processors.  For
> such processors, _PAGE_CACHE_MODE_WT is redirected to UC- per the
> default setup in __cachemode2pte_tbl[].
> 
> Signed-off-by: Toshi Kani <toshi.kani@hp.com>
> Reviewed-by: Juergen Gross <jgross@suse.com>

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>