From: "Maciej W. Rozycki" <macro@orcam.me.uk> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Damien Le Moal <damien.lemoal@opensource.wdc.com>, linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] serial: sifive: Report actual baud base rather than fixed 115200 Date: Fri, 29 Apr 2022 21:40:18 +0100 (BST) [thread overview] Message-ID: <alpine.DEB.2.21.2204291656280.9383@angie.orcam.me.uk> (raw) In-Reply-To: <alpine.DEB.2.21.2204281344190.9383@angie.orcam.me.uk> The base baud value reported is supposed to be the highest baud rate that can be set for a serial port. The SiFive FU740-C000 SOC's on-chip UART supports baud rates of up to 1/16 of the input clock rate, which is the bus clock `tlclk'[1], often at 130MHz in the case of the HiFive Unmatched board. However the sifive UART driver reports a fixed value of 115200 instead: 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 115200) is a SiFive UART v0 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 115200) is a SiFive UART v0 even though we already support setting higher baud rates, e.g.: $ tty /dev/ttySIF1 $ stty speed 230400 The baud base value is computed by the serial core by dividing the UART clock recorded in `struct uart_port' by 16, which is also the minimum value of the clock divider supported, so correct the baud base value reported by setting the UART clock recorded to the input clock rate rather than 115200: 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 8125000) is a SiFive UART v0 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 8125000) is a SiFive UART v0 References: [1] "SiFive FU740-C000 Manual", v1p3, SiFive, Inc., August 13, 2021, Section 16.9 "Baud Rate Divisor Register (div)", pp.143-144 Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Fixes: 1f1496a923b6 ("riscv: Fix sifive serial driver") --- drivers/tty/serial/sifive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) linux-serial-sifive-base-baud.diff Index: linux-macro/drivers/tty/serial/sifive.c =================================================================== --- linux-macro.orig/drivers/tty/serial/sifive.c +++ linux-macro/drivers/tty/serial/sifive.c @@ -998,7 +998,7 @@ static int sifive_serial_probe(struct pl /* Set up clock divider */ ssp->clkin_rate = clk_get_rate(ssp->clk); ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; - ssp->port.uartclk = ssp->baud_rate * 16; + ssp->port.uartclk = ssp->clkin_rate; __ssp_update_div(ssp); platform_set_drvdata(pdev, ssp);
WARNING: multiple messages have this Message-ID (diff)
From: "Maciej W. Rozycki" <macro@orcam.me.uk> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: Damien Le Moal <damien.lemoal@opensource.wdc.com>, linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] serial: sifive: Report actual baud base rather than fixed 115200 Date: Fri, 29 Apr 2022 21:40:18 +0100 (BST) [thread overview] Message-ID: <alpine.DEB.2.21.2204291656280.9383@angie.orcam.me.uk> (raw) In-Reply-To: <alpine.DEB.2.21.2204281344190.9383@angie.orcam.me.uk> The base baud value reported is supposed to be the highest baud rate that can be set for a serial port. The SiFive FU740-C000 SOC's on-chip UART supports baud rates of up to 1/16 of the input clock rate, which is the bus clock `tlclk'[1], often at 130MHz in the case of the HiFive Unmatched board. However the sifive UART driver reports a fixed value of 115200 instead: 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 115200) is a SiFive UART v0 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 115200) is a SiFive UART v0 even though we already support setting higher baud rates, e.g.: $ tty /dev/ttySIF1 $ stty speed 230400 The baud base value is computed by the serial core by dividing the UART clock recorded in `struct uart_port' by 16, which is also the minimum value of the clock divider supported, so correct the baud base value reported by setting the UART clock recorded to the input clock rate rather than 115200: 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 8125000) is a SiFive UART v0 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 8125000) is a SiFive UART v0 References: [1] "SiFive FU740-C000 Manual", v1p3, SiFive, Inc., August 13, 2021, Section 16.9 "Baud Rate Divisor Register (div)", pp.143-144 Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Fixes: 1f1496a923b6 ("riscv: Fix sifive serial driver") --- drivers/tty/serial/sifive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) linux-serial-sifive-base-baud.diff Index: linux-macro/drivers/tty/serial/sifive.c =================================================================== --- linux-macro.orig/drivers/tty/serial/sifive.c +++ linux-macro/drivers/tty/serial/sifive.c @@ -998,7 +998,7 @@ static int sifive_serial_probe(struct pl /* Set up clock divider */ ssp->clkin_rate = clk_get_rate(ssp->clk); ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; - ssp->port.uartclk = ssp->baud_rate * 16; + ssp->port.uartclk = ssp->clkin_rate; __ssp_update_div(ssp); platform_set_drvdata(pdev, ssp); _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-04-29 20:40 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-29 20:40 [PATCH 0/2] serial: sifive: Correct/improve baud base handling Maciej W. Rozycki 2022-04-29 20:40 ` Maciej W. Rozycki 2022-04-29 20:40 ` Maciej W. Rozycki [this message] 2022-04-29 20:40 ` [PATCH 1/2] serial: sifive: Report actual baud base rather than fixed 115200 Maciej W. Rozycki 2022-04-29 20:40 ` [PATCH 2/2] serial: sifive: Remove duplicate `clkin_rate' setting Maciej W. Rozycki 2022-04-29 20:40 ` Maciej W. Rozycki
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