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From: Paul Walmsley <paul.walmsley@sifive.com>
To: Christoph Hellwig <hch@lst.de>
Cc: Sebastian Reichel <sre@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, peter.maydell@linaro.org
Subject: Re: [PATCH 1/2] dt-bindings: power: reset: document the QEMU RISC-V virt machine poweroff device
Date: Thu, 7 Nov 2019 14:32:01 -0800 (PST)	[thread overview]
Message-ID: <alpine.DEB.2.21.9999.1911071431390.8918@viisi.sifive.com> (raw)
In-Reply-To: <20191107212408.11857-2-hch@lst.de>

On Thu, 7 Nov 2019, Christoph Hellwig wrote:

> Add the binding for the trivial Qemu RISC-V poweroff mechanism, which is

There's nothing RISC-V specific here.  This IP isn't defined in the RISC-V 
specifications, or anything like that.  

Apparently it's a SiFive IP block which now has a virtual IP 
implementation in QEMU in hw/riscv/sifive_test.c.  But since there's 
nothing RISC-V specific about this IP block, any QEMU system, with any CPU 
implementation, should be able to use this virtual IP, and this Linux 
driver.

For these reasons, it's better if "RISC-V" is just removed from everywhere 
in this driver.  If something needs to go in its place, "SiFive" may be 
better.


- Paul


> just a single MMIO register exposed through the DT.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  .../power/reset/qemu-riscv-virt-poweroff.txt     | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt b/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt
> new file mode 100644
> index 000000000000..80ff6fd4e3b7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt
> @@ -0,0 +1,16 @@
> +QEMU RISC-V virt machine poweroff device
> +
> +This is a device in Qemu that can signal successful or error exit
> +by writing two magic numbers to a trivial mmio register.
> +A Linux poweroff is implemented as successful exit.
> +
> +Required Properties:
> +-compatible: "sifive,test0"
> +-reg: Specifies the physical address of the register
> +
> +Example:
> +
> +	test@100000 {
> +		compatible = "sifive,test0";
> +		reg = <0x100000 0x1000>;
> +	};
> -- 
> 2.20.1
> 
> 


- Paul

WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <paul.walmsley@sifive.com>
To: Christoph Hellwig <hch@lst.de>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
	peter.maydell@linaro.org, Sebastian Reichel <sre@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH 1/2] dt-bindings: power: reset: document the QEMU RISC-V virt machine poweroff device
Date: Thu, 7 Nov 2019 14:32:01 -0800 (PST)	[thread overview]
Message-ID: <alpine.DEB.2.21.9999.1911071431390.8918@viisi.sifive.com> (raw)
In-Reply-To: <20191107212408.11857-2-hch@lst.de>

On Thu, 7 Nov 2019, Christoph Hellwig wrote:

> Add the binding for the trivial Qemu RISC-V poweroff mechanism, which is

There's nothing RISC-V specific here.  This IP isn't defined in the RISC-V 
specifications, or anything like that.  

Apparently it's a SiFive IP block which now has a virtual IP 
implementation in QEMU in hw/riscv/sifive_test.c.  But since there's 
nothing RISC-V specific about this IP block, any QEMU system, with any CPU 
implementation, should be able to use this virtual IP, and this Linux 
driver.

For these reasons, it's better if "RISC-V" is just removed from everywhere 
in this driver.  If something needs to go in its place, "SiFive" may be 
better.


- Paul


> just a single MMIO register exposed through the DT.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  .../power/reset/qemu-riscv-virt-poweroff.txt     | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt b/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt
> new file mode 100644
> index 000000000000..80ff6fd4e3b7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/reset/qemu-riscv-virt-poweroff.txt
> @@ -0,0 +1,16 @@
> +QEMU RISC-V virt machine poweroff device
> +
> +This is a device in Qemu that can signal successful or error exit
> +by writing two magic numbers to a trivial mmio register.
> +A Linux poweroff is implemented as successful exit.
> +
> +Required Properties:
> +-compatible: "sifive,test0"
> +-reg: Specifies the physical address of the register
> +
> +Example:
> +
> +	test@100000 {
> +		compatible = "sifive,test0";
> +		reg = <0x100000 0x1000>;
> +	};
> -- 
> 2.20.1
> 
> 


- Paul

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  parent reply	other threads:[~2019-11-07 22:32 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-07 21:24 QEMU RISC-V virt machine poweroff driver Christoph Hellwig
2019-11-07 21:24 ` Christoph Hellwig
2019-11-07 21:24 ` [PATCH 1/2] dt-bindings: power: reset: document the QEMU RISC-V virt machine poweroff device Christoph Hellwig
2019-11-07 21:24   ` Christoph Hellwig
2019-11-07 21:52   ` Palmer Dabbelt
2019-11-07 21:52     ` Palmer Dabbelt
2019-11-07 22:32   ` Paul Walmsley [this message]
2019-11-07 22:32     ` Paul Walmsley
2019-11-14  1:44     ` Rob Herring
2019-11-14  1:44       ` Rob Herring
2019-11-07 21:24 ` [PATCH 2/2] power: reset: add a QEMU RISC-V virt machine poweroff driver Christoph Hellwig
2019-11-07 21:24   ` Christoph Hellwig
2019-11-07 21:53   ` Palmer Dabbelt
2019-11-07 21:53     ` Palmer Dabbelt
2019-11-07 22:33   ` Paul Walmsley
2019-11-07 22:33     ` Paul Walmsley
2019-11-07 21:56 ` Palmer Dabbelt
2019-11-07 21:56   ` Palmer Dabbelt
2019-11-11 11:36 ` Anup Patel
2019-11-11 11:36   ` Anup Patel
2019-11-11 16:12   ` Christoph Hellwig
2019-11-11 16:12     ` Christoph Hellwig
2019-11-11 17:20     ` Paul Walmsley
2019-11-11 17:20       ` Paul Walmsley
2019-11-12  4:16       ` Anup Patel
2019-11-12  4:16         ` Anup Patel
2019-11-14  1:50         ` Rob Herring
2019-11-14  1:50           ` Rob Herring
2019-11-15 22:14 ` Nick Kossifidis
2019-11-15 22:14   ` Nick Kossifidis
2019-11-18  6:12   ` Anup Patel
2019-11-18  6:12     ` Anup Patel

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