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From: Lucas Tanure <tanureal@opensource.cirrus.com>
To: James Schulman <james.schulman@cirrus.com>,
	David Rhodes <david.rhodes@cirrus.com>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
	Takashi Iwai <tiwai@suse.com>
Cc: patches@opensource.cirrus.com,
	Richard Fitzgerald <rf@opensource.cirrus.com>,
	alsa-devel@alsa-project.org,
	Lucas Tanure <tanureal@opensource.cirrus.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 02/15] ASoC: cs42l42: Fix channel width support
Date: Fri, 5 Mar 2021 17:34:29 +0000	[thread overview]
Message-ID: <20210305173442.195740-3-tanureal@opensource.cirrus.com> (raw)
In-Reply-To: <20210305173442.195740-1-tanureal@opensource.cirrus.com>

Remove the hard coded 32 bits width and replace with the correct width
calculated by params_width.

Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
---
Changes in v2:
- No changes

 sound/soc/codecs/cs42l42.c | 47 ++++++++++++++++++--------------------
 sound/soc/codecs/cs42l42.h |  1 -
 2 files changed, 22 insertions(+), 26 deletions(-)

diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index df0d5fec0287a..4f9ad95479292 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -691,24 +691,6 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
 					CS42L42_CLK_OASRC_SEL_MASK,
 					CS42L42_CLK_OASRC_SEL_12 <<
 					CS42L42_CLK_OASRC_SEL_SHIFT);
-			/* channel 1 on low LRCLK, 32 bit */
-			snd_soc_component_update_bits(component,
-					CS42L42_ASP_RX_DAI0_CH1_AP_RES,
-					CS42L42_ASP_RX_CH_AP_MASK |
-					CS42L42_ASP_RX_CH_RES_MASK,
-					(CS42L42_ASP_RX_CH_AP_LOW <<
-					CS42L42_ASP_RX_CH_AP_SHIFT) |
-					(CS42L42_ASP_RX_CH_RES_32 <<
-					CS42L42_ASP_RX_CH_RES_SHIFT));
-			/* Channel 2 on high LRCLK, 32 bit */
-			snd_soc_component_update_bits(component,
-					CS42L42_ASP_RX_DAI0_CH2_AP_RES,
-					CS42L42_ASP_RX_CH_AP_MASK |
-					CS42L42_ASP_RX_CH_RES_MASK,
-					(CS42L42_ASP_RX_CH_AP_HI <<
-					CS42L42_ASP_RX_CH_AP_SHIFT) |
-					(CS42L42_ASP_RX_CH_RES_32 <<
-					CS42L42_ASP_RX_CH_RES_SHIFT));
 			if (pll_ratio_table[i].mclk_src_sel == 0) {
 				/* Pass the clock straight through */
 				snd_soc_component_update_bits(component,
@@ -824,14 +806,29 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 {
 	struct snd_soc_component *component = dai->component;
 	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
-	int retval;
+	unsigned int width = (params_width(params) / 8) - 1;
+	unsigned int val = 0;
 
 	cs42l42->srate = params_rate(params);
-	cs42l42->swidth = params_width(params);
 
-	retval = cs42l42_pll_config(component);
+	switch(substream->stream) {
+	case SNDRV_PCM_STREAM_PLAYBACK:
+		val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
+		/* channel 1 on low LRCLK */
+		snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
+							 CS42L42_ASP_RX_CH_AP_MASK |
+							 CS42L42_ASP_RX_CH_RES_MASK, val);
+		/* Channel 2 on high LRCLK */
+		val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
+		snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
+							 CS42L42_ASP_RX_CH_AP_MASK |
+							 CS42L42_ASP_RX_CH_RES_MASK, val);
+		break;
+	default:
+		break;
+	}
 
-	return retval;
+	return cs42l42_pll_config(component);
 }
 
 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
@@ -896,9 +893,9 @@ static int cs42l42_mute(struct snd_soc_dai *dai, int mute, int direction)
 	return 0;
 }
 
-#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
-			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
-			SNDRV_PCM_FMTBIT_S32_LE)
+#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+			 SNDRV_PCM_FMTBIT_S24_LE |\
+			 SNDRV_PCM_FMTBIT_S32_LE )
 
 
 static const struct snd_soc_dai_ops cs42l42_ops = {
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h
index 1f0d67c95a9ad..9b017b76828a4 100644
--- a/sound/soc/codecs/cs42l42.h
+++ b/sound/soc/codecs/cs42l42.h
@@ -757,7 +757,6 @@ struct  cs42l42_private {
 	struct completion pdn_done;
 	u32 sclk;
 	u32 srate;
-	u32 swidth;
 	u8 plug_state;
 	u8 hs_type;
 	u8 ts_inv;
-- 
2.30.1


  parent reply	other threads:[~2021-03-05 17:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-05 17:34 [PATCH v2 00/15] Report jack and button detection + Capture Support Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 01/15] ASoC: cs42l42: Fix Bitclock polarity inversion Lucas Tanure
2021-03-05 17:34 ` Lucas Tanure [this message]
2021-03-05 17:34 ` [PATCH v2 03/15] ASoC: cs42l42: Fix mixer volume control Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 04/15] ASoC: cs42l42: Don't enable/disable regulator at Bias Level Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 05/15] ASoC: cs42l42: Always wait at least 3ms after reset Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 06/15] ASoC: cs42l42: Remove power if the driver is being removed Lucas Tanure
2021-03-05 18:49   ` Mark Brown
2021-03-05 17:34 ` [PATCH v2 07/15] ASoC: cs42l42: Disable regulators if probe fails Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 08/15] ASoC: cs42l42: Provide finer control on playback path Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 09/15] ASoC: cs42l42: Set clock source for both ways of stream Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 10/15] ASoC: cs42l42: Add Capture Support Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 11/15] ASoC: cs42l42: Report jack and button detection Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 12/15] ASoC: cs42l42: Use bclk from hw_params if set_sysclk was not called Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 13/15] ASoC: cs42l42: Wait at least 150us after writing SCLK_PRESENT Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 14/15] ASoC: cs42l42: Only start PLL if it is needed Lucas Tanure
2021-03-05 17:34 ` [PATCH v2 15/15] ASoC: cs42l42: Wait for PLL to lock before switching to it Lucas Tanure
2021-03-08 16:06 ` (subset) [PATCH v2 00/15] Report jack and button detection + Capture Support Mark Brown

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