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From: Maxime Ripard <maxime@cerno.tech>
To: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Cc: "Ulf Hansson" <ulf.hansson@linaro.org>,
	"Prashant Gaikwad" <pgaikwad@nvidia.com>,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
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Subject: Re: [PATCH v2 56/65] clk: ingenic: cgu: Switch to determine_rate
Date: Mon, 7 Nov 2022 09:54:17 +0100	[thread overview]
Message-ID: <20221107085417.xrsh6xy3ouwdkp4z@houat> (raw)
In-Reply-To: <cp7Yh29ndlOOi1yW8KwCcpzoLPLxm1vR@localhost>

Hi,

On Fri, Nov 04, 2022 at 05:35:29PM +0000, Aidan MacDonald wrote:
> 
> Maxime Ripard <maxime@cerno.tech> writes:
> 
> > Hi Paul,
> >
> > On Fri, Nov 04, 2022 at 02:31:20PM +0000, Paul Cercueil wrote:
> >> Le ven. 4 nov. 2022 à 14:18:13 +0100, Maxime Ripard <maxime@cerno.tech> a
> >> écrit :
> >> > The Ingenic CGU clocks implements a mux with a set_parent hook, but
> >> > doesn't provide a determine_rate implementation.
> >> >
> >> > This is a bit odd, since set_parent() is there to, as its name implies,
> >> > change the parent of a clock. However, the most likely candidate to
> >> > trigger that parent change is a call to clk_set_rate(), with
> >> > determine_rate() figuring out which parent is the best suited for a
> >> > given rate.
> >> >
> >> > The other trigger would be a call to clk_set_parent(), but it's far less
> >> > used, and it doesn't look like there's any obvious user for that clock.
> >> >
> >> > So, the set_parent hook is effectively unused, possibly because of an
> >> > oversight. However, it could also be an explicit decision by the
> >> > original author to avoid any reparenting but through an explicit call to
> >> > clk_set_parent().
> >> >
> >> > The driver does implement round_rate() though, which means that we can
> >> > change the rate of the clock, but we will never get to change the
> >> > parent.
> >> >
> >> > However, It's hard to tell whether it's been done on purpose or not.
> >> >
> >> > Since we'll start mandating a determine_rate() implementation, let's
> >> > convert the round_rate() implementation to a determine_rate(), which
> >> > will also make the current behavior explicit. And if it was an
> >> > oversight, the clock behaviour can be adjusted later on.
> >>
> >> So it's partly on purpose, partly because I didn't know about
> >> .determine_rate.
> >>
> >> There's nothing odd about having a lonely .set_parent callback; in my case
> >> the clocks are parented from the device tree.
> >>
> >> Having the clocks driver trigger a parent change when requesting a rate
> >> change sounds very dangerous, IMHO. My MMC controller can be parented to the
> >> external 48 MHz oscillator, and if the card requests 50 MHz, it could switch
> >> to one of the PLLs. That works as long as the PLLs don't change rate, but if
> >> one is configured as driving the CPU clock, it becomes messy.
> >> The thing is, the clocks driver has no way to know whether or not it is
> >> "safe" to use a designated parent.
> >>
> >> For that reason, in practice, I never actually want to have a clock
> >> re-parented - it's almost always a bad idea vs. sticking to the parent clock
> >> configured in the DTS.
> >
> > Yeah, and this is totally fine. But we need to be explicit about it. The
> > determine_rate implementation I did in all the patches is an exact
> > equivalent to the round_rate one if there was one. We will never ask to
> > change the parent.
> >
> > Given what you just said, I would suggest to set the
> > CLK_SET_RATE_NO_REPARENT flag as well.
>
> Ideally there should be a way for drivers and the device tree to
> say, "clock X must be driven by clock Y", but the clock framework
> would be allowed to re-parent clocks freely as long as it doesn't
> violate any DT or driver constraints.

I'm not really sure what you mean there, sorry. Isn't it what
assigned-clock-parents/clk_set_parent() at probe, plus a determine_rate
implementation that would affect best_parent_hw would already provide?

> That way allowing reparenting doesn't need to be an all-or-nothing
> thing, and it doesn't need to be decided at the clock driver level
> with special flags.

Like I said, the default implementation is already working to what you
suggested if I understood properly. However, this has never been tested
for any of the drivers in that series so I don't want to introduce (and
debug ;)) regressions in all those drivers that were not setting any
constraint but never actually tested their reparenting code.

So that series is strictly equivalent to what you had before, it's just
explicit now.

If you find that some other decision make sense for your driver in
particular cases, feel free to change it. I barely know most of these
platforms, so I won't be able to make that decision (and test it)
unfortunately.

Maxime

  reply	other threads:[~2022-11-09 17:22 UTC|newest]

Thread overview: 115+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-04 13:17 [PATCH v2 00/65] clk: Make determine_rate mandatory for muxes Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 01/65] clk: Export clk_hw_forward_rate_request() Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 02/65] clk: lan966x: Remove unused round_rate hook Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 03/65] clk: nodrv: Add a determine_rate hook Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 04/65] clk: test: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 05/65] clk: actions: composite: Add a determine_rate hook for pass clk Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 06/65] clk: at91: main: Add a determine_rate hook Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 07/65] clk: at91: sckc: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 08/65] clk: berlin: div: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 09/65] clk: cdce706: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 10/65] clk: k210: pll: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 11/65] clk: k210: aclk: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 12/65] clk: k210: mux: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 13/65] clk: lmk04832: clkout: " Maxime Ripard
2022-11-13 22:35   ` Liam Beguin
2022-11-04 13:17 ` [PATCH v2 14/65] clk: lochnagar: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 15/65] clk: qoriq: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 16/65] clk: si5341: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 17/65] clk: stm32f4: mux: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 18/65] clk: vc5: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 19/65] clk: vc5: clkout: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 20/65] clk: wm831x: " Maxime Ripard
2022-11-07 10:58   ` Charles Keepax
2022-11-04 13:17 ` [PATCH v2 21/65] clk: davinci: da8xx-cfgchip: " Maxime Ripard
2022-11-04 16:45   ` David Lechner
2022-11-07 12:06     ` Maxime Ripard
2022-11-07 14:52       ` David Lechner
2022-11-04 13:17 ` [PATCH v2 22/65] " Maxime Ripard
2022-11-04 16:46   ` David Lechner
2022-11-04 13:17 ` [PATCH v2 23/65] clk: imx: busy: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 24/65] clk: imx: fixup-mux: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 25/65] clk: imx: scu: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 26/65] clk: mediatek: cpumux: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 27/65] clk: pxa: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 28/65] clk: renesas: r9a06g032: " Maxime Ripard
2022-11-07  7:51   ` Geert Uytterhoeven
2022-11-04 13:17 ` [PATCH v2 29/65] clk: socfpga: gate: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 30/65] clk: stm32: core: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 31/65] clk: tegra: bpmp: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 32/65] clk: tegra: super: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 33/65] clk: tegra: periph: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 34/65] clk: ux500: prcmu: " Maxime Ripard
2022-11-08 13:25   ` Linus Walleij
2022-11-09 11:05     ` Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 35/65] clk: ux500: sysctrl: " Maxime Ripard
2022-11-08 13:27   ` Linus Walleij
2022-11-10 11:28   ` Ulf Hansson
2022-11-10 11:39     ` Linus Walleij
2022-11-10 13:05       ` Ulf Hansson
2022-11-11  9:20         ` Linus Walleij
2022-11-14  9:05           ` Lee Jones
2022-11-04 13:17 ` [PATCH v2 36/65] clk: versatile: sp810: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 37/65] drm/tegra: sor: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 38/65] phy: cadence: sierra: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 39/65] phy: cadence: torrent: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 40/65] phy: ti: am654-serdes: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 41/65] phy: ti: j721e-wiz: " Maxime Ripard
2022-11-04 13:17 ` [PATCH v2 42/65] rtc: sun6i: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 43/65] ASoC: tlv320aic32x4: " Maxime Ripard
2022-11-04 15:44   ` Mark Brown
2022-11-04 15:51     ` Maxime Ripard
2022-11-04 15:59       ` Mark Brown
2022-11-07  8:43         ` Maxime Ripard
2022-11-07 12:06           ` Mark Brown
2022-11-07 15:26             ` Maxime Ripard
2022-11-07 16:02               ` Mark Brown
2023-03-22 23:31               ` Stephen Boyd
2023-03-29 19:50                 ` Maxime Ripard
2023-03-29 20:04                   ` Stephen Boyd
2022-11-04 13:18 ` [PATCH v2 44/65] clk: actions: composite: div: Switch to determine_rate Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 45/65] clk: actions: composite: fact: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 46/65] clk: at91: smd: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 47/65] clk: axi-clkgen: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 48/65] clk: cdce706: divider: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 49/65] clk: cdce706: clkout: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 50/65] clk: si5341: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 51/65] clk: si5351: pll: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 52/65] clk: si5351: msynth: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 53/65] clk: si5351: clkout: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 54/65] clk: da8xx: clk48: " Maxime Ripard
2022-11-04 16:49   ` David Lechner
2022-11-07 14:52     ` Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 55/65] clk: imx: scu: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 56/65] clk: ingenic: cgu: " Maxime Ripard
2022-11-04 14:31   ` Paul Cercueil
2022-11-04 14:59     ` Maxime Ripard
2022-11-04 17:35       ` Aidan MacDonald
2022-11-07  8:54         ` Maxime Ripard [this message]
2022-11-07 20:57           ` Aidan MacDonald
2022-11-09 11:00             ` Maxime Ripard
2023-03-22 23:41               ` Stephen Boyd
2023-03-23 15:35                 ` Aidan MacDonald
2023-03-24 11:19                   ` Maxime Ripard
2023-03-24 20:58                     ` Aidan MacDonald
2023-03-27 19:24                       ` Maxime Ripard
2023-04-05 12:57                         ` Paul Cercueil
2023-04-05 14:50                           ` Maxime Ripard
2023-04-05 15:29                             ` Paul Cercueil
2022-11-05 10:33       ` Paul Cercueil
2022-11-09 10:53         ` Maxime Ripard
2022-11-09 11:36           ` Paul Cercueil
2022-11-04 13:18 ` [PATCH v2 57/65] clk: ingenic: tcu: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 58/65] clk: sprd: composite: " Maxime Ripard
2022-11-09  2:43   ` Chunyan Zhang
2022-11-04 13:18 ` [PATCH v2 59/65] clk: st: flexgen: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 60/65] clk: stm32: composite: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 61/65] clk: tegra: periph: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 62/65] clk: tegra: super: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 63/65] ASoC: tlv320aic32x4: pll: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 64/65] ASoC: tlv320aic32x4: div: " Maxime Ripard
2022-11-04 13:18 ` [PATCH v2 65/65] clk: Warn if we register a mux without determine_rate Maxime Ripard
2022-11-07 10:56   ` Charles Keepax
2023-03-21 23:55 ` [PATCH v2 00/65] clk: Make determine_rate mandatory for muxes Stephen Boyd
2023-03-22 10:01   ` Maxime Ripard
2023-03-22 15:19     ` Stephen Boyd

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