From: "Sit, Michael Wei Hong" <michael.wei.hong.sit@intel.com>
To: "Sia, Jee Heng" <jee.heng.sia@intel.com>,
"Shevchenko, Andriy" <andriy.shevchenko@intel.com>,
"pierre-louis.bossart@linux.intel.com"
<pierre-louis.bossart@linux.intel.com>,
"Rojewski, Cezary" <cezary.rojewski@intel.com>,
"liam.r.girdwood@linux.intel.com"
<liam.r.girdwood@linux.intel.com>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"tiwai@suse.com" <tiwai@suse.com>,
"broonie@kernel.org" <broonie@kernel.org>
Cc: "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
"lars@metafoo.de" <lars@metafoo.de>
Subject: RE: [RFC PATCH 2/4] ASoC: soc-generic-dmaengine-pcm: Add custom prepare and submit function
Date: Mon, 30 Nov 2020 09:57:01 +0000 [thread overview]
Message-ID: <BYAPR11MB30465A81744EA686D2502DB69DF50@BYAPR11MB3046.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CO1PR11MB5026A81C4294BEF4EE5EF923DAFB0@CO1PR11MB5026.namprd11.prod.outlook.com>
> -----Original Message-----
> From: Sia, Jee Heng <jee.heng.sia@intel.com>
> Sent: Tuesday, 24 November, 2020 11:51 AM
> To: Shevchenko, Andriy <andriy.shevchenko@intel.com>
> Cc: Sit, Michael Wei Hong <michael.wei.hong.sit@intel.com>;
> alsa-devel@alsa-project.org; tiwai@suse.com;
> broonie@kernel.org; pierre-louis.bossart@linux.intel.com;
> Rojewski, Cezary <cezary.rojewski@intel.com>;
> liam.r.girdwood@linux.intel.com; vkoul@kernel.org;
> lars@metafoo.de
> Subject: RE: [RFC PATCH 2/4] ASoC: soc-generic-dmaengine-pcm:
> Add custom prepare and submit function
>
>
>
> > -----Original Message-----
> > From: Shevchenko, Andriy <andriy.shevchenko@intel.com>
> > Sent: 18 November 2020 10:51 PM
> > To: Sia, Jee Heng <jee.heng.sia@intel.com>
> > Cc: Sit, Michael Wei Hong <michael.wei.hong.sit@intel.com>;
> > alsa-devel@alsa- project.org; tiwai@suse.com;
> broonie@kernel.org;
> > pierre- louis.bossart@linux.intel.com; Rojewski, Cezary
> > <cezary.rojewski@intel.com>; liam.r.girdwood@linux.intel.com;
> > vkoul@kernel.org; lars@metafoo.de
> > Subject: Re: [RFC PATCH 2/4] ASoC: soc-generic-dmaengine-
> pcm: Add
> > custom prepare and submit function
> >
> > On Wed, Nov 18, 2020 at 02:34:22AM +0200, Sia, Jee Heng
> wrote:
> > > > From: Andy Shevchenko <andriy.shevchenko@intel.com>
> > > > Sent: 17 November 2020 11:51 PM
> > > > On Tue, Nov 17, 2020 at 04:03:48PM +0800, Michael Sit Wei
> Hong wrote:
> > > > > Enabling custom prepare and submit function to
> overcome DMA limitation.
> > > > >
> > > > > In the Intel KeemBay solution, the DW AXI-based DMA
> has a
> > > > > limitation on the number of DMA blocks per transfer. In
> the case
> > > > > of 16 bit audio ASoC would allocate blocks exceeding the
> DMA block limitation.
> > > >
> > > > I'm still not sure the hardware has such a limitation.
> > > >
> > > > The Synopsys IP supports linked list (LLI) transfers and I
> hardly
> > > > can imagine the list has any limitation. Even though, one can
> > > > always emulate LLI in software how it's done in the
> DesignWare AHB DMA driver.
> > > >
> > > > I have briefly read chapter 4.6 "AXI_DMA" of Keem Bay TRM
> and
> > > > didn't find any errata or limits like this.
> > > [>>] Intel KeemBay datasheet can be found at below link:
> > >
> https://www.intel.com/content/www/us/en/secure/design/con
> fidential/p
> > > ro
> > > ducts-and-solutions/processors-and-chipsets/keem-
> bay/technical-libra
> > > ry .html?grouping=EMT_Content%20Type&sort=title:asc
> > > Pg783, "Programmable transfer length (block length), max
> 1024".
> > > Sub-list can't
> > exceed 1024 blocks.
> > > BTW, I think the 16bits audio could be a confusion because it is
> not
> > > about the
> > number of bits, but rather the constraint of the block length.
> Base on
> > my understanding, Audio needs a period larger than 10ms,
> regardless of the bit depth.
> > > The questions here are:
> > > 1. Should DMAEngine expose a new API to constraint the
> block_length
> > > (instead of
> > size in bytes)?
> > > 2. Should DMA client re-split the linked-list before passing the
> > > linked-list to
> > DMAEngine.
> > > 3. Should DMA controller driver re-split the linked-list before
> execution.
> >
> > Since we have DMA slave capabilities, the consumer may ask
> for them
> > and prepare the SG list accordingly.
> >
> > Above limitation is a block size (value of 1023 is a maximum,
> meaning
> > 1024 maximum items in the block of given transfer width). So,
> like
> > DesignWare DMA
> > (AHB) has up to 4095 (but I saw hardware with 2047) or iDMA
> 32- and
> > 64-bit have 131071. There is no limitation for amount of blocks
> of
> > given maximum length in the LLI!
> >
> > No hacks are needed, really.
> [>>] Hi All, can we have the agreement that DMA clients should
> optimize the linked-list [>>] by retrieve the DMA capabilities from
> the DMA controller?
> [>>] I noticed that Vinod voted #3 but Andy voted #2.
> [>>] We need your decision to move on.
> >
> > --
> > With Best Regards,
> > Andy Shevchenko
> >
Hi everyone,
Is there anymore comment on this RFC?
We will be using the ASoC framework to split the linked-list, since resplitting the linked-list in DMA is a no go.
If there isn't any more comments, we will push these patches for review and merging.
Thanks,
Regards,
Michael
next prev parent reply other threads:[~2020-11-30 9:58 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-17 8:03 [RFC PATCH 0/4] Enable DMA mode on Intel Keem Bay platform Michael Sit Wei Hong
2020-11-17 8:03 ` [RFC PATCH 1/4] dt-bindings: sound: intel, keembay-i2s: Add info for device to use DMA Michael Sit Wei Hong
2020-11-17 8:03 ` [RFC PATCH 2/4] ASoC: soc-generic-dmaengine-pcm: Add custom prepare and submit function Michael Sit Wei Hong
2020-11-17 13:56 ` Vinod Koul
2020-11-17 15:50 ` Andy Shevchenko
2020-11-18 0:34 ` Sia, Jee Heng
2020-11-18 4:40 ` Vinod Koul
2020-11-18 5:27 ` Sia, Jee Heng
2020-11-18 14:50 ` Shevchenko, Andriy
2020-11-24 3:51 ` Sia, Jee Heng
2020-11-30 9:57 ` Sit, Michael Wei Hong [this message]
2020-11-30 10:45 ` Lars-Peter Clausen
2020-11-30 11:09 ` Shevchenko, Andriy
2020-12-01 8:22 ` Lars-Peter Clausen
2020-12-01 9:10 ` Sia, Jee Heng
2020-12-05 0:55 ` Sit, Michael Wei Hong
2020-12-07 10:05 ` Lars-Peter Clausen
2020-12-07 15:36 ` Pierre-Louis Bossart
2020-12-08 3:21 ` Sia, Jee Heng
2020-12-10 8:24 ` Sit, Michael Wei Hong
2020-12-14 3:23 ` Sit, Michael Wei Hong
2020-11-17 8:03 ` [RFC PATCH 3/4] ASoC: dmaengine_pcm: expose functions to header file for custom functions Michael Sit Wei Hong
2020-11-17 8:03 ` [RFC PATCH 4/4] ASoC: Intel: KMB: Enable DMA transfer mode Michael Sit Wei Hong
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