From: Paul Cercueil <paul@crapouillou.net>
To: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Cc: alsa-devel@alsa-project.org, Zhou Yanjie <zhouyu@wanyeetech.com>,
lgirdwood@gmail.com, linux-kernel@vger.kernel.org,
tiwai@suse.com, linux-mips@vger.kernel.org, broonie@kernel.org
Subject: Re: [PATCH v4 07/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific
Date: Sat, 22 Oct 2022 21:03:53 +0100 [thread overview]
Message-ID: <HQ76KR.B1PM87E2GIYZ1@crapouillou.net> (raw)
In-Reply-To: <UQ597w4FmzOT8p76tdRPhzECStUpFmYe@localhost>
Hi Aidan,
Le sam. 22 oct. 2022 à 18:15:05 +0100, Aidan MacDonald
<aidanmacdonald.0x0@gmail.com> a écrit :
>
> Zhou Yanjie <zhouyu@wanyeetech.com> writes:
>
>> Hi Paul,
>>
>> On 2022/7/13 下午11:07, Paul Cercueil wrote:
>>> Hi Zhou,
>>>
>>> Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie
>>> <zhouyu@wanyeetech.com>
>>> a écrit :
>>>> Hi Aidan,
>>>>
>>>> On 2022/7/9 上午12:02, Aidan MacDonald wrote:
>>>>> @@ -400,6 +402,7 @@ static const struct i2s_soc_info
>>>>> jz4740_i2s_soc_info =
>>>>> {
>>>>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8,
>>>>> 11),
>>>>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV,
>>>>> 0, 3),
>>>>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV,
>>>>> 0, 3),
>>>>> + .pll_clk_name = "pll half",
>>>>> .shared_fifo_flush = true,
>>>>> };
>>>>
>>>>
>>>> Since JZ4760, according to the description of the I2SCDR register,
>>>> Ingenic SoCs no longer use PLL/2 clock, but directly use PLL
>>>> clock,
>>>> so it seems also inappropriate to use "pll half" for these SoCs.
>>>
>>> The device tree passes the clock as "pll half". So the driver
>>> should use this
>>> name as well...
>>
>>
>> I see...
>>
>> It seems that the device tree of JZ4770 has used "pll half" already,
>> but there is no "pll half" used anywhere in the device tree of
>> JZ4780,
>> maybe we can keep the pll_clk_name of JZ4770 as "pll half", and
>> change
>> the pll_clk_name of JZ4780 to a more reasonable name.
>>
>>
>> Thanks and best regards!
>
> Actually, the clock names in the DT are meaningless. The clk_get()
> call
> matches only the clock's name in the CGU driver. So in fact the driver
> is "broken" for jz4780. It seems jz4770 doesn't work correctly either,
> it has no "pll half", and three possible parents for its "i2s" clock.
That's not true. The clock names are matched via DT.
Only in the case where a corresponding clock cannot be found via DT
will it search for the clock name among the clock providers. I believe
this is a legacy mechanism and you absolutely shouldn't rely on it.
-Paul
> Since the driver only supports the internal codec, which requires the
> "ext" clock, there isn't a problem in practice.
>
> I'm just going to drop this patch and leave .set_sysclk() alone for
> now.
> I think a better approach is to have the DT define an array of parent
> clocks for .set_sysclk()'s use, instead of hardcoding parents in the
> driver. If the parent array is missing the driver can default to using
> "ext" so existing DTs will work.
>
> Regards,
> Aidan
next prev parent reply other threads:[~2022-10-22 20:05 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-08 16:02 [PATCH v4 00/11] ASoC: cleanups and improvements for jz4740-i2s Aidan MacDonald
2022-07-08 16:02 ` [PATCH v4 01/11] ASoC: jz4740-i2s: Handle independent FIFO flush bits Aidan MacDonald
2022-07-20 11:44 ` Paul Cercueil
2022-07-20 14:43 ` Aidan MacDonald
2022-07-21 10:08 ` Paul Cercueil
2022-10-22 15:43 ` Aidan MacDonald
2022-07-08 16:02 ` [PATCH v4 02/11] ASoC: jz4740-i2s: Remove unused 'mem' resource Aidan MacDonald
2022-07-20 11:44 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 03/11] ASoC: jz4740-i2s: Convert to regmap API Aidan MacDonald
2022-07-20 12:05 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 04/11] ASoC: jz4740-i2s: Simplify using regmap fields Aidan MacDonald
2022-07-20 11:50 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 05/11] ASoC: jz4740-i2s: Use FIELD_PREP() macros in hw_params callback Aidan MacDonald
2022-07-20 11:52 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 06/11] ASoC: jz4740-i2s: Align macro values and sort includes Aidan MacDonald
2022-07-08 16:02 ` [PATCH v4 07/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific Aidan MacDonald
2022-07-13 14:33 ` Zhou Yanjie
2022-07-13 15:07 ` Paul Cercueil
2022-07-13 15:29 ` Zhou Yanjie
2022-10-22 17:15 ` Aidan MacDonald
2022-10-22 20:03 ` Paul Cercueil [this message]
2022-10-23 13:29 ` Aidan MacDonald
2022-10-24 13:06 ` Paul Cercueil
2022-10-25 9:20 ` Aidan MacDonald
2022-07-20 11:53 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 08/11] ASoC: jz4740-i2s: Support S20_LE and S24_LE sample formats Aidan MacDonald
2022-07-20 11:56 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 09/11] ASoC: jz4740-i2s: Support continuous sample rate Aidan MacDonald
2022-07-08 16:02 ` [PATCH v4 10/11] ASoC: jz4740-i2s: Move component functions near the component driver Aidan MacDonald
2022-07-20 11:58 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 11/11] ASoC: jz4740-i2s: Refactor DAI probe/remove ops as component ops Aidan MacDonald
2022-07-20 12:04 ` Paul Cercueil
2022-07-20 23:12 ` (subset) [PATCH v4 00/11] ASoC: cleanups and improvements for jz4740-i2s Mark Brown
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