From: Paul Cercueil <paul@crapouillou.net>
To: Zhou Yanjie <zhouyu@wanyeetech.com>
Cc: alsa-devel@alsa-project.org,
Aidan MacDonald <aidanmacdonald.0x0@gmail.com>,
lgirdwood@gmail.com, linux-kernel@vger.kernel.org,
tiwai@suse.com, linux-mips@vger.kernel.org, broonie@kernel.org
Subject: Re: [PATCH v4 07/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific
Date: Wed, 13 Jul 2022 16:07:39 +0100 [thread overview]
Message-ID: <ROSYER.QTJF8J14H2YX1@crapouillou.net> (raw)
In-Reply-To: <0269b850-f33a-7aa9-a3eb-83655bd4e19a@wanyeetech.com>
Hi Zhou,
Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie
<zhouyu@wanyeetech.com> a écrit :
> Hi Aidan,
>
> On 2022/7/9 上午12:02, Aidan MacDonald wrote:
>> On some Ingenic SoCs, such as the X1000, there is a programmable
>> divider used to generate the I2S system clock from a PLL, rather
>> than a fixed PLL/2 clock. It doesn't make much sense to call the
>> clock "pll half" on those SoCs, so the clock name should really be
>> a SoC-dependent value.
>>
>> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
>> ---
>> sound/soc/jz4740/jz4740-i2s.c | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/sound/soc/jz4740/jz4740-i2s.c
>> b/sound/soc/jz4740/jz4740-i2s.c
>> index 0dcc658b3784..a41398c24d0e 100644
>> --- a/sound/soc/jz4740/jz4740-i2s.c
>> +++ b/sound/soc/jz4740/jz4740-i2s.c
>> @@ -75,6 +75,8 @@ struct i2s_soc_info {
>> struct reg_field field_i2sdiv_capture;
>> struct reg_field field_i2sdiv_playback;
>> \x7f+ const char *pll_clk_name;
>> +
>> bool shared_fifo_flush;
>> };
>> \x7f@@ -281,7 +283,7 @@ static int jz4740_i2s_set_sysclk(struct
>> snd_soc_dai *dai, int clk_id,
>> clk_set_parent(i2s->clk_i2s, parent);
>> break;
>> case JZ4740_I2S_CLKSRC_PLL:
>> - parent = clk_get(NULL, "pll half");
>> + parent = clk_get(NULL, i2s->soc_info->pll_clk_name);
>> if (IS_ERR(parent))
>> return PTR_ERR(parent);
>> clk_set_parent(i2s->clk_i2s, parent);
>> @@ -400,6 +402,7 @@ static const struct i2s_soc_info
>> jz4740_i2s_soc_info = {
>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11),
>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
>> + .pll_clk_name = "pll half",
>> .shared_fifo_flush = true,
>> };
>> \x7f@@ -409,6 +412,7 @@ static const struct i2s_soc_info
>> jz4760_i2s_soc_info = {
>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
>> + .pll_clk_name = "pll half",
>> };
>
>
> Since JZ4760, according to the description of the I2SCDR register,
> Ingenic SoCs no longer use PLL/2 clock, but directly use PLL clock,
> so it seems also inappropriate to use "pll half" for these SoCs.
The device tree passes the clock as "pll half". So the driver should
use this name as well...
Cheers,
-Paul
>> \x7f static struct snd_soc_dai_driver jz4770_i2s_dai = {
>> @@ -435,6 +439,7 @@ static const struct i2s_soc_info
>> jz4770_i2s_soc_info = {
>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11),
>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
>> + .pll_clk_name = "pll half",
>> };
>
>
> Same here.
>
>
>> \x7f static const struct i2s_soc_info jz4780_i2s_soc_info = {
>> @@ -443,6 +448,7 @@ static const struct i2s_soc_info
>> jz4780_i2s_soc_info = {
>> .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
>> .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11),
>> .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
>> + .pll_clk_name = "pll half",
>> };
>>
>
> Same here.
>
>
> Thanks and best regards!
>
>
>> static const struct snd_soc_component_driver jz4740_i2s_component
>> = {
next prev parent reply other threads:[~2022-07-13 15:08 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-08 16:02 [PATCH v4 00/11] ASoC: cleanups and improvements for jz4740-i2s Aidan MacDonald
2022-07-08 16:02 ` [PATCH v4 01/11] ASoC: jz4740-i2s: Handle independent FIFO flush bits Aidan MacDonald
2022-07-20 11:44 ` Paul Cercueil
2022-07-20 14:43 ` Aidan MacDonald
2022-07-21 10:08 ` Paul Cercueil
2022-10-22 15:43 ` Aidan MacDonald
2022-07-08 16:02 ` [PATCH v4 02/11] ASoC: jz4740-i2s: Remove unused 'mem' resource Aidan MacDonald
2022-07-20 11:44 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 03/11] ASoC: jz4740-i2s: Convert to regmap API Aidan MacDonald
2022-07-20 12:05 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 04/11] ASoC: jz4740-i2s: Simplify using regmap fields Aidan MacDonald
2022-07-20 11:50 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 05/11] ASoC: jz4740-i2s: Use FIELD_PREP() macros in hw_params callback Aidan MacDonald
2022-07-20 11:52 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 06/11] ASoC: jz4740-i2s: Align macro values and sort includes Aidan MacDonald
2022-07-08 16:02 ` [PATCH v4 07/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific Aidan MacDonald
2022-07-13 14:33 ` Zhou Yanjie
2022-07-13 15:07 ` Paul Cercueil [this message]
2022-07-13 15:29 ` Zhou Yanjie
2022-10-22 17:15 ` Aidan MacDonald
2022-10-22 20:03 ` Paul Cercueil
2022-10-23 13:29 ` Aidan MacDonald
2022-10-24 13:06 ` Paul Cercueil
2022-10-25 9:20 ` Aidan MacDonald
2022-07-20 11:53 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 08/11] ASoC: jz4740-i2s: Support S20_LE and S24_LE sample formats Aidan MacDonald
2022-07-20 11:56 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 09/11] ASoC: jz4740-i2s: Support continuous sample rate Aidan MacDonald
2022-07-08 16:02 ` [PATCH v4 10/11] ASoC: jz4740-i2s: Move component functions near the component driver Aidan MacDonald
2022-07-20 11:58 ` Paul Cercueil
2022-07-08 16:02 ` [PATCH v4 11/11] ASoC: jz4740-i2s: Refactor DAI probe/remove ops as component ops Aidan MacDonald
2022-07-20 12:04 ` Paul Cercueil
2022-07-20 23:12 ` (subset) [PATCH v4 00/11] ASoC: cleanups and improvements for jz4740-i2s Mark Brown
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